JPS62235777A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To readily miniaturize a pattern indispensable to improve high frequency characteristic of a semiconductor device by selectively forming a second polycrystalline silicon film doped with a P-type impurity in high density without masking step, and then thermally diffusing to form a base contact region. CONSTITUTION:A polycrystalline Si film 3 and an insulating film 4 are laminated on a one conductivity type epitaxial layer 1, and one conductivity type impurity ions and reverse conductivity type impurity ions are so implanted into the film 3 as to arrive at a deeper portion of the latter than the former. After a predetermined region of the films 4, 3 and the layer 1 is then anisotropically etched, a second insulating film 5 is deposited on the exposed surfaces of the films 4, 3 and the layer 1, and anisotropically etched to allow only a sidewall to remain. Then, a second polycrystalline Si film 6 doped in high density with a reverse conductivity type impurity is deposited, anisotropically etched to allow it to remain on the sidewall of the film 5. Then, the impurities in the films 3, 6 are simultaneously diffused in the epitaxial layer to form a junction, and the region 8 diffused from the film 3 and a reverse conductivity type impurity region 9 diffused from the film 6 are contacted in the layer 1.

Description

DETAILED DESCRIPTION OF THE INVENTION 31\-2' Field of Industrial Application The present invention relates to a semiconductor device, particularly to a method for manufacturing a bipolar transistor having a self-aligned base contact with an emitter.

Conventional technology Conventionally, in order to realize bipolar transistors with excellent high frequency characteristics and integrated circuits using the transistors, N
It is common practice to form the emitter region of a PN transistor into a mesa structure.

Figure 2 shows its configuration. In FIG. 2, 1 is an N-type epitaxial layer, 2 is a silicon oxide film, 3 is a first polycrystalline silicon film, and 4 is a silicon nitride film.

7 is an N layer (emitter region), 8 is a P layer (active base region), and 9 is a P layer (base contact region).

That is, in FIG. 2, on the surface of the N-type epitaxial layer 1 which becomes the collector region.

After forming a single P layer (active base region) 8 using the silicon oxide film 2 as a mask, a first polycrystalline film selectively doped with arsenic is deposited thereon, and a shallow N layer (active base region) is formed using arsenic as an impurity.
emitter region) 7 in a nitrogen atmosphere at a temperature of 95o to 1ooo.
℃ into the epitaxial layer, and then one layer of P (
A silicon nitride film 4 is deposited by low pressure CVD on the entire surface of the first polycrystalline silicon layer on the silicon oxide film 2 and the N layer 7, which serves as a mask for forming the active base region) 8.

Next, the silicon nitride film 4 is etched by an anisotropic dry etching method using a positive type photoresist pattern such as 0FPR-8oo as a mask. Then,
After etching the P layer 8 using the silicon nitride film 4 as a mask to form an N-type emitter region, silicon is etched on the exposed parts of the P layer 8, the N layer 7, and the first polycrystalline silicon film 3 by thermal oxidation. An oxide film 2 is formed. Furthermore, after removing the silicon nitride film 4 by etching with hot phosphoric acid to expose the first polycrystalline silicon film 3 and forming an emitter contact window, a predetermined region of the silicon oxide film 2 on the P layer 8 is etched with photoresist. Using the pattern as a mask, one layer is selectively etched away to form a base contact window, and then, using the photoresist pattern as a mask, ion implantation is performed at an acceleration voltage of 50 to 100 Key and a dose of 1.
~3 x I C3” Boron ion (B) at about Cyn2
After injecting and removing the photoresist pattern by etching,
A P layer (base contact region) 9 is formed by thermal diffusion.

Problems to be Solved by the Invention In such a conventional structure, the emitter contact window of the N layer (emitter region) 7 of the mesa structure can be formed without a mask process, but the emitter contact window of the P layer (base contact region) 9 can be formed without going through a mask process. A mask process is required to form the pattern, and the accuracy of mutual mask alignment must also be taken into account. Therefore, the existence of such a mask process poses a major problem in pattern miniaturization, which is essential for improving high frequency characteristics. It had become.

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the problems in the mask process described above.

Means for Solving the Problems In order to solve the above problems, the present invention provides the following steps: - forming an epitaxial layer of the same conductivity type as the semiconductor substrate on a conductivity type semiconductor substrate; a step of sequentially stacking a first polycrystalline silicon film and a first insulating film, and a step of sequentially laminating a first polycrystalline silicon film and a first insulating film; a step of implanting second impurity ions of a conductivity type opposite to that of the semiconductor substrate so that the second impurity ions reach a deeper part than the first impurity ions, and a step of implanting the first impurity ions by a known photolithography method. a step of selectively anisotropically etching a predetermined region of an insulating film, the first polycrystalline silicon film, and a part of the epitaxial layer directly below the first insulating film and the first polycrystalline silicon film; Depositing a second insulating film on the exposed surface of the silicon film and the epitaxial layer, and anisotropically etching the second insulating film to form the first polycrystalline silicon film and the epitaxial layer immediately below it. a second insulating film doped with impurities of a conductivity type opposite to that of the semiconductor substrate at a high concentration on exposed surfaces of the first insulating film, the second insulating film, and the epitaxial layer; evaporate a polycrystalline silicon film of
forming the seventh polycrystalline silicon film on the exposed sidewall surface of the second insulating film and a part of the exposed surface of the epitaxial layer by anisotropic etching;
An impurity of the same conductivity type as the semiconductor substrate in the first polycrystalline silicon film, an impurity of a conductivity type opposite to the semiconductor substrate in the second polycrystalline silicon film, and an impurity of a conductivity type opposite to the semiconductor substrate in the second polycrystalline silicon film are formed in the epitaxial layer. The semiconductor substrate and the opposite conductivity type impurity region diffused from the first polycrystalline silicon film and the semiconductor substrate diffused from the second polycrystalline silicon film while simultaneously diffusing into the layers to form a junction. and an opposite conductivity type impurity region in contact with each other in the epitaxial layer.

Function Conventionally, in an integrated circuit using a bipolar transistor, a masking process for forming a base contact window is required in order to form a P-type cavity concentration region as a tact region of an NPN transistor. In particular, the presence of these elements poses a serious obstacle to the miniaturization of patterns, which is essential for improving high frequency characteristics. Here, in the present invention, as shown in FIG. 1, the second polycrystalline silicon film 6 doped with a P-type impurity at a high concentration is selectively formed without going through a mask process, and then thermally diffused. Therefore, there is no need for a mask process for forming a base contact window, making it easy to miniaturize the pattern that is essential for improving high frequency characteristics. I can do it.

EXAMPLE An example of the present invention will be described below with reference to FIG. In FIG. 1, 1 is an N-type epitaxial layer, 2 is a silicon oxide film, 3 is a first polycrystalline silicon film, 4 is a silicon nitride film, 5 is a high temperature oxide film (HTO) formed by low pressure CVD, 6 7 is a second polycrystalline silicon film heavily doped with P-type impurities; 7 is an N layer (emitter region);
8 indicates a P layer (active base region), and 9 indicates a P layer (base contact region). That is, in FIG. 1, a silicon oxide film 2 is formed by thermal oxidation on the surface of an N-type epitaxial layer 1 that will become a collector region, and a predetermined region of the silicon oxide film 2 is etched using a photoresist pattern as a mask to form an N-type epitaxial layer. After exposing a predetermined region of the epitaxial layer 1, the first polycrystalline silicon film 3 and the silicon nitride film 4 are coated using a low pressure CVN method at a temperature of 2,000 to 300%, respectively.
0A.

Evaporate sequentially on about 100Q~150o people, and then.

Using the ion implantation method, implantation energy is applied to the entire surface 4
After implanting arsenic ions (As) into the first polycrystalline silicon at 0 KeV and a dose of about 6×1oα,
Furthermore, the entire surface was implanted with an energy of 160 KeV,
Boron ions (B) at a dose of 1 x 10 m and 8 degrees,
A P layer is formed directly under the N layer (emitter region) 7 by implanting it into the first polycrystalline silicon to a depth that overtakes the N layer (emitter region) 7.

Next, using the photoresist pattern as a mask, the silicon nitride film 4 and the first
polycrystalline silicon film 3 and the N-type epitaxial layer 1 immediately below
After etching a portion (approximately 3,000 people in the depth direction), low-pressure CVD was used.

Dichlorosilane (5iH2C12) as raw material gas
Page 10 and nitrous oxide (N20) '! Using i=, 85o~
At a growth temperature of about 900°C, high temperature oxide film (HTO) 5i
The silicon nitride film 4, the first polycrystalline silicon film 3, and the epitaxial layer immediately below are etched using an anisotropic dry etching device without going through a mask process. 1 on the exposed side wall of the
A high temperature oxide film (HTO) 5 is selectively formed, and monosilane (SiH
4) at a growth temperature of about 560 to 650°C.
After depositing a polycrystalline silicon film 6'1z of about 2000 to 30008, boron ions C1) are implanted into the entire surface using an ion implantation method at an implantation energy of 20 KeV and a dose of about 1 to 3 x 10α, and then a mask is applied. By etching using an anisotropic dry etching device without any process, a high concentration of P is selectively formed on the exposed sidewall surface of the high temperature oxide film (HTO) 5 and a part of the exposed surface of the N-type epitaxial layer 1. A second polycrystalline silicon film 6 containing type impurities is formed and then heat treated at a temperature of about 960 to 100°C at 111+- in a nitrogen atmosphere to form a bond between the N layer (emitter region) 7 and the P- A layer (active base region) 8 and a layer (base contact region) 9 are formed simultaneously.

Effects of the Invention As described above, according to the present invention, as shown in FIG.
Since the P layer (base contact region) 9 can be formed without going through a process, and the emitter and base contacts have a self-aligned contact structure, there is no problem with mutual mask alignment. Therefore, it is possible to easily realize a bipolar transistor or the like with excellent high frequency characteristics.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a bipolar transistor with a mesa structure emitter according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a conventional bipolar transistor having a mesa structure emitter. 1... Nfi epitaxial layer, 2...
・Silicon oxide film, 3...First polycrystalline silicon film, 4...Silicon nitride film, 6...
High temperature oxide film (HTO). 6...Second polycrystalline silicon film, 7...
・N layer (emitter region), 8...P single layer (active base region), 9...P layer (base contact region).

Claims (1)

[Claims] a step of forming an epitaxial layer of the same conductivity type as the semiconductor substrate on a semiconductor substrate of one conductivity type; a step of sequentially laminating a first polycrystalline silicon film and a first insulating film on the epitaxial layer; Highly concentrated first impurity ions of the same conductivity type as the semiconductor substrate and second impurity ions of the opposite conductivity type to the semiconductor substrate are formed in the first polycrystalline silicon film. a step of implanting the first impurity ions to a depth deeper than the first impurity ions; and a step of implanting the first insulating film, the first polycrystalline silicon film, and a portion of the epitaxial layer immediately below them using a photolithography method. selectively anisotropically etching a region; depositing a second insulating film on the first insulating film, the first polycrystalline silicon film, and the exposed surface of the epitaxial layer; forming the second insulating film by anisotropic etching only on the sidewalls of the first polycrystalline silicon film and the epitaxial layer directly below the first insulating film and the second insulating film; A second polycrystalline silicon film doped with impurities of a conductivity type opposite to that of the semiconductor substrate is deposited on the exposed surface of the epitaxial layer, and anisotropic etching is performed to remove the second polycrystalline silicon film. a step of forming an impurity of the same conductivity type as the semiconductor substrate in the first polycrystalline silicon film and a conductivity opposite to that of the semiconductor substrate; type impurities and the semiconductor substrate in the second polycrystalline silicon film and opposite conductivity type impurities are simultaneously diffused into the epitaxial layer to form a junction, and at the same time, the semiconductor substrate and the opposite conductivity type impurities in the second polycrystalline silicon film are diffused from the first polycrystalline silicon film. The method further comprises a step of bringing the semiconductor substrate and the opposite conductivity type impurity region diffused from the second polycrystalline silicon film into contact in the epitaxial layer. A method for manufacturing a semiconductor device.