JPS622352B2 - - Google Patents

Info

Publication number
JPS622352B2
JPS622352B2 JP56016093A JP1609381A JPS622352B2 JP S622352 B2 JPS622352 B2 JP S622352B2 JP 56016093 A JP56016093 A JP 56016093A JP 1609381 A JP1609381 A JP 1609381A JP S622352 B2 JPS622352 B2 JP S622352B2
Authority
JP
Japan
Prior art keywords
memory
processor
processors
return
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56016093A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57130164A (en
Inventor
Makoto Tazaki
Yukio Kamya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56016093A priority Critical patent/JPS57130164A/ja
Publication of JPS57130164A publication Critical patent/JPS57130164A/ja
Publication of JPS622352B2 publication Critical patent/JPS622352B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP56016093A 1981-02-05 1981-02-05 Synchronization adjusting circuit Granted JPS57130164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56016093A JPS57130164A (en) 1981-02-05 1981-02-05 Synchronization adjusting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56016093A JPS57130164A (en) 1981-02-05 1981-02-05 Synchronization adjusting circuit

Publications (2)

Publication Number Publication Date
JPS57130164A JPS57130164A (en) 1982-08-12
JPS622352B2 true JPS622352B2 (enExample) 1987-01-19

Family

ID=11906894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56016093A Granted JPS57130164A (en) 1981-02-05 1981-02-05 Synchronization adjusting circuit

Country Status (1)

Country Link
JP (1) JPS57130164A (enExample)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59844B2 (ja) * 1978-08-14 1984-01-09 日本電気株式会社 入出力装置制御方式

Also Published As

Publication number Publication date
JPS57130164A (en) 1982-08-12

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