JPS62233942A - Interference compensation circuit - Google Patents
Interference compensation circuitInfo
- Publication number
- JPS62233942A JPS62233942A JP61075555A JP7555586A JPS62233942A JP S62233942 A JPS62233942 A JP S62233942A JP 61075555 A JP61075555 A JP 61075555A JP 7555586 A JP7555586 A JP 7555586A JP S62233942 A JPS62233942 A JP S62233942A
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- Prior art keywords
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- quadrature
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- signal
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 18
- 238000001514 detection method Methods 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000003786 synthesis reaction Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はディジタル通信方式においてディジタル通信が
受ける他方式からの干渉を除去する干渉補償回路の構成
に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the configuration of an interference compensation circuit that eliminates interference from other systems that digital communication receives in a digital communication system.
（従来の技術）
従来の構成例を第３図に示す（特願昭６０−２８７８８
１）以下第３図を詳しく説明する。主信号受信用の主ア
ンテナ１で受信した信号は必要に応じＳ／Ｎ ＝ｉ良く
するため帯域通過フィルタ２を通した後周波数変換器３
によりＩＦ帯に変換される。一方、干渉信号受信用の補
助アンテナ４で受信した干渉信号は必要に応じＳ／Ｎを
良くするため帯域通過フィルタ５全通した後主信号と共
通の局部発振器７を用いて周波数変換器６によりＩＦ帯
に変換される。ＩＦ帯に変換された干渉信号は位相およ
び振幅を調整するため、可変位相回路９および可変振幅
回路８を通り、主信号中にもれ込んでいる干渉成分とほ
ぼ逆相１等振幅となるよう制御される。その干渉信号と
主信号とを合成回路１１で加算することにより主信号中
の干渉成分は除去される。つぎに可変位相回路と可変振
幅回路の制御方法について述べる。合成器１１による合
成後の主信号を復調器１００に入力する。復調器では再
生した基準搬送波２０を用いて直交位相検波１２．１３
され、その出力信号をそれぞれ高調波除去フィルタ１４
゜１５に通すことにより同相および直交分のベースバン
ド信号を得る。得られたベースバンド信号はそれぞれ誤
差信号発生回路１０２，１０３に入力される。ここで主
信号として１６ ＱＡＭ信号を考える。１６ ＱＡＭを
復調すると４値のベースバンド信号を得る。第４図に示
すように、４値信号を３ビット以上の出力を有するＡカ
変換器に通すことにより、その出力のうち上位２ビツト
は識別信号を、上位３ビツト目は誤差信号を表わす。従
って、上位３ビツト目の出力を用いて、残留の干渉成分
を検出することができる。(Prior art) An example of a conventional configuration is shown in FIG.
1) Figure 3 will be explained in detail below. The signal received by the main antenna 1 for receiving the main signal is passed through a band pass filter 2 to improve the S/N = i as necessary, and then passed through a frequency converter 3.
is converted into an IF band. On the other hand, the interference signal received by the auxiliary antenna 4 for receiving the interference signal is passed through the bandpass filter 5 to improve the S/N ratio as necessary, and then transmitted to the frequency converter 6 using the local oscillator 7 common to the main signal. Converted to IF band. In order to adjust the phase and amplitude of the interference signal converted to the IF band, it passes through a variable phase circuit 9 and a variable amplitude circuit 8 so that it has almost the opposite phase and equal amplitude as the interference component leaking into the main signal. controlled. By adding the interference signal and the main signal in the combining circuit 11, the interference component in the main signal is removed. Next, a method of controlling the variable phase circuit and variable amplitude circuit will be described. The main signal after being combined by the combiner 11 is input to the demodulator 100 . The demodulator uses the regenerated reference carrier wave 20 to perform quadrature phase detection12.13
and the output signals are passed through a harmonic removal filter 14.
15 to obtain in-phase and quadrature baseband signals. The obtained baseband signals are input to error signal generation circuits 102 and 103, respectively. Here, consider a 16 QAM signal as the main signal. When the 16 QAM is demodulated, a 4-level baseband signal is obtained. As shown in FIG. 4, by passing a 4-value signal through an A converter having an output of 3 bits or more, the upper 2 bits of the output represent an identification signal and the upper 3rd bit represents an error signal. Therefore, the residual interference component can be detected using the output of the third most significant bit.
一方、干渉信号を分岐回路１０で分岐しその一方を主信
号用基準搬送波２０を用いて直交位相検波２２，２３し
た後、高調波除去フィルタ２４゜２５全通し、主信号復
調器で再生したクロック信号を用いて、識別器２７１２
Ｂにより干渉信号の識別結果を得る。そして、同相およ
び直交成分の干渉信号の識別結果と誤差信号との間で相
関検出をおこなう。すなわち同相分の干渉の識別信号と
同相分の誤差信号との乗算（乗算器３０）（ここではデ
ィジタルにおこなっている）した結果と、直交分の干渉
の識別信号と直交分の誤差信号との乗算（乗算器２９）
した結果とをアナログ的に抵抗回路３３．３４を用いて
加算した結果を積分器３８により積分することにより可
変振幅回路８の制御信号とする。また、直交分の干渉の
識別信号と同相分の誤差信号との乗算３１した結果と、
同相分の干渉の識別信号と直交分の誤差信号との乗算３
２した結果との減算３５，３６Ｌ、た信号を積分器３７
に通し積分することにより可変位相回路９の制御信号と
する。On the other hand, the interference signal is branched by a branch circuit 10, one of which is subjected to quadrature phase detection 22, 23 using a main signal reference carrier wave 20, and then passed through harmonic removal filters 24 and 25, and a clock signal regenerated by a main signal demodulator. Using the signal, the discriminator 2712
The interference signal identification result is obtained by B. Then, correlation detection is performed between the identification results of the in-phase and quadrature component interference signals and the error signal. In other words, the result of multiplying the in-phase interference identification signal and the in-phase error signal (multiplier 30) (this is done digitally here), and the result of multiplying the in-phase interference identification signal and the orthogonal error signal by the orthogonal interference identification signal and the orthogonal error signal. Multiplication (multiplier 29)
The results are added in an analog manner using resistance circuits 33 and 34, and the result is integrated by an integrator 38, thereby providing a control signal for the variable amplitude circuit 8. In addition, the result of multiplication 31 of the identification signal of the interference of the orthogonal component and the error signal of the in-phase component,
Multiplication of in-phase interference identification signal and orthogonal error signal 3
Subtract 35, 36L with the result of 2, and integrator 37
A control signal for the variable phase circuit 9 is obtained by integrating the signal.
以上により自動的に干渉補償をおこなうことができる。As described above, interference compensation can be automatically performed.
（発明が解決しようとする問題点）
しかし、従来の上記回路では、干渉信号の振幅及び位相
の制御のために可変振幅回路及び可変位相回路を用いる
ため構成が複雑となる。(Problems to be Solved by the Invention) However, the conventional circuit described above uses a variable amplitude circuit and a variable phase circuit to control the amplitude and phase of the interference signal, and therefore has a complicated configuration.
本発明はこの点を改善することを目的とする。The present invention aims to improve this point.
（問題点を解決するための手段）
本発明は従来の可変振幅回路と可変位相回路の機能を直
交振幅変調器で行なうもので、そのひとつの特徴は、主
信号受信用の主アンテナと、干渉信号受信手段と、該干
渉信号受信手段の出力の位相及び振幅と前記主アンテナ
の出力との相対関係を調節する直交振幅変調器と、該変
調器により調節された主アンテナ及び干渉信号受信手段
の出力を合成する合成回路と、該合成回路の出力及び主
信号から再生した基準搬送波を入力として同相成分と直
交成分に分解する第１の直交位相検波器と、前記同相成
分及び直交成分を各々入力とする２つの誤差信号発生回
路と、前記第１の直交位相検波器と同じ基準搬送波によ
シ、前記干渉信号受信手段の出力を同相成分と直交成分
に分解する第２の直交位相検波器と、同相成分の誤差信
号発生回路の出力と、第２の直交位相検波器の同相成分
出力との積を提供する第１の乗算器と、直交成分の誤差
信号発生回路の出力と、第２の直交位相検波器の直交成
分出力との積を提供する第２の乗算器と、直交成分の誤
差信号発生回路の出力と、第２の直交位相検波器の同相
成分出力との積を提供する第３の乗算器と、同相成分の
誤差信号発生回路の出力と、第２の直交位相検波器の直
交成分出力との積を提供する第４の乗算器と、第１の乗
算器の出力、第２の乗算器の出力、又は両者の和を入力
とする第１の積分器と、第３の乗算器の出力、第４の乗
算器の出力、又は両者の差を入力とする第２の積分器と
を有し、第１の積分器の出力により前記直交振幅変調器
の同相成分を制御し、第２の積分器の出力により前記直
交振幅変調器の直交成分を制御する干渉補償回路にある
。(Means for Solving the Problems) The present invention performs the functions of the conventional variable amplitude circuit and variable phase circuit using a quadrature amplitude modulator. One of its features is that the main antenna for receiving the main signal and the interference a signal receiving means; a quadrature amplitude modulator for adjusting the relative relationship between the phase and amplitude of the output of the interference signal receiving means and the output of the main antenna; and the main antenna adjusted by the modulator and the interference signal receiving means; a synthesis circuit for synthesizing the outputs; a first quadrature phase detector for inputting the output of the synthesis circuit and a reference carrier wave regenerated from the main signal and decomposing it into an in-phase component and a quadrature component; and inputting the in-phase component and the quadrature component, respectively. and a second quadrature phase detector that uses the same reference carrier as the first quadrature phase detector and decomposes the output of the interference signal receiving means into an in-phase component and a quadrature component. , a first multiplier that provides the product of the output of the in-phase component error signal generation circuit and the in-phase component output of the second quadrature phase detector; a second multiplier that provides the product of the quadrature component output of the quadrature phase detector; and a second multiplier that provides the product of the output of the quadrature component error signal generation circuit and the in-phase component output of the second quadrature phase detector. a fourth multiplier that provides the product of the output of the in-phase component error signal generation circuit and the quadrature component output of the second quadrature phase detector; A first integrator that receives as input the output of the second multiplier, or the sum of both, and a second integrator that receives as input the output of the third multiplier, the output of the fourth multiplier, or the difference between the two. an interference compensation circuit having an output of a first integrator to control an in-phase component of the quadrature amplitude modulator, and an output of a second integrator to control a quadrature component of the quadrature amplitude modulator. .
（実施例）
特許請求の範囲（１）の実施例を第１図に示す。主信号
受信用の主アンテナ１がら受信したディジタル信号は必
要に応じてＳハを良くするため帯域通過フィルタ２を通
り・周波数変換器３によりＩＦ帯に変換される。一方、
干渉信号受信用の補助アンテナ４から受信した干渉信号
は必要に応じＳ／Ｎを良くするため帯域通過フィルタ５
を通り、主信号側と共通の局部発振器７を用いて、周波
数変換器６によりＩＦ帯に変換される。ＩＦ帯に変換さ
れた干渉信号は振幅および位相を制御する直交振幅変調
器２００に入力される。その出方信号は主信号中にもれ
込んだ干渉成分とほぼ逆相１等振幅となっている。従っ
て合成器１４出力には干渉成分はほとんどあられれない
。(Example) An example of claim (1) is shown in FIG. The digital signal received by the main antenna 1 for receiving the main signal passes through a band pass filter 2 and is converted into an IF band by a frequency converter 3 in order to improve the S C as necessary. on the other hand,
The interference signal received from the auxiliary antenna 4 for receiving the interference signal is passed through a bandpass filter 5 to improve the S/N ratio as necessary.
, and is converted into an IF band by a frequency converter 6 using a local oscillator 7 common to the main signal side. The interference signal converted into the IF band is input to a quadrature amplitude modulator 200 that controls the amplitude and phase. The output signal has an amplitude substantially opposite in phase to the interference component leaked into the main signal. Therefore, almost no interference components appear in the output of the combiner 14.
直交振幅変調器２００は、信号を２分配する分配器９と
、その一方の信号を入力する両極性可変減衰器１１と、
分配器９出カの他方を９０’だけ位相を偏移する移相器
１０ｆ、通った後両極性可変減衰器１２と２つの両極性
可変減衰器出力を合成する合成器１３から構成される。The quadrature amplitude modulator 200 includes a divider 9 that divides a signal into two, a bipolar variable attenuator 11 that inputs one of the signals,
It consists of a phase shifter 10f that shifts the phase of the other output of the divider 9 by 90', a bipolar variable attenuator 12 after passing through, and a synthesizer 13 that combines the outputs of the two bipolar variable attenuators.
上記２つの両極性可変減衰器の制御方法について以下に
説明する。１４による合成後の主信号を復調器１００に
入力する。復調器では再生した２１による基準搬送波に
より１５と１６により直交位相検波され、さらに高調波
除去フィルタ２２．２３を通った後、復調ベースバンド
信号を得る。同相および直交成分のベースバンド信号は
残留する干渉信号を検出する誤差信号発生回路１０２
、１０３に接続される。１６ ＱＡＭ信号を例にとると
、復調したベースバンド信号は４値となる。この信号を
入力とし、第４図で示すような３ピット以上の出力を有
するφ変換器を用いることにより出力のうち上位２ビ、
トは識別信号、上位３ビツト目は誤差信号、すなわち残
留の干渉成分を検出可能となる・一方、ＩＦ帯に変換さ
れた干渉信号を主信号用復調器で再生した基準搬送波２
１−を用いて１７゜１８により直交位相検波した後、高
調波成分を除去する低域通過フィルタ２４．２５に通し
、その信号を主信号用復調器で再生したクロック信号を
用いて識別器３１．３２により２値化された同相および
直交成分の干渉信号を得る。得られた同相および直交成
分の誤差信号と同相および直交成分の干渉信号の間で相
関検出をおこなう。すなわち同相分の誤差信号と同相分
の干渉信号を３４で乗算（ここではディジタル的におこ
なうためＥＸ−ＯＲ回路を用いる。）した結果と直交分
の誤差信号と直交分の干渉信号を３３で乗算した結果に
ついて両者をアナログ的に加算する抵抗回路３７ｔ３８
とその出力を積分するため積分器４２に通す。その出力
により直交振幅変調器２００の０相の両極性可変減衰器
１１を制御する。また、同相成分の誤差信号と直交成分
の干渉信号を３５で乗算した結果と直交成分の誤差信号
と同相成分の干渉信号を３６で乗算した結果との減算を
抵抗回路３９゜４０によりおこない、その出力を積分す
るため積分器４１に通す。その出力により直交振幅変調
器２００のπ／２相の両極性可変減衰器１２を制御する
。以上により１動的に干渉は除去される。A method of controlling the above two bipolar variable attenuators will be explained below. The main signal after synthesis by 14 is input to the demodulator 100. In the demodulator, the regenerated reference carrier wave 21 is subjected to quadrature phase detection by 15 and 16, and after passing through harmonic removal filters 22 and 23, a demodulated baseband signal is obtained. The baseband signals of in-phase and quadrature components are generated by an error signal generation circuit 102 that detects residual interference signals.
, 103. Taking a 16 QAM signal as an example, the demodulated baseband signal has four levels. By using this signal as an input and using a φ converter having an output of 3 or more pits as shown in Fig. 4, the upper 2 bits of the output,
The top three bits are the identification signal, and the third highest bit is the error signal, which makes it possible to detect residual interference components.On the other hand, the reference carrier wave 2 is reproduced by the main signal demodulator from the interference signal converted to the IF band.
After performing orthogonal phase detection at 17°18 using 1-, the signal is passed through a low-pass filter 24 and 25 that removes harmonic components, and the signal is regenerated by a main signal demodulator. Using the clock signal, the discriminator 31 Obtain interference signals of in-phase and quadrature components binarized by .32. Correlation is detected between the obtained in-phase and quadrature component error signals and the in-phase and quadrature component interference signals. In other words, the result of multiplying the in-phase error signal and the in-phase interference signal by 34 (here, an EX-OR circuit is used because it is done digitally) and the orthogonal error signal and the orthogonal interference signal are multiplied by 33. Resistance circuit 37t38 that adds both results in an analog manner
and its output is passed through an integrator 42 for integration. The output controls the 0-phase bipolar variable attenuator 11 of the quadrature amplitude modulator 200. In addition, the result of multiplying the error signal of the in-phase component and the interference signal of the quadrature component by 35 and the result of multiplying the error signal of the quadrature component and the interference signal of the in-phase component by 36 are subtracted by the resistor circuit 39°40. The output is passed through an integrator 41 for integration. The output controls the π/2 phase bipolar variable attenuator 12 of the quadrature amplitude modulator 200. As described above, interference is removed dynamically.
特許請求の範囲（２）の実施例を第２図に示す。請求の
範囲（１）の実施例である第１図との相異点としては、
第１図の場合、干渉信号の処理に直交位相検波器を用い
ているが、第２図では単なる位相検波器１７を用いる。An embodiment of claim (2) is shown in FIG. The differences from FIG. 1, which is an embodiment of claim (1), are as follows.
In the case of FIG. 1, a quadrature phase detector is used to process the interference signal, but in FIG. 2, a simple phase detector 17 is used.
従って第２図の場合、その分回路構成が簡単化できると
いう利点がある。詳しく以下に説明する。ＩＦ帯に変換
された干渉信号は主信号用復調器で再生された搬送波２
１を用いて位相検波器１７によシ検波された後高調波除
去フィルタ２４を通った後、主信号側の復調器で再生さ
れたクロック信号を用いて識別器３１により２値化され
た干渉信号を得る。その干渉信号と、それと相対的に同
相関係の誤差信号（１０３）出力とを３３によシ乗算（
ここではディジタル的におこなうためＥＸ−ＯＲを用い
ている）した後積分器４１に通すことにより直交振幅変
調器（２００）のＯ相の両極性可変減衰器１１を制御す
る。また２値化された干渉信号と、それと相対的に直交
関係の誤差信号（１０２）出力と３５により乗算した後
積分器４２に通すことにより直交振幅変調器（２００）
のπ／２相の両極性可変減衰器１２を制御する。Therefore, in the case of FIG. 2, there is an advantage that the circuit configuration can be simplified accordingly. This will be explained in detail below. The interference signal converted to the IF band is the carrier wave 2 which is regenerated by the main signal demodulator.
1, the interference is detected by the phase detector 17, passed through the harmonic removal filter 24, and then binarized by the discriminator 31 using the clock signal regenerated by the demodulator on the main signal side. Get a signal. The interference signal and the output of the error signal (103) having a relatively in-phase relationship with it are multiplied by 33 (
Here, EX-OR is used because it is performed digitally) and then passed through an integrator 41 to control the O-phase bipolar variable attenuator 11 of the quadrature amplitude modulator (200). In addition, the binarized interference signal is multiplied by the output of the error signal (102) having a relatively orthogonal relationship thereto by 35, and then passed through the integrator 42 to generate the quadrature amplitude modulator (200).
π/2 phase bipolar variable attenuator 12 is controlled.
従って、自動的に干渉補償をおこなうことができる。Therefore, interference compensation can be performed automatically.
以上、本発明の実施例をＩＦ帯で適用した場合について
述べたがＲＦ帯で直接おこなうことももちろん可能であ
る。Although the embodiments of the present invention have been described above in the IF band, it is of course possible to apply them directly in the RF band.
第１図または第２図の実施例について、実際には、τ１
．τ２．τ３の遅延線により相対的なタイミングを調整
し、補償効果が最も大きくなるようにする必要がある。For the embodiment of FIG. 1 or FIG. 2, in practice, τ1
．． τ2. It is necessary to adjust the relative timing by the delay line of τ3 to maximize the compensation effect.
本発明の実施例の第１図または第２図において、主信号
としてＱＡＭ （直交振幅変調）信号の場合、例えば１
６ ＱＡＭ信号の場合、１０２，１０３の誤差信号発生
回路としては３ビツト以上の出力を有するＡ／Ｄ変換器
を用い、第４図に示すように、上位３ビツト目から直接
誤差信号をとり出すことができる。一般に２ 値ＱＡＭ
の場合、復調したベースバンド信号は２Ｎ値信号となり
この信号を識別し、誤差信号を得るためにはＮ＋ｌビッ
ト以上の出力を有するＡ／Ｄ変換器を用い、上位Ｎ＋１
ビツト目から直接誤差信号を取り出すことができる。In FIG. 1 or 2 of the embodiment of the present invention, if the main signal is a QAM (quadrature amplitude modulation) signal, for example,
In the case of a 6-QAM signal, an A/D converter with an output of 3 bits or more is used as the error signal generation circuits 102 and 103, and the error signal is directly extracted from the upper 3rd bit as shown in Figure 4. be able to. Generally two-value QAM
In this case, the demodulated baseband signal becomes a 2N-value signal, and in order to identify this signal and obtain an error signal, an A/D converter with an output of N+1 bits or more is used, and the upper N+1
The error signal can be extracted directly from the bit.
一方、８ ＰＳＫ 、 １６ ＰＳＫのように、復調し
たベースバンド信号が等間隔でない場合、単にある１ビ
ツトだけをとり出して誤差信号とすることはできない。On the other hand, when demodulated baseband signals are not equally spaced, such as 8 PSK and 16 PSK, it is not possible to simply extract one bit and use it as an error signal.
例えば８ ＰＳＫの場合の誤差信号発生回路として８ビ
ツトのＡ／Ｄ変換器を用いる例を第５図に示している。For example, FIG. 5 shows an example in which an 8-bit A/D converter is used as an error signal generating circuit in the case of 8 PSK.
８ ＰＳＫを直交位相検波することにより、復調したベ
ースバンド波形は信号間隔の異なる４値信号となる。こ
れを８ビツトでディジタル化す誤差信号としては斜線部
分は正の誤差を、また空白の部分は負の誤差を示してい
る。従って、φ変換器の出力８ビツトを常にモニタし、
斜線部分に入ったとき、正、それ以外は負の誤差信号を
得るようにＲＯＭ等により、変換回路を設けることによ
り誤差信号発生回路を実現できる。By performing quadrature phase detection on the 8 PSK, the demodulated baseband waveform becomes a four-level signal with different signal intervals. As for the error signal obtained by digitizing this with 8 bits, the shaded area indicates a positive error, and the blank area indicates a negative error. Therefore, always monitor the 8-bit output of the φ converter,
An error signal generation circuit can be realized by providing a conversion circuit using a ROM or the like so that a positive error signal is obtained when the shaded area is entered and a negative error signal is obtained otherwise.
（発明の効果）
以上、説明したように補助アンテナから受信した干渉信
号の振幅および位相を可変する場合、直交振幅変調器を
用い、そのＯ相およびπ／２相の両極性可変減衰器を制
御することにより自動的に主信号中にもれ込んだ干渉成
分を消去可能である。(Effect of the invention) As explained above, when varying the amplitude and phase of the interference signal received from the auxiliary antenna, a quadrature amplitude modulator is used to control the O-phase and π/2-phase bipolar variable attenuator. By doing so, it is possible to automatically cancel interference components that have leaked into the main signal.
【図面の簡単な説明】
第１図は本発明の実施例のブロック図、第２図は本発明
の別の実施例のブロック図、第３図は従来の干渉補償回
路のブロック図、第４図は誤差信号発生回路の説明図、
第５図は誤差信号発生回路の動作説明図である。
（符号の説明：第１図）
１・・・主アンテナ、４・・・補助アンテナ、２，５・
・・帯域通過フィルタ、３，６・・・周波数変換回路、
７・・・局部発振器、８．９・・・分配器、１０・・・
９０°移相器、１１，１２・・・両極性可変減衰器％
１３，１４・・・合成器、１５，１６，１７，１８・・
・位相検波器、１９．２０・・・９０°移相器、２１・
・・再生搬送波、２２ 、２３ ｔ ２４ ｅ ２５・
・・低域通過フィルタ、２７．２８，３１．３２・・・
識別回路、２９ 、３０・・・減算器、２６・・・再生
クロック、３３ 、３４ 。
３５ ・ＥＸ−ＯＲ回路、３６ ・ＥＸ−ＮＯＲ回路、
３７．３８゜３９．４０・・・抵抗回路、４１．４２・
・・積分器、１００・・・主信号復調器、１０１・・・
制御回路、１０２゜１０３・・・誤差信号発生回路、２
００・・・直交振幅変調器[Brief Description of the Drawings] Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of another embodiment of the invention, Fig. 3 is a block diagram of a conventional interference compensation circuit, and Fig. 4 is a block diagram of an embodiment of the present invention. The figure is an explanatory diagram of the error signal generation circuit.
FIG. 5 is an explanatory diagram of the operation of the error signal generation circuit. (Explanation of symbols: Fig. 1) 1... Main antenna, 4... Auxiliary antenna, 2, 5...
...bandpass filter, 3,6...frequency conversion circuit,
7...Local oscillator, 8.9...Distributor, 10...
90° phase shifter, 11, 12...Bipolar variable attenuator%
13, 14... combiner, 15, 16, 17, 18...
・Phase detector, 19.20...90° phase shifter, 21.
・Regenerated carrier wave, 22, 23 t 24 e 25・
・Low pass filter, 27.28, 31.32...
Identification circuit, 29, 30... Subtractor, 26... Regeneration clock, 33, 34. 35 ・EX-OR circuit, 36 ・EX-NOR circuit,
37.38°39.40...Resistance circuit, 41.42.
... Integrator, 100... Main signal demodulator, 101...
Control circuit, 102゜103...Error signal generation circuit, 2
00...Quadrature amplitude modulator
Claims (2)
テナの出力との相対関係を調節する直交振幅変調器と、 該変調器により調節された主アンテナ及び干渉信号受信
手段の出力を合成する合成回路と、該合成回路の出力及
び主信号から再生した基準搬送波を入力として同相成分
と直交成分に分解する第１の直交位相検波器と、 前記同相成分及び直交成分を各々入力とする２つの誤差
信号発生回路と、 前記第１の直交位相検波器と同じ基準搬送波により、前
記干渉信号受信手段の出力を同相成分と直交成分に分解
する第２の直交位相検波器と、同相成分の誤差信号発生
回路の出力と、第２の直交位相検波器の同相成分出力と
の積を提供する第１の乗算器と、 直交成分の誤差信号発生回路の出力と、第２の直交位相
検波器の直交成分出力との積を提供する第２の乗算器と
、 直交成分の誤差信号発生回路の出力と、第２の直交位相
検波器の同相成分出力との積を提供する第３の乗算器と
、 同相成分の誤差信号発生回路の出力と、第２の直交位相
検波器の直交成分出力との積を提供する第４の乗算器と
、 第１の乗算器の出力、第２の乗算器の出力、又は両者の
和を入力とする第１の積分器と、 第３の乗算器の出力、第４の乗算器の出力、又は両者の
差を入力とする第２の積分器とを有し、第１の積分器の
出力により前記直交振幅変調器の同相成分を制御し、第
２の積分器の出力により前記直交振幅変調器の直交成分
を制御することを特徴とする干渉補償回路。(1) A main antenna for receiving a main signal, an interference signal receiving means, a quadrature amplitude modulator that adjusts the relative relationship between the phase and amplitude of the output of the interference signal receiving means and the output of the main antenna, and the modulation. a combining circuit that combines the output of the main antenna adjusted by the receiver and the output of the interference signal receiving means, and a first quadrature phase that inputs the output of the combining circuit and the reference carrier wave reproduced from the main signal and decomposes it into an in-phase component and a quadrature component. a detector, two error signal generation circuits receiving the in-phase component and the quadrature component, respectively, and using the same reference carrier as the first quadrature phase detector, the output of the interference signal receiving means is divided into the in-phase component and the quadrature component. a first multiplier that provides the product of the output of the error signal generation circuit of the in-phase component and the in-phase component output of the second quadrature-phase detector; a second multiplier that provides the product of the output of the error signal generation circuit and the quadrature component output of the second quadrature phase detector; and the output of the error signal generation circuit of the quadrature component and the second quadrature phase detector. and a fourth multiplier that provides the product of the output of the error signal generation circuit of the in-phase component and the quadrature component output of the second quadrature phase detector. and a first integrator that receives as input the output of the first multiplier, the output of the second multiplier, or the sum of both, the output of the third multiplier, the output of the fourth multiplier, or and a second integrator that receives the difference between the two as input, the in-phase component of the quadrature amplitude modulator is controlled by the output of the first integrator, and the in-phase component of the quadrature amplitude modulator is controlled by the output of the second integrator. An interference compensation circuit characterized by controlling orthogonal components of.
テナの出力との相対関係を調節する直交振幅変調器と、 該変調器により調節された主アンテナ及び干渉信号受信
手段の出力を合成する合成回路と、該合成回路の出力及
び主信号から再生した基準搬送波を入力として同相成分
と直交成分に分解する第１の直交位相検波器と、 前記同相成分及び直交成分を各々入力とする２つの誤差
信号発生回路と、 前記第１の直交位相検波器と同じ基準搬送波により、前
記干渉信号受信手段の出力を位相検波する位相検波器と
、 同相成分の誤差信号発生回路の出力と、位相検波器の出
力との積を提供する第１の乗算器と、直交成分の誤差信
号発生回路の出力と、位相検波器の出力との積を提供す
る第２の乗算器と、各乗算器の出力に結合する第１及び
第２の積分器を有し、 第１の積分器の出力により前記直交振幅変調器の同相成
分を制御し、第２の積分器の出力により前記直交振幅変
調器の直交成分を制御することを特徴とする干渉補償回
路。(2) a main antenna for receiving a main signal; an interference signal receiving means; a quadrature amplitude modulator that adjusts the relative relationship between the phase and amplitude of the output of the interference signal receiving means and the output of the main antenna; and the modulation. a combining circuit that combines the output of the main antenna adjusted by the receiver and the output of the interference signal receiving means, and a first quadrature phase that inputs the output of the combining circuit and the reference carrier wave reproduced from the main signal and decomposes it into an in-phase component and a quadrature component. a detector; two error signal generation circuits each receiving the in-phase component and the quadrature component; and a phase detector for phase-detecting the output of the interference signal receiving means using the same reference carrier as the first quadrature phase detector. a first multiplier that provides the product of the output of the error signal generation circuit for the in-phase component and the output of the phase detector; and the output of the error signal generation circuit for the quadrature component and the output of the phase detector; a second multiplier for providing a product, and first and second integrators coupled to the output of each multiplier, the output of the first integrator controlling the in-phase component of the quadrature amplitude modulator; , an interference compensation circuit characterized in that a quadrature component of the quadrature amplitude modulator is controlled by an output of a second integrator.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61075555A JPH06105898B2 (en) | 1986-04-03 | 1986-04-03 | Interference compensation circuit |
| US06/921,093 US4736455A (en) | 1985-12-23 | 1986-10-21 | Interference cancellation system |
| CA000521944A CA1257658A (en) | 1985-12-23 | 1986-10-31 | Interference cancellation system |
| DE8686308589T DE3685645T2 (en) | 1985-12-23 | 1986-11-04 | SYSTEM FOR COMPENSATING A RADIO INTERFERENCE SIGNAL. |
| EP86308589A EP0228786B1 (en) | 1985-12-23 | 1986-11-04 | Radio signal interference cancellation system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61075555A JPH06105898B2 (en) | 1986-04-03 | 1986-04-03 | Interference compensation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62233942A true JPS62233942A (en) | 1987-10-14 |
| JPH06105898B2 JPH06105898B2 (en) | 1994-12-21 |
Family
ID=13579542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61075555A Expired - Lifetime JPH06105898B2 (en) | 1985-12-23 | 1986-04-03 | Interference compensation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06105898B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100727458B1 (en) | 2004-10-04 | 2007-06-13 | 마이크로나스 게엠베하 | Method and circuit arrangement for suppressing an orthogonal perturbation |
| US8098769B2 (en) | 2004-09-28 | 2012-01-17 | Trident Microsystems (Far East) Ltd. | Circuit and method for recovering a carrier |
-
1986
- 1986-04-03 JP JP61075555A patent/JPH06105898B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8098769B2 (en) | 2004-09-28 | 2012-01-17 | Trident Microsystems (Far East) Ltd. | Circuit and method for recovering a carrier |
| KR100727458B1 (en) | 2004-10-04 | 2007-06-13 | 마이크로나스 게엠베하 | Method and circuit arrangement for suppressing an orthogonal perturbation |
| US7920653B2 (en) | 2004-10-04 | 2011-04-05 | Trident Microsystems (Far East) Ltd. | Method and circuit arrangement for suppressing an orthogonal perturbation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06105898B2 (en) | 1994-12-21 |
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