JPS622322A - Adding circuit - Google Patents

Abstract

PURPOSE:To reduce an increase of an operation time and to execute an operation at a high speed even against a binary number having a large bit number, by providing three pieces of unit adding circuits, one piece of selecting signal generating circuit, and three pieces of selecting circuits. CONSTITUTION:A unit circuit 601 inputs two pieces of binary numbers X1, Y1 and putputs its sum V1 and the sum V1 and the sum W1 of said sum and '1'. A unit adding circuit 602 inputs binary numbers X2, Y2 and outputs its sum V2, the sum W2 of said sum '1', and the respective carry outputs g2, p2. A unit circuit 603 inputs binary numbers X3, Y3, the sum W3 of said sum and '1', and the respective carry outputs g3, p3. A selecting signal generating circuit 620 inputs the outputs g2, p2, g3 and p3, and an auxiliary input (r) and outputs selecting signals s1-s3, t1-t3. Selecting circuits 631-633 input the signals V1 and W1, V2 and W2, and V3 and W3, respectively, and select and output binary numbers Z1, Z2 and Z3, based on a logic of the signals s1, s2 and s3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an adder circuit, and particularly to a binary number adder circuit.

[Conventional technology]

Conventionally, this type of adder circuit takes as input two m (positive integer) bit binary numbers Xi, yi and an auxiliary human power r,
An m-bit binary number Zi of the sum of Xi, Yi, and r, and
the first carry output gi to the upper digit of the sum of i and Yi;
Second digit ascending output p of the sum of Xi, yi, and 1 to the upper digit
Generate and output i! (Positive integer) unit adder circuits are provided in parallel, and the two first carry outputs g+, gz, ..., g output from the two unit adder circuits.
i and two second carry outputs Ill 1. pt...
・, pi and the auxiliary input CIN are input, and the first representative carry signal G and the second representative carry signal P are given as the logical formula % formula %
and two auxiliary human power r1 for the two unit adder circuits,
The configuration includes a carry signal generation circuit that generates and outputs rt, . . . , rl.

FIG. 7 shows an example of a conventional adder circuit.

In FIG. 7, three unit addition circuits 910, 920.9
30 are the auxiliary human power r5, r2, r, and the binary number x, respectively.

Input x2, Xi and binary numbers Y + , Y z, Y, and output binary numbers Z, Zt, Zi.
Carry output g+, gz, gz and second carry output 1)+
, pz, 1)s are output to the carry signal generation circuit 940. The carry signal generation circuit 940 generates first carry outputs g1, gz, g3 and second carry outputs pr, pz, p.
i and the auxiliary input CIN, the auxiliary human power r1, rfi,
rl, and also generates and outputs a first representative carry signal G and a second representative carry signal P.

Here, binary number X = (X+, Xz, Xff) = (X+, x ,,
・', x12] and binary number Y= ('y'+, Yz, Yi) = ()'1. y
2,...,y+z], the unit addition circuit 9
10 is input X+= (x,, x,, x,
, x, ).

For Y+-(yi, '!z, Yx, ya), for example, the first carry output gi that becomes the logical formula % formula % (or pI = gI +51s2・s3・s4) and the second digit The uplink output p2 is outputted to the carry signal generation circuit 940.

Similarly, the unit adder circuits 920 and 930 output the first carry outputs g2 and g3 and the second carry outputs p2 and pi to the carry signal generation circuit 940.

The carry signal generation circuit 940 outputs a first carry output g+.

Input gl, gi, second carry output p+, pt, p3, and auxiliary input CIN, G=g++p+-gz+p+°pz・gszp=pdirection・
pri1φptor+”gz+pz=gs+pz-p3・C+N-rt=
g3+px・C+xs rconiC,N The first representative carry output G and the second representative carry output P
and auxiliary human power rl, rgir.

When the unit addition circuit 910 inputs the auxiliary human power r, z+=s+e(c, +s, -c3+sz・s3・c4+
5g-32・S4・rl), 2,=S2■(c3+33-C4+ s,・54-r,
), z3=s, ■ (Ca+Sa□r+), z 4
Outputs a 4-bit binary number Z+=(2+, Zz, 23.24) where = saer l.

Similarly, the unit addition circuits 920 and 930 also have auxiliary human power r2,
r, and outputs 4-bit binary numbers Zz and Zx.

In this way, the adder circuit 9000 adds 2 bits of 12 bits.
A 12-bit binary number Z = (Z
,,i,Z,).

Here, since this adder circuit 9000 satisfies the conditions for a unit adder circuit, a 12.times.3 bit adder circuit can be constructed by using the adder circuit 9000 as a unit adder circuit, for example, with a configuration similar to that shown in FIG.

[Problem that the invention seeks to solve]

In the conventional adder circuit described above, the unit adder circuit used requires an auxiliary input ri to generate the sum of binary numbers Z5, and a higher-level auxiliary human power CIN is required to generate the auxiliary human power r. There is a problem with this.

This means that to generate the sum of input binary numbers X and Y,
This means that the computation time is the sum of all circuit delay times from generation of the first carry output and second carry output to generation of the auxiliary input and generation of the binary number 2. Therefore, as the number of bits of the input binary number XiY increases and the carry signal generation circuit has a multi-stage configuration, there is a drawback that the calculation time increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide an adder circuit that is suitable for increasing the speed of calculations with less increase in calculation time even for binary numbers with a large number of bits.

Means for Solving Problem C] The adder circuit of the present invention stores two 1n-bit binary numbers Xi
, yt, the m-bit first binary number v of the sum of Xi and Yi, the first loss output gi to the upper digit of the sum of Xl and Yi, and the sum of Xi, Yi, and 1. The second of m bits of the sum of
The binary number W1 and the second digit up output p to the upper digit of the sum of Xi, Yi, and l.

One unit adder circuit that generates and outputs g2.
g2. ..., g, (l-1) second carry outputs pt, ps, ..., p, and auxiliary human power r are input, and one selection signal that becomes the logical formula A selection signal generation circuit that generates and outputs sl, sa, . . . , S, and one first binary number Vi, Vi output from the one unit addition circuit.

..., one binary number ■ of V, and one second
One binary number Wi among the binary numbers W8, W2, . . . , W2 and one selection signal s ,, s ! output from the selection signal generation circuit. , ..., S, and the selection signal s4 is a logic "
1 when the selection signal si is logic ``1'', and one selection circuit that generates and outputs an m-bit binary number Zt as a result of selecting Wi when the selection signal si is logic ``1''; of(IXm
) Bit binary number A = (X+, Xi, ..., Xe-1
,Xi),B=(YI,Yt,...,y,-,,y,
) and auxiliary human power r as inputs, and the sum of A, B, and r (
/Xm) Generates and outputs a bit binary number C=[Zl, Zl, . . . , Z, -, , Z,).

Further, the adder circuit of the present invention can store two m-bit binary numbers X
t, Yt, and m-bit first binary number V! of the sum of Xi and Yi. and the first to the upper digit of the sum of X5 and Yi
Carry output gi, Xi and Y.

The m-bit second binary number Wi which is the sum of and 1, and X and Y
Two unit adder circuits that generate and output the second carry output pi to the upper digit of the sum of i and 1, and (1-1) unit adders of these two unit adder circuits. (l-1) first carry outputs g2, gx, . . . output from the circuit
, g, (g-1) second carry outputs p2, p3,
. . . Input pi and auxiliary human power r, and select one first selection board number s that becomes the logical formula % formula % 1. sz,...,3
1, and four second selection board numbers t1. tt,...,t
, and a selection signal generation circuit that generates and outputs p4 first binary number ■1, which is output from the one unit addition circuit.
One binary number Vi out of v2, ..., ■, and two second binary numbers Wi, W2. ..., one binary number w8 of W, and one first selection board number S output from the selection signal generation circuit 1. S @, . . . , one first selection board number si and one second selection board number 1. ,1. , . . . , one second selection board number 1 of t2. When the first board selection number Q is logic "0", select Vi, and when the first board selection number si is logic "1", select Wi. Binary number Z.

and when the second selection board number t1 is logic "O", vl is set, and the second selection board number 1. has four selection circuits that generate and output an m-bit binary number Q8 as a result of selecting Wi when is logic "1", and two (6Xm)-bit 2
Base number A= (X+, Xgi..., Xi-,, Xi), B=
CYi, Y2. ..., Yl-+, Y1) and the auxiliary human power r, the (lXm)-bit binary number C= (Z, Z t, -1Z, -3, Z, ) and (#Xm)-bit binary numbers D-(Q, , Q, . . . , QtL-, , QI) of the sum of A, B, and 1 are generated and output.

Furthermore, the adder circuit of the present invention manually inputs two m-bit binary numbers Xi and YI, and generates an m-bit first binary number Vi of the sum of Xi and Yi, and an upper m-bit binary number Vi of the sum of Xi and Yi. 1st to digit
Generate a carry output g8, an m-bit second binary number W of the sum of Xi, Yi, and 1, and a second carry output pt to the upper digit of the sum of Xi, Yi, and 1. Of the two unit adder circuits that output, and (l-
1) The first (for G) output from the unit adder circuits.
Carry output g z, g s,..., gt, (β~
1) second carry output p! , p 3. ..., p
Well, input the auxiliary human power and enter the logical formula % formula %: jt=gi++ + p i++'gi conflict! + p
i*IHp i orderz° gt dispute s+1 + p l4I
Hp Breath◆t ' ”” p E -1° g
history"pI+1pl+2"0'pt-1'pt(1≦i
≦I! -2), t Q-, =g +pet.

Generate and output one first selection board number s1, sl, ..., 51 and one second selection board number t+, h, ..., t, where t, = 1. and one first binary number Vi, Vi, . . . outputted from the one unit addition circuit.
・, ■, one binary number Vi and one second 2
One binary number W from the base numbers Wi, Wi, ..., Wi
1, and the four first signals output from the selection signal generation circuit.
Board selection number S, Sgi..., 1st of 5g
Selection board number S, and four second selection board numbers, t,...
, t, and when the first JA selection board si is logic "0", Vi
, when the first selection board number si is logic "1", the m-bit binary number Z! as a result of selecting WL. and the second selection board number 1. m-bit binary number Q as a result of selecting V8 when t8 is logic "0" and selecting Wi when the second board selection number t8 is logic "1".

one selection circuit that generates and outputs g, and one first carry output g+, g output from the four unit adder circuits.
z,..., gII and one second carry output p7, p
2,..., pi are input, and the first representative carry signal G and the second representative carry signal P are
and a carry signal generation circuit that generates and outputs a two (IXm) bit binary number A= (Xi, Xi, . . .
・, Xi-1, Xi), B −(Y+, Yt,...
, Yg −+, Yt ) and the auxiliary human power r, the (#Xm)-bit binary number C=(Z+, Zz, . . . , Z, −1, 2Q), and the (IXm)-bit binary number D of the sum of A, B, and 1 = (Q,,Q!,...,Q,-1,Q,),
Carry signal G to the upper digit of the sum of A and B, A, B, and 1
A carry-over signal P to the upper digit of the sum of the sum and the signal P is generated and output.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, the adder circuit 600 is composed of three unit adder circuits 601, 602, and 603, one selection signal generation circuit 620, and three selection circuits 631, 632, and 633. 12-bit binary number X = (x
+, Xz, Xz) = (X+, Kt, -1X+z),
Y = [Yl, Yt, Ys) = (Y +, Y z
, ..., 3'+t) and the auxiliary human power r, the 12-bit binary number Z= (Z+, Zz, Zs) = (2+, 2gi"',
Outputs 21.

The unit addition circuit 602 inputs 4 bits XZ of the 12-bit input binary numbers X and Y = (XS, Xb, X], X II)
5YZ=0'5.3'6, yt, 3's) manually, the sum of X2 and Y2 Vz= (V5.V 6.V ), Va) and the upper digit of the sum of X2 and Y2 Carry output g2 to Xt and Y2
and 1, W2 = (w5, W6.W), W@), and carry output p2 of the sum of X2, Y2, and 1 to the upper digit.
Outputs .

For example, the unit addition circuit 602 is as=Xs・ys% I)S=X5■y5\ah”Xh
-Ybs bh=XbeYh-a Fu=Xt・Y? s
b? ＝x、■Yqsa馋＝ ``l')'
6% bl = X @ΦyII~gg=as
+bSHa, +b5・bh-aq+ b 5- b h
・b 1・a s %pz=bs・b,・b,,b.

(or gt+bsbh, bl, b++), Vs=b
se (a, +b&・a7+b,・b, -a,,), ws
=bse <a6+b6-al+b6・bl・a@+b6-bl-
bB), v, = b6■(at+by・a*), w6=b,■ (a, 4- b7- a 1.+ b
,,ba), vt=bteas, w,=b, ■ (ae+bs).

The unit addition circuit 601 calculates the upper 4 bits of the 12-pin input binary numbers X and Y, X+=(X+, It inputs and outputs the sum Vi=(v,,Vz,v3.v,) of Xi and Yi and the sum Wi=(w,,w2,Wko,wa) of Xi, Yl, and 1.

The unit addition circuit 601 can be realized by a logic circuit similar to the unit addition circuit 602, and in this embodiment, carry outputs g+, p+
is not used.

The unit addition circuit 603 receives the lower 4 bits of the 12-bit input binary numbers X and Y, Xs-(Xl, X111.Xt+, X+z)-
.

Y−+= (Yq, yIo, Y++, Y+t)
Input the sum of X3 and Yi, V3"' (V9. VIO, Vll, V+z),
Carry output g of the sum of Xi and Yi to the upper digit.

and the sum Wi of X3, Yi, and 1 = [wq, Wi,, Wi+, WI! ] and a carry output p3 to the upper digit of the sum of Xi, Yi, and 1.

The unit addition circuit 603 can be realized by a logic circuit similar to the unit addition circuit 602.

The selection signal generation circuit 620 includes unit addition circuits 602 and 60.
The carry outputs gt, pz, g5, pi outputted from 3 and the auxiliary human power r are inputted, and selection signals s1 and sgis2 that form the logical formula % are output.

The selection circuit 631 inputs the binary numbers Vi and Wi outputted from the unit addition circuit 601 and the selection signal s1 outputted from the selection signal generation circuit 620, and selects the selection signal si when the logic "
0”, Z + =V I= (V +, VgiVi, V4)
, when the selection signal s1 is logic "1", it outputs the binary number Z+= (21, 22, zs, Zm) such that 7, , =Wi= (w,, w,, tvl, w4).

For example, the selection circuit 631 z,=sl−Vi+5. °Wi.

Zg=51'Vg+SI'W2, z3=sl'v3+sl'wl, Z, =S, ・V4+S, -W.

This can be achieved using the following logic.

The selection circuit 632 inputs the binary numbers Vi and Wi outputted from the unit addition circuit 602 and the selection signal s2 outputted from the selection signal generation circuit 620, and similarly to the selection circuit 631, the selection signal S- is logical. When the selection signal s2 is "0", v2 is output, and when the selection signal s2 is logic "1", w2 is output as a binary number Z2.

Selection port 1"11'・,゛) is also the selection circuit 631.6
Similarly to 32, a binary number Z is generated and output in response to the input of the binary numbers Vi, Wi and the selection signal S.

The selection circuits 632 and 633 can be realized by logic circuits similar to the selection circuit 631.

FIG. 2 is a block diagram showing a second embodiment of the present invention, and the addition circuit 700 of this embodiment is the selection signal generation circuit 620 in the addition circuit 600 of the first embodiment shown in FIG.
The functions of the selection circuits 631, 632, and 633 are strengthened.

In FIG. 2, the adder circuit 700 is composed of three unit adder circuits 701, 702, and 703, one selection signal generation circuit 720, and three selection circuits 731, 732, and 733. 12-bit binary number X = (X +, Xz, Xs) - (X +,
l, ..., X+z), Y= (Y+, Yz, Yi)=
Input (y+, 3'z, ..., y+z) and the auxiliary human power r, and enter the 12-bit binary number Z= (Z+, Zz, Zz) = (Z+, 2z, -12
+z) and the 12-bit binary number Q, which is the sum of X, Y, and 1.
−(Q+, QCQ3) = (ql, Q z,...
, q12].

Since the unit adder circuits 701, 702, and 703 are similar to the unit adder circuits 601, 602, and 603 in the adder circuit 600 of the first embodiment shown in FIG. 1, a detailed explanation thereof will be omitted.

The selection signal generation circuit 720 includes unit addition circuits 702.70
Carry output gz, pz, gs, p3 output from 3
and auxiliary human power r are input, and a selection signal sH, t, , sz, t2 . Outputs sco,t.

The selection circuit 731 inputs the binary numbers v + and Wi outputted from the unit addition circuit 701 and the selection signals S1 and tl outputted from the selection signal generation circuit 720, and generates the selection signal s.
When i is logic “0”, Z + −V + = (V +, Vl, V3, V4)
, when the selection signal S1 is logic "l", the binary number Z+" (2+, 22.23, 24) becomes ZI=W+= (Wl, W2.Wl, w,), and the selection signal t1 is logic " 0”, Q,=Vi=
(v,,vz,v3.v4), selection signal t1 is logic “
1'', it outputs the binary number Q+= (q+, Qz, qz, qa) where Q,=W1= (w,, wz, w31w4).

For example, the selection circuit 731 z,=9. - v, +51-wl.

Q+=E+°v+ + L 1 ' W 1 %z, =
sl'Vt+SI'W2, q z= L 11V@ + L 1' WZ%Z1
=51'vl+31' W2S q3°t, 6vl+t, -w,.

z, = s, + Vi+3. -Wi, qa"j+ ・v4+t, -w4 This can be achieved using the following logic.

The selection circuit 732 inputs ■2, Wi outputted from the unit addition circuit 702 and selection signals S2, t2, and the selection circuit 733 inputs V3, Wi outputted from the unit addition circuit 703.
Input Wi and selection signals S1, t, and select 2
It outputs the base numbers Z,,Q, and Zl,Q3.

The selection circuits 732 and 733 can be realized by logic circuits similar to the selection circuit 731.

FIG. 3 is a block diagram showing a third embodiment of the present invention, and an adder circuit 800 of the present embodiment provides a carry signal to a circuit similar to the adder circuit 700 of the second embodiment shown in FIG. A generation circuit 840 is added.

In FIG. 3, the addition circuit 800 includes three unit addition circuits 801.802.803, one selection signal generation circuit 820, and three selection circuits 831.832.833.
It consists of one carry signal generation circuit 840 and two 12-bit binary numbers X = (Xt, Xz, Xs) = (Xt, xz, . . .
, x, 2], Y = CY+, Y*, Yz) = (V
＋、Y! , ``', )' 12) and auxiliary manpower ``
Input the 12-bit binary number Z= (Z+, Zt, Zs)= (2+, 2z, ・=,
212) and the 12-bit binary number Q, which is the sum of X, Y, and 1.
= (Q,,Q,,Q3)=(Q+,qz,...,
qI2), a carry signal G for the sum of X and Y to the upper digit, and a carry signal P for the sum of X, Y, and 1 to the upper digit.

The unit addition circuits 801, 802.803, selection signal generation circuit 820, and selection circuits 831.832.833 are
Unit addition circuits 701, 702, 703, selection signal generation circuit 720, and selection circuit 700 of the second embodiment shown in FIG. 31, 732, and 733, detailed description thereof will be omitted.

The carry signal generation circuit 840 is a unit addition circuit 801゜8.
Carry output g7, pl, g output from 02, 803
z.

Input p2, gx, and px, respectively, and select G” g I
+ pI-g t + p +・pI・g3, P=pi
・Output representative carry signals G and P that become pz-ps.

FIG. 4 is a block diagram showing a fourth embodiment of the present invention, and an adder circuit 6000 of this embodiment has the same configuration as the adder circuit 600 of the first embodiment shown in FIG. Adder circuit 80 of the third embodiment shown in FIG. 3 as an adder circuit
This uses a circuit in which the auxiliary human power of 0 is set to 0.

In FIG. 4, an adder circuit 6000 includes three unit adder circuits 6001, similar to the adder circuit 600 of the first embodiment.
．． 6002.6003 and one selection signal generation circuit 60
20 and three selection circuits 6031.6032.6033
It consists of two 36-bit binary numbers A = (l+, Az, Ai) = (at, at, -, a
ss), B=CBl, Bt, B2)= (b+, bz,
..., 1) + 6) and the auxiliary human power R, A and B
36-bit binary number c = (c + , C2, Cz) = (c +,
c z, -1CB6).

The unit addition circuit 6002 is the addition circuit 80 of the third embodiment.
Since this is a circuit in which the auxiliary human power r (rz) of 0 is set to "0", there are three unit addition circuits, one selection signal generation circuit,
Consisting of three selection circuits and one carry signal generation circuit, two 12 vias) binary number Ag = (a + z, a + 4, ° ° °, a B4)
−(X+, Xz, Xs), B2= (b+3.b+a,..., b24]=[Yl
, Yzl, Yi) and enter the 12-bit binary number of the sum of At and 82 ■2
= (vIiv14, °°°, V 24) = [Zl, Zz
, Zi) and a carry signal G2 to the upper digit of the sum of Ax and 82,
A carry signal P2 to the upper digit of the sum of At, B2, and 1 is output.

The unit addition circuit 6001 calculates the 12-bit binary number A+=(
at, az,...', a+z), B+=(b+, bt,
..., b1□], the sum of A1 and B, V+ = (V+, Vz, "・, v, l), and A1, B1, 1, and nT1 Wi = (w,, Wgi-, Output Wirit.

The unit addition circuit 6003 inputs a 12-bit binary number A x
= (a zs, a th, ”', 83 &) ~Bx
= Cbts, bth, ”', b 36),
The sum of A, B, and 1 is V2'' CVt5. w, 6. ”', W S&),
Carry output G of the sum of A and B to the upper digit.

Carry output P of the sum of , A, B, and 1 to the upper digit,
Outputs .

Unit addition circuits 6001 and 6003 are unit addition circuits 60
Similarly to 02, this is a circuit in which the auxiliary human power r (rt % +2) of the addition circuit 800 of the third embodiment is set to "0",
In this embodiment, the carry output G of the unit addition circuit 6001.

P+ is not used.

Selection signal generation circuit 6020 and selection circuit 6031.6
The operations of the circuits 032 and 6033 are the same as those of the selection signal generation circuit 620 and selection circuits 631, 632, and 633 in the adder circuit 600 of the first embodiment shown in FIG. 1, so a detailed explanation thereof will be omitted.

FIG. 5 is a block diagram showing a fifth embodiment of the present invention, and an adder circuit 7000 of this embodiment has the same configuration as the adder circuit 700 of the second embodiment shown in FIG. Adder circuit 80 of the third embodiment shown in FIG. 3 as an adder circuit
This circuit uses a circuit in which the auxiliary human power r is set to "0".

In FIG. 5, an adder circuit 7000 includes three unit adder circuits 7001, similar to the adder circuit 700 of the second embodiment.
．． 7002.7003 and one selection signal generation circuit 70
20 and three selection circuits 7031.7032.7033
It consists of two 36-bit binary numbers A = (l+, At, A, +) = (at, ax,...
・,B3. ], B= CB+, Bt, Bs)= (b+
, bt, ..., b36] and the auxiliary human power R,
36-bit binary number C = (Ct, Cz, C5) = (c+, cz,...
・, C16] and the 36-bit binary number D = (D+, Dz, Dzl = (d +,
d2,...,d36].

The unit addition circuit 7002 is the addition circuit 80 of the third embodiment.
Since it is a circuit with 0 auxiliary human power "(r2)" as "θ", it requires three unit addition circuits, one selection signal generation circuit,
Consisting of three selection circuits and one carry signal generation circuit, two 12-bit binary numbers A@= (a 13.a 14.°'°, a 24)-
(X 1X!, X s), Bz= Cb+x, bla,..., bzi)=(Y+
, Yz, Y s ), and input the 12-bit binary number vt of the sum of At and B2.
"cVIIVI4."', v24] = (Z+, Zz
, Zs), a carry signal Gt to the upper digit of the sum of A2 and B,
A carry signal P to the upper digit of the sum of A□, B2, and 1 is output.

Unit addition circuits 7001 and 7003 are also unit addition circuits 700
2, this is a circuit in which the auxiliary human power r (r+, rs) of the addition circuit 800 of the third embodiment is set to "O", and A.

For the inputs of and B, let vl, WI, G1 and P, and A,
and Vi, Wi, G3, and P for the human power of B'+.

In this embodiment, G, and P are generated.

is not used.

Selection signal generation circuit 7020 and selection circuit 7o31.7
The operation of 032.7033 is similar to the selection signal generation circuit 720 and the selection circuits 731, 732.733 in the adder circuit 700 of the second embodiment shown in FIG. 2, so a detailed explanation thereof will be omitted.

FIG. 6 is a block diagram showing a sixth embodiment of the present invention, and an adder circuit 8000 of this embodiment has the same configuration as the adder circuit 800 of the third embodiment shown in FIG. The adder circuit also uses a circuit in which the auxiliary human power r of the adder circuit 800 is set to "0".

In FIG. 6, an adder circuit 8000 includes three unit adder circuits 8001, similar to the adder circuit 800 of the third embodiment.
．． 8002.8003 and one selection signal generation circuit 80
20 and three selection circuits 8031.8032.8033
and one carry signal generation circuit 8040, and two 36-bit binary numbers A = (l+, AgiAs) - (a +, at, -
, ash], B, = (Bl, Bz, Bx) = (b+
, b3. ..., b 36) and auxiliary human power R to generate a 36-bit binary number C"" (C+, Cz, G3)" (C+, Cz,...
”, C36) and 2 of the 36 bits of the sum of A, B, and 1.
Base number D = CD,, B2, Dko) = (dl, dl,
..., dl,], a carry signal E of the sum of A and B to the upper digit, and a carry signal F of the sum of A, B, and 1 to the upper digit.
Outputs .

The unit addition circuit 8002 is the addition circuit 80 of the third embodiment.
Since this is a circuit in which the auxiliary human power r(r2) of 0 is set to "O", there are three unit addition circuits, one selection signal generation circuit,
It is composed of three selection circuits and one carry signal generation circuit, and generates two 12-bit binary numbers Az= (a Ill, a 14. = ., a 1
4) = (X 1. X t, X 3), Bz = C
blz, bra, ..., b24] = (Yi, Yi,
ys), and input the 12-bit binary number Vt of the sum of A2 and B2.
−(V's, V+m, ..., vza]= (Z
+, Zt, Zs) and a carry signal G to the upper digit of the sum of A2 and 82.

A carry signal Pt to the upper digit of the sum of A2, B, and 1
Outputs .

The unit addition circuits 8001 and 8003 are also unit addition circuits 80
02, this is a circuit in which the auxiliary input r (rl, rl) of the adder circuit 800 of the third embodiment is set to 0'', and A
, and Bl (Vi, Wi, G, and P for 0 human power.

and Vi, Wi, and G for the inputs of As and B3.

and P, respectively, are generated and output.

Selection signal generation circuit 8020, selection circuit 8031.803
2.8033 and the operation of the carry signal generation circuit 8040 are similar to the selection signal generation circuit 820 and the selection circuit 831.832 in the addition circuit 800 of the third embodiment shown in Section 3.
．． 833 and carry signal generation circuit 840, detailed explanation thereof will be omitted.

〔Effect of the invention〕

As explained above, the present invention eliminates the need for an auxiliary input, which in conventional adder circuits is generated sequentially from the highest carry signal generation circuit to the lower order, and is necessary for the unit adder circuit to generate a binary number for the sum. First, a unit adder circuit that outputs a binary number that is the sum of two input binary numbers and a binary number that is the sum of the two input binary numbers, and a selection signal generation circuit at the highest level. By using a selection circuit that selects either of the two summed binary numbers using a selection signal generated from carry information at This has the effect of reducing time.

Further, since the increase in calculation time is small even for binary numbers with a large number of bits, it is possible to obtain an adder circuit suitable for speeding up calculations.

Furthermore, post-addition processing, such as normalization shift of operation results, parity generation, leading zero, etc., is prepared before input to the selection circuit, that is, at the time of output of the unit addition circuit, and other processing is performed within the selection circuit. Since it is relatively easy to incorporate part or all of the post-addition processing into the system, it is possible to speed up not only the addition circuit but also the entire data processing device including the addition logic.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, FIG. 3 is a block diagram of a third embodiment of the present invention, and FIG. The figure is a block diagram of the fourth embodiment of the present invention, FIG. 5 is a block diagram of the fifth embodiment of the present invention, FIG. 6 is a block diagram of the sixth embodiment of the present invention, and FIG. FIG. 1 is a block diagram showing an example of a conventional adder circuit. In the figure, 600.700.800.6000.7000.800
0...Addition circuit, 601-603, 701-703, 801-803.6
001~6003.7001~7003.8001~8
003...Unit addition circuit, 620.720.820.6020.7020.802
0... Selection signal generation circuit, 631-633, 731-733.831-833.6
031~6033.7031~7033.8031~8
033...Selection circuit, 840.8040...Carry signal generation circuit. Bodhisattva IWJ $-2m 3rd figure grass 4I! ] Kaya SvJ Figure 6 Figure 7 Written amendment to procedure (voluntary)

Claims (4)

[Claims] (1) Two m (positive integer) bit binary numbers X_i, Y_
input i, m-bit first binary number V_i of the sum of X_i and Y_i, first carry output g_i to the upper digit of the sum of X_i and Y_i, and sum of X_i, Y_i, and 1. m
l (positive integer) unit adder circuits that generate and output a second binary number W_i of bits and a second digit up output p_i to the upper digit of the sum of X_i, Y_i, and 1; (l-1) first carry outputs g_2, g_3 output from (l-1) unit adder circuits of the unit adder circuits
,...,g_l and (l-1) second carry outputs p_2
, p_3, ..., p_l and the auxiliary input r are input, and the logical formula s_i=g_i_+_1+p_i_+_1・g_i_+
_2+p_i_+_1・p_i_+_2・g_i_+_
3+…+p_i_+_1・p_i_+_2・…・p_l
＿−＿１・g＿l＋p＿i＿＋＿１・p＿i＿＋＿２・
...・p_l_-_1・p_l・r (1≦i≦l-2), s_l_-_1==g_l+p_l・r, s_l=r Generate and output l selection signals s_1, s_2, ..., s_l a selection signal generation circuit; and l first 2 outputs from the l unit adder circuits;
One binary number V_i among the base numbers V_1, V_2, ..., V_l and l second binary numbers W_1, W_2, ..., W
One binary number W_i of _l and l selection signals s_1, s_2, . . . output from the selection signal generation circuit.
, s_l, and selects V_i when the selection signal s_i is logic "0" and selects W_i when the selection signal s_i is logic "1". and l selection circuits that generate and output a bit binary number Z_i, and two (l×m) bit binary numbers A=[X_1, X_2, ..., X_l_-_1, X_l]
, B=[Y_1, Y_2, ..., Y_l_-_1, Y_l
] and auxiliary input r as inputs, and the sum of A, B, and r (
l × m) bit binary number C = [Z_1, Z_2, ..., Z_l_-_1, Z_l]
An addition circuit characterized by generating and outputting. (2) Two m (positive integer) bit binary numbers X_i, Y_
input i, m-bit first binary number V_i of the sum of X_i and Y_i, first carry output g_i to the upper digit of the sum of X_i and Y_i, and sum of X_i, Y_i, and 1. m
l (positive integer) unit adder circuits that generate and output a second binary number W_i of bits and a second digit up output p_i to the upper digit of the sum of X_i, Y_i, and 1; (l-1) first carry outputs g_2, g_3 output from (l-1) unit adder circuits of the unit adder circuits
,...,g_l and (l-1) second carry outputs p_2
, p_3, ..., p_l and the auxiliary input r are input, and the logical formula s_i=g_i_+_1+p_i_+_1・g_i_+
_2+p_i_+_1・p_i_+_2・g_i_+_
3+…+p_i_+_1・p_i_+_2・…・p_l
＿−＿１・g＿l＋p＿i＿＋＿１・p＿i＿＋＿２・
…・p_l_−_1・p_l・r (1≦i≦l−2), s_l_−_1=g_l+p_l・r, s_l=r, t_i=g_i_+_1+p_i_+_1・g_i_+
_2+p_i_+_1・p_i_+_2・g_i_+_
3+…+p_i_+_1・p_i_+_2・…・p_l
＿−＿１・g＿l＋p＿i＿＋＿１・p＿i＿＋＿２・
...・p_l_-_1・p_l (1≦i≦l-2), t_l_-_1=g_l+p_l, t_l=1 l first selection signals s_1, s_2, ..., s_l
and a selection signal generation circuit that generates and outputs l second selection signals t_1, t_2,..., t_l; and l first selection signals output from the l unit adder circuits.
One binary number V_i among the base numbers V_1, V_2, ..., V_l and l second binary numbers W_1, W_2, ..., W
one binary number W_i of _l and l first selection signals s_1, s_2 output from the selection signal generation circuit
, ..., s_l, one first selection signal s_i and l
one second selection signal t_i among the second selection signals t_1, t_2, ..., t_l is input, and when the first selection signal s_i is logic "0", V_i is inputted to the first selection signal t_i. When the signal s_i is logic "1", the m-bit binary number Z_i resulting from selecting W_i and the second selection signal t_i
is logic “0”, V_i is set to the second selection signal t_
When i is logic "1", it has l selection circuits that generate and output an m-bit binary number Q_i as a result of selecting W_i, and two (l×m)-bit binary numbers A. = [X_1, X_2, ..., X_l_-_1, X_l]
, B=[Y_1, Y_2, ..., Y_l_-_1, Y_l
] and auxiliary input r as inputs, and the sum of A, B, and r (
l × m) bit binary number C = [Z_1, Z_2, ..., Z_l_-_1, Z_l]
and the (l×m)-bit binary number D of the sum of A, B, and 1 = [Q_1, Q_2, ..., Q_l_-_1, Q_l]
An adder circuit characterized in that it generates and outputs. (3) Two m (positive integer) bit binary numbers X_i, Y_
input i, m-bit first binary number V_i of the sum of X_i and Y_i, first carry output g_i to the upper digit of the sum of X_i and Y_i, and sum of X_i, Y_i, and 1. m of
l (positive integer) unit adder circuits that generate and output a second binary number W_i of bits and a second digit up output p_i to the upper digit of the sum of X_i, Y_i, and 1; (l-1) first carry outputs g_2, g_3 output from (l-1) unit adder circuits of the unit adder circuits
,...,g_l and (l-1) second carry outputs p_2
, p_3, ..., p_l, and the auxiliary input r are input, and the logical formula s_i=g_i_+_1+p_i_+_1・g_i_+
_2+p_i_+_1・p_i_+_2・g_i_+_
3+…+p_i_+_1・p_i_+_2・…・p_l
＿−＿１・g＿l＋p＿i＿＋＿１・p＿i＿＋＿２・
…・p_l_−_1・p_l・r (1≦i≦l−2), s_l_−_1=g_l+p_l・r, s_l=r, t_i=g_i_+_1+p_i_+_1・g_i_+
_2+p_i_+_1・p_i_+_2・g_i_+_
3+…+p_i_+_1・p_i_+_2・…・p_l
＿−＿１・g＿l＋p＿i＿＋＿１・p＿i＿＋＿２・
...・p_l_-_1・p_l (1≦i≦l-2), t_l_-_1=g_l+p_l, t_l=1 l first selection signals s_1, s_2, ..., s_l
and a selection signal generation circuit that generates and outputs l second selection signals t_1, t_2,..., t_l; and l first selection signals output from the l unit adder circuits.
One binary number V_i among the base numbers V_1, V_2, ..., V_l and l second binary numbers W_1, W_2, ..., W
one binary number W_i of _l and l first selection signals s_1, s_2 output from the selection signal generation circuit
, ..., s_l, one first selection signal s_i and l
one second selection signal t_i among the second selection signals t_1, t_2, ..., t_l is input, and when the first selection signal s_i is logic "0", V_i is inputted to the first selection signal t_i. When the signal s_i is logic “1”, the m-bit binary number Z_i as a result of selecting W_i and the second selection signal t_i
is logic “0”, V_i is set to the second selection signal t_
l selection circuits that generate and output an m-bit binary number Q_i as a result of selecting W_i when i is logic "1"; and l first selection circuits output from the l unit adder circuits; Input the carry outputs g_1, g_2, ..., g_l and l second carry outputs p_1, p_2, ..., p_l, and form the logical formula G=g_1+p_1・g_2+p_1・p_2・g_3
+...+p_1・p_2・...・p_l_-_1・g_l,
A first representative carry signal G and a second representative carry signal P where P=p_1・p_2・...・p_l
and a carry signal generation circuit that generates and outputs two (l×m) bit binary numbers A = [X_1, X_2, ..., X_l_−_1, X_l]
, B=[Y_1, Y_2, ..., Y_l_-_1, Y_l
] and auxiliary input r as inputs, and the sum of A, B, and r (
l × m) bit binary number C = [Z_1, Z_2, ..., Z_l_-_1, Z_l]
and the (l×m)-bit binary number D of the sum of A, B, and 1 = [Q_1, Q_2, ..., Q_l_-_1, Q_l]
, a carry signal G to the upper digit of the sum of A and B, and A and B.
1. An adder circuit that generates and outputs a carry signal P to a high-order digit of the sum of 1 and 1. (4) The unit addition circuit inputs two m-bit binary numbers X_i and Y_i, and
an m-bit first binary number V_i of the sum of i and Y_i;
First carry output g_ to the upper digit of the sum of X_i and Y_i
i, the second 2 of m bits of the sum of X_i, Y_i, and 1
l unit adder circuits that generate and output the base number W_i and the second digit up output p_i to the upper digit of the sum of X_i, Y_i, and 1; 1) (l-1) first carry outputs g_2, g_3, ..., g_l output from the unit adder circuits and (l-1) second carry outputs p_2, p_3, ..., Input p_l and auxiliary input r, and formulate the logical formula s_i=g_i_+_1+p_i_+_1・g_i_+
_2+p_i_+_1・p_i_+_2・g_i_+_
3+…+p_i_+_1・p_i_+_2・…・p_l
＿−＿１・g＿l＋p＿i＿＋＿１・p＿i＿＋＿２・
…・p_l_−_1・p_l・r (1≦i≦l−2), s_l_−_1=g_l+p_l・r, s_l=r, t_i=g_i_+_1+p_i_+_1・g_i_+
_2+p_i_+_1・p_i_+_2・g_i_+_
3+…+p_i_+_1・p_i_+_2・…・p_l
＿−＿１・g＿l＋p＿i＿＋＿１・p＿i＿＋＿２・
...・p_l_-_1・p_l (1≦i≦l-2), t_l_-_1=g_l+p_l, t_l=1 l first selection signals s_1, s_2, ..., s_l
and a selection signal generation circuit that generates and outputs l second selection signals t_1, t_2,..., t_l; and l first selection signals output from the l unit adder circuits.
One binary number V_i among the base numbers V_1, V_2, ..., V_l and l second binary numbers W_1, W_2, ..., W
one binary number W_i of _l and l first selection signals s_1, s_2 output from the selection signal generation circuit
, ..., s_l, one first selection signal s_i and l
one second selection signal t_i among the second selection signals t_1, t_2, ..., t_l is input, and when the first selection signal s_i is logic "0", V_i is inputted to the first selection signal t_i. When the signal s_i is logic "1", the m-bit binary number Z_i resulting from selecting W_i and the second selection signal t_i
is logic “0”, V_i is set to the second selection signal t_
l selection circuits that generate and output an m-bit binary number Q_i as a result of selecting W_i when i is logic "1"; and l first selection circuits output from the l unit adder circuits; Input the carry outputs g_1, g_2, ..., g_l and l second carry outputs p_1, p_2, ..., p_l, and form the logical formula G=g_1+p_1・g_2+p_1・p_2・g_3
+...+p_1・p_2・...・p_l_-_1・g_l,
A first representative carry signal G and a second representative carry signal P where P=p_1・p_2・...・p_l
and a carry signal generation circuit that generates and outputs two (l×m) bit binary numbers A=[X_1, X_2, ..., X_l_−_1, X_l]
, B=[Y_1, Y_2, ..., Y_l_-_1, Y_l
] and auxiliary input r as inputs, and the sum of A, B, and r (
l × m) bit binary number C = [Z_1, Z_2, ..., Z_l_-_1, Z_l]
and the (l×m)-bit binary number D of the sum of A, B, and 1 = [Q_1, Q_2, ..., Q_l_-_1, Q_l]
, a carry signal G to the upper digit of the sum of A and B, and A and B.
Claim 1, characterized in that the adder circuit is an adder circuit in which the auxiliary input r of the adder circuit that generates and outputs a carry signal P to the upper digit of the sum of The addition circuit according to item 2 or 3.