JPS62232062A - Bus width controller - Google Patents

Abstract

PURPOSE:To eliminate one clock that is additional for purposes of the interpretation of a port-width response signal and the relocation of a data block by providing an address discriminating means and a port-width holding means. CONSTITUTION:An address discriminating circuit 111 as the address discriminating means, discriminates to what area the physical address on an address bus 104 corresponds, and outputs the result of the discrimination as an address are information 113. A port-width holding register 112 as the data-bus port-width information holding means, holds the information of the width port for data-bus for a memory device or a peripheral equipment in each physical address space. The content of the register 112 is able to be written in or read out. The register 112 also outputs the data-bus port-width of a memory device or a peripheral equipment programmed in correspondent area as a port-width information 121 at the time when an address area information 113 is inputted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bus used in a microcomputer system in which the data bus width is changed according to the data bus port width and address of a memory device or peripheral device to which it is connected. The present invention relates to a width control device, and particularly relates to a bus width control device that does not require input of a data bus port width information signal from the outside.

[Conventional technology]

As integrated circuit technology advances, the word length of microcomputer systems has increased from 4 bits to 8 bits, from 8 bits to 16 bits, and more recently to 3 bits, which is comparable to minicomputers.
It has expanded to 2 bits.

In general, a microcomputer system with a long word length can handle a large amount of information at once, thereby significantly improving the functionality and performance of the computer. When a microcomputer system is used to refer to large databases, process Japanese characters with long character codes, and process images, an 8-bit microcomputer system is no longer able to handle the processing sufficiently, and it takes a long time. It can be said that the construction of a microcomputer system with word length is a requirement of the times.

The data that is manipulated by the microcombinator system by executing instructions is called operand data. Generally, in a microcomputer system, one byte is made up of 8 bits, which is used as a unit of data or instruction words, and each byte of data is assigned an address.

By the way, a microcomputer system with a long word length can be used with memory devices having different data bus port widths such as 8 bits, 16 bits, and 32 bits! Alternatively, when connecting to a peripheral device, it is necessary to control the data transfer procedure to match the data bus port width of the transfer partner.

Bus width control (bus sizing) was born against this background, and it is based on the data bus port width of the memory device or peripheral device to which data is transferred, the length of the operand data to be transferred, The data transmission/reception procedure is adapted depending on three factors including the address of the transfer destination.

Here, the configuration and operation of a conventional bus width control device will be explained using the drawings. FIG. 7 shows an example of the internal configuration of a conventional bus width control device. 8th
The figure shows an example in which a memory having a 16-pit width data bus port is connected to a conventional microcomputer system that performs bus width control. Further, FIG. 9 is a timing chart showing the operation of the conventional bus width control device when 32-bit operand data is transferred to the memory shown in the eighth factor.

First, an example of the internal configuration of a conventional bus width control device will be described with reference to FIG. Transfer data length holding device 2215
is the operand length initial information 2 from the instruction decoder 2251
252 and the active byte number information 2214 from the active byte number determining device 2211, 2-bit transfer data length information 2216 is formed and output. The active byte number determination unit 2211 is configured to determine the number of active bytes by the 2 output from the data bus port width response logic of the memory or peripheral element.
Data bus port width response signal 2243, transfer data length information 2216, and lower 2 bits of physical address Al
, AO, the number of bytes of the data bus that can be effectively used for transfer is determined, and active byte number information 2214 is output. 77 tot control device 2213 has active byte number information 2
214, a shift control signal 2253 is output. Cheetah block placement control device 2212U transfer data length information 2216 and physical address lower two bits) Al.

A placement control signal 2254 is output based on the AO.

The physical address generation device 2221 updates the physical address related to the transfer of the same operand data every bus cycle based on the active byte count information 2214.

data bus port) 2261 is DP in byte units from the lower
O, DPl, BF2, BF3 O4 Noah'o y
Each block is connected to the 7th to 0th bits, the 15th to 8th bits, the 23rd to 16th bits, and the 31st to 24th bits of the external data bus 2231. Similarly, the buffer 2263 stores Bl;'O, BFI in byte units from the lowest.

The four blocks of BF2 and BF3 are standing together.

Operation 2 Dratsuchi 22651m! It consists of four blocks: OLO, OLI, OL2, and OL3 in byte units starting from the lowest. Block DP i (i=0.11213) of data bus port 2261 and buffer 22 according to multiplexer 2262i placement control signal 2254
63 blocks BFj<j=o, x, z, 3). Sick 2264 is shift iti control signal 2253
Under the control of block B of buffer 2263
(j=o, xi, 3) and block OLk (k=o, 1+2, 3) of the operand latch 2265 are connected. In the initial state, block BFj and OL are set so that j=
k is connected.

Next, the entire configuration of a conventional microcomputer system that performs full path width control will be explained using FIG.

FIG. 8 shows an example in which a 2-byte data bus port 1μ of memory is connected. Address decoder 2321 activates memory selection signal 2341 when the physical address is in this memory area.

The data bus port width response logic 2322 is essential to conventional bus width controllers, and the memory select signal 2322
When 41 becomes active, it outputs a data bus port width response signal 2243 indicating the data bus port width of the corresponding element. Byte selection logic 2323 is also essential for conventional bus width control devices, and transfer data length information 221
6 and the lower two bits of the physical address A1. Based on A.O.
A byte selection signal 2324 for selecting each of the upper byte and lower byte of the 2-byte wide memory is activated. AND gate 2332-0.1 is byte selection signal 2
When 324-0.1 and memory selection signal 2341 are both active, they each select memory device 2331-0.1. If the read/write control signal 2312 is at a high level, it specifies a read operation, and if it is at a low level, a write operation is specified for the memory device or peripheral device. The strobe signal 2311 specifies the timing for reading and writing data to a memory device or peripheral device.

Next, we will explain the operation of the conventional bus width control device using the timing chart in Fig. 9 for writing 4-byte data to an even address in a memory having a 2-byte data bus port width as shown in Fig. 8. explain.

The 32-bit operand data is divided into four data blocks, DBO, DBI, DB2, and DB3, in units of lower sibytes. At the beginning of the pass cycle,
Operand data is stored in operand latch 2265.

At the start of the first pass cycle (T=1), the shifter 2264 shifts blocks BFj and OLk so that j=
is connected to. As shown in FIG. 9, at the timing of SO, the transfer data length holding device 2215 outputs (00) as transfer data length information 2216, indicating that 4-byte length data is to be transferred. In response to this, the data block arrangement control device 2212 instructs the multiplexer 2262 to connect blocks DPi and BFj so that blocks i and BFj are connected. As a result, DBO and D15 are applied to D7 to DO of the data bus 2231 from the timing of Sl.
- DBI at D8, DB2 at D23-D16. D31~D
DB3 is output to 24. On the other hand, the byte selection logic 2323 shown in FIG.
, AQ are OO, and the transfer data length information 2216 indicates a length of 4 bytes, so it outputs (11) to select both memory devices as the byte selection signal 2324. As a result, data block DBO is stored in memory device f! L2331
-0, DBt is transferred to memory device 2331-IK.

The data bus port width response logic 2322 outputs a port width response signal 2 of (10) indicating a 2-byte width at timing 82.
Outputs 243. Active byte number determination device 221
1 determines this, and at timing 84, active byte number information 221 indicating that the active byte number is 2.
Outputs 4.

The shift control device 2213 has active byte number information 22
14, the number of bytes to shift in the next bus cycle is (2)
The shift control signal 2253 is output at timing 85.

At the SO timing of the second bus cycle (T=2), the physical address generation device 112221 adds 2 to the physical address in the first bus cycle and outputs the result.

In addition, the transfer data length holding unit [2215] subtracts the transfer data length value by 2 because the active byte number information 2214 is (2), and indicates 2 bytes at the SO timing (10).
Transfer data length information 2216 is output. The data block placement control device 2212 updates the address Al,
A placement control signal 2254 is output to the multiplexer 2262 from the AO and the transfer data length information 2216 at timing 81. Multiplexer 2262 and shifter 22
64 are blocks DPo, BF'O, and O under the control of the placement control signal 2254 and shift control signal 2253, respectively.
1, 2, blocks DPI, BFL, and Ol3 are connected. As a result, at timing 81, data bus 2231
D7~DO of DB2. DB3 outputs to DI5 to D8. Similarly to the first bus cycle, the selection signal 2324 is output, and the data block D82 is assigned to the memory device 2331-
〇, data block DB3 is memory device 2331-1
will be forwarded to. On the other hand, data bus port width response logic 23
22 outputs a vote width response signal 2243 of (10) indicating 2 bytes at timing 82. The active byte tt determination device 2211 determines this and outputs the active byte number information 2214 at the timing of S4, indicating that the active byte number is 2 bytes. Since the transfer data length holding device 2215 subtracts 2 from the held data length and the result is 0, it detects that all transfers related to this operand data have been completed, and as a result, it detects that all transfers related to this operand data have been completed. Enter the bus cycle.

In this way, the conventional bus width control device executes the connection control between the data bus and the data block that is required in the next bus cycle after receiving the data boat width response signal returned as a result of decoding the address output. There is. Further, a Lii logical circuit is provided which generates an element selection signal in units of bytes from the transfer data length information and address information output from the memory device and the peripheral device R(lj, bus width control device).

[Problem 3 to be Solved by the Invention The conventional bus width control device described above has the following drawbacks. First of all, a normal bus cycle basically consists of two clocks: address output and data confirmation, but with conventional bus width control devices, the memory or peripheral device port width is The period for interpreting the response signal and relocating the data block is l
I have to add more for the clock. For this,
Micro combinator 7 with conventional bus width control device
In the system, the transfer operation of operand data becomes a bottleneck, and the execution performance of instructions cannot be improved. Second, each memory device or peripheral device must have an external logic circuit in order to respond to the microcomputer with the data bus port width and to select the device ffJi in bytes.

For this reason, the circuit configuration of a microcomputer system using a conventional bus width control device has become complicated, and its implementation efficiency and reliability have been significantly reduced.

The present invention solves the above-mentioned drawbacks and provides a bus width control device that does not require any external circuitry.

[Means for solving problems]

The present invention provides data bus port width information holding means that divides an address space into a plurality of areas and holds data bus port width information for each area, and a physical address related to data to be transferred that exists in any area of the address space. address determining means for determining whether the data is to be transferred; transfer data length holding means for holding the length of data to be transferred; data bus port selection means for selecting a data bus port to be used for data transfer; The data bus port selection means has a data arrangement control means that corresponds to the selected data bus port, and a physical address update means that updates the physical address by the address corresponding to the transferred data, and the data bus port selection means selects the physical address of the transfer destination. The gist is that the data bus port to be used is selected based on the data length and data length.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 μ is a block diagram showing the configuration of an embodiment of the present invention. In this embodiment, a microcomputer system with 32 bits for both the internal data bus and the external data bus will be explained, but this does not mean that the present invention can be applied to 8 bits, 16 bits, or 32 bits.
This does not prevent it from being applied to microcomputer systems with lengths longer than 2 bits.

In FIG. 1, an address discriminating circuit 111 serving as address discriminating means discriminates to which area the physical address on the address bus 104 corresponds, and outputs the result as address area information 113. A port width holding register 112 serving as data bus port width information holding means holds information on the data passport width of a memory device or peripheral device for each area of the physical address space. The port width holding register 112 can read and write its contents, and when the address area information 113 is input, it is programmed in advance to determine the width of the memory device of the corresponding area [or the data bus port width of the peripheral device]. is output as port width information 121.

Transfer data length holding device 1 as transfer data length holding means
37 updates the transfer data length information 143 every bus cycle based on the operand length initial information 122 from the instruction decoder 103 and the acti-pno(item number information 123).
Output this.

Data block arrangement control device [13L shift control i1 &
161. Data bus port 132, multiplexer 13
3. The buffer 134, shifter 135, and operand latch 136 are data arrangement control means X described in the claims.
Configure. The data block placement control device ft131 is
Transfer data length information 143 and lower 2 bits of physical address
A1. From AO, corresponding control signal 1 every bus cycle
41 is updated and output. The shift control device 161 updates the shift control signal 142 from the active byte number information 123 and outputs it. The data bus port 132 has DPO and DPI in byte units starting from the lowest.

pP2. It is divided into four blocks of DP3. Each block DPO-DP3U, external data bus 1
05 7th to mO bits), 115th to 8th bits, 23rd bits
-16th bit and 31st to 24th bit, but only the byte corresponding to the active byte selection signal 152 is electrically connected to the data bus. Buffer 13
It is a 4U32-bit register, and it stores BFO, BFI, BF2 . BF3 (04M) Bu C1?
It is divided into /ri. Operand latch 136 is 32
Use pit register, OLO in byte units from the lower
, OLI, OL2. It is completed with oL3o4o blocks. Each block is connected to the 7th to Oth bits, the 15th to 8th bits, the 23rd to 16th bits, and the 31st to 24th bits of the internal data bus 101.

Inside the microcomputer, read/write of operand data is realized as a transfer operation with this operand latch 136, and the least significant bit of all operand data is handled so as to correspond to the least significant bit of the operand latch 136. One. Multiplexer 133 connects data bus port 13 under the control of corresponding control signal 141.
2 block DPi (s = o + 1 + 2 + 3
), block BFj of buffer 134 (j=0.1,
2, 3). Shifter 135 controls block BFj of buffer 134 under the control of shift control signal 142.
(j=o, 1, 2.a) and block 0Lk (k=0.1, 2.3) of the operand latte 136 are connected.

The byte selection control device 138 as a data bus port selection means includes boat width information 121 and transfer data length information 14.
3 and the lower 2 bits of the physical address Al and AO,
The byte selection signal 152 is updated and output every bus cycle. The byte selection signal 152 is a signal indicating an active data bus in byte units, and selects BEO from the lower byte.
.

BEI, BF2. It consists of four signals of BF3. Byte selection control device 138 outputs the number of active byte selection signals 152 as active byte number information 123.

Physical address generation device 1 as physical address update means
02 updates the physical address in each pass cycle based on the active byte count information 123, and updates the physical address with the address bus 104.
Output to.

Next, the operation of the transfer data length holding device 137 will be explained. Transfer data length holding device 137 updates transfer data length information 143 in synchronization with the bus cycle as described below. The number of bytes of the transfer data length is DL (T), the number of active bytes is W123, the number of bytes of the input active data bus is AB (T), and the initial data length of operand data is LO. Here, T represents the number of bus cycles, and T=1 for the first bus cycle. DL(T) is the value of the transfer data length information 143,
LO is the value of the operand data length initial information 122.

The transfer data length holding device 137 relates these variables as follows.

DL(1)=LO DL(T+1)=DL('1)-ABα)DL(T+
1) The transfer operation of one operand data ends at the T% bus cycle where =o. And transfer data length holding device [1
37 inputs the operand length initial information 122 again in order to transfer the next operand data.

If the number of bytes to be shifted in the bus cycle T is 8B ('l'), the shift control unit kl 61 has a shift of 8B (T
+1) = S B ('l') + AB (T) 8
B(1)-0, it operates as if it were combed. However, the above-mentioned update of the number of shift bytes to 88 (T%) is performed half a clock before the next bus cycle, and is output as the shift control signal 142. When DL(T+1)=O, 88(T+1)=
Set to 0.

The physical address generation unit 102 performs an address update operation in the following manner in one-operand data transfer. The physical address in bus cycle T is A D ('1), and the number of active bytes in bus cycle T is AB (T).
Then, AD (T+ 1) = AD (T) + AB (T
) The physical address generation device 102 performs a physical address update operation half a clock before a new bus cycle. Half a clock after the update operation, the address is output on address bus 104. The updating of the physical address using the active byte number information 123 continues until bus cycle T when DL(T+1)=0 in the transfer data length holding device 137.

Next, the function of the data block arrangement control device 131 will be explained. In order to enable data transfer with memory devices or peripheral devices having any data bus port width, the data bus port 132 is
The block in the buffer 7134 must be uniquely connected to the block in the buffer 7134. Attached Table 1 shows the connection method. For example, 1 byte of data is stored in the lower 2 physical addresses.
Bit A1. When transferring data to a memory device or peripheral device whose AO is 10, blocks DPQ and BFO, npl and BFO, BF2 and BFo, and BF3 and BFO are connected, respectively. For example, if 3 bytes of data is AIAO=
When transferring to memory device a or peripheral device at address 01, block DPO and B F Q%LJPI and L
IFo, BF2 and BF'l, and BF3 and BF2 are connected, respectively. The data block placement control device 131 is.

Based on the transfer data length information 143 and the lower two bits At and λ0 of the physical address, the multi-blephr 133 is caused to execute the connection correspondence shown in Attached Table 1 using the correspondence control signal 141. The placement control device 131 updates the corresponding control signal 141 in synchronization with the bus cycle.

Next, the function of the byte selection control device 138 will be explained. Generally, of the data bus divided into blocks in bytes, the block to which valid data is transferred is determined by the length of the data to be transferred, the address of the transfer destination, and the width of the data bus port of the transfer destination. . Attachment 2 shows the byte selection signal 152 activated by the byte selection control device 138 according to this relationship. In Attached Table 2, symbol B indicates port width information 121 of 1 byte, symbol W indicates port width information 121, symbol W indicates port width information 121 of 4 bytes, and symbol R indicates port width information 121 of 4 bytes. Byte selection activated by the byte selection control device 138 A signal 152 is shown.

For example, when transferring 1 byte of data to a memory or peripheral device whose address is AIAO = 11, if the data bus port width of the memory or peripheral device is 1 byte, BEO will not be active; When the data bus port width is 4 bytes, BF3 becomes active. For example, when transferring 4 bytes of data to a memory device or peripheral device with an address of AIAO=00, if the data bus port width of the memory device or peripheral device is 1 byte, BEO will not be active. When the bus port width is 2 bytes, BEQ and BEl are active, and when the data bus port width is 4 bytes, BEo, BEI, BF2, and BF3 are active. The port width information 121 is sent to the byte selection control device 138.
Based on the transfer data length information 143 and the lower two bits AI and AO of the physical address, the corresponding byte selection signal 152 shown in Attached Table 2 is activated.

Furthermore, the right side of Attached Table 2 shows the number of bytes of the data bus that becomes active in each of the above cases. for example,
When transferring 3-byte data to a memory or peripheral device with an address of Al, AO = OO, if the data bus port width of the transfer destination is 1 byte, the number of active bytes is 1, and the data bus port width is 2 bytes. , the number of active bytes is Vi2) and the data bus port width is 4.
When it is a byte, the number of active bytes is 3.

The byte selection control device 138 outputs active byte number information 123 having the values shown in Attached Table 2.

FIG. 2 shows a connection between a memory device having a 32-bit data bus port width and an example of the connection between the memory or peripheral device and the address bus and data bus in this embodiment.

In this example, the address bus is assumed to be 32 bits. Memory devices 405-0 to 405-3 are chips each having a data bus port width of 8 bits, and are connected to data buses 105-0 to 105-3 in byte units, respectively. 16-bit address bus 41 excluding lower bits
1 is connected to the address input of each memory device. The upper address bus 404 is the address decoder 4.
06 and the decoded result is the memory selection signal 40.
Output as 7. Four byte selection signals 152-0~
1゛52-3 is the memory selection signal 407 and AND gate 4
A logical product is performed with 00-0 to 400-3 and inputted to the chip selection of each memory element 405-0 to 405-3. Strobe signal 408 is input to the chip enable signal of each memory device. Read/write control signal 409
is input to read/write control of each memory device 405-0 to 405-3. With the above configuration, address decoder 4
A 32-bit data bus port width memory is implemented with a physical address area where 06 activates the memory selection signal 407. The bus width control device of this embodiment does not require special external circuits such as the byte selection logic and data bus width response logic described in the conventional example.

Next, the specific operation of this embodiment will be explained using an example. It is assumed that the port width holding register 112 has previously stored the information shown in Appendix 3 in a program.

First, the case of writing 4-byte data to address 00000000H will be described. The peripheral data bus port width of this area is 2 bytes±16 bits as shown in Appendix 3. For the purpose of explanation, we will use the block diagram in Figure 3 (A) @, the attached table 4 (5) (G) corresponding to Figure 3 (A (C)), and the timing chart in Figure 4. For each cycle, block DPi of data bus port 132, block BFj of buffer 134, and operand latch 1
36 shows connection correspondence with block OLk. The timing chart shows the bus cycle, clock, address output, byte selection signal 152, data output, and read/write.
The timing of the write signal 409 etc. is shown.

First, 4 bytes of data are stored in the operand latch 136. At timing 83 immediately before the first bus cycle T-1, the physical address generator ffff110
2 is the transfer destination address 00000 of this operand data
Holds 000H. Address discrimination circuit 111 discriminates the area of this address and notifies vote width holding register 112 with address area information 113. The vote width holding register 112 outputs 2-byte vote width information 121 at the SO timing. The physical address generation device 102 outputs a physical address onto the address bus l04 at the SO timing of T=l. On the other hand, since the operand data length initial value LO from the l decoder 103 is 4 bytes, the transfer data length holding device 137 sets the transfer data byte number DL(1)=LO=4 as the transfer data length information 143 and sets the SO timing. Output with . The shift control device 161 sets the number of bytes 5B(1)=O to the shift control signal 142 at the beginning of the bus cycle when 'l'=1.
It is output as . In addition, the data block arrangement control device 131 uses the correspondence between DPi and BFj shown in Attached Table 1, since the lower two bits (AI) and AO of the physical address are OO, and the number of transferred data bytes DL (1) = 4. , i.e. DPQ and BF'O, DPI and BFl, DP2 and BF2
．． The multiplexer 133 is instructed to connect DP3 and BF3 using the multi-to-many control signal 141. As a result, blocks OLo and BF.

and DPo, blocks OLI, BFI and DPl, blocks OL2, BF2 and DP2, blocks OL3 and BF
3 and DP3 are connected respectively.

On the other hand, the byte selection control device 138 has a vote width of 2 bytes, a transfer data length of 4 bytes, a physical address AI,
Since Ao is 00, according to the relationship shown in Attached Table 2,
Of the byte selection signals 152, BEQ and BEI are set to active level 1 and output from the SO timing. The number of bytes of active data at this time is AB(1)=2, and the byte selection control device 138 outputs this as active byte number information 123 at timing 81.

As a result, the operand latch 136, buffer 134, and data bus board 132 are connected as shown in FIG. Output to the 15th to 0th bits of bus 05.

At the end of the first bus cycle 'r=1, the transfer data length holding device 137 calculates the number of bytes of transfer data in the next bus cycle.

DL (2) = DL (1) - AB (1) = 4 - 2 = 2 God O
Therefore, it is decided to enter the second bus cycle related to this operand data transfer. At timing 83 of T=1, the shift control device 161 changes the number of shift bytes to 8.
B(2) = 8 B(1) 10A B(1) = O+
2=2 and output as the shift control signal 142. At timing 83 when 1 = 1, the physical address generation device 102 changes the physical address to 0 because AB (11 = 2).
0000002 Update to address H. The updated address is output onto the address bus 104 at the SO timing of T=2.

As in the case of the first bus cycle, the address determination circuit 111 determines the area, and the boat width information 12
As 1, 2 bytes are output at the SO timing of T=2. The transfer data length holding device 137 outputs the transfer data length information 143 of DL(2)=2 at the SO timing of the second bus cycle.

The byte selection control device 138 selects bytes according to the relationship shown in Attached Table 2 since the number of transfer data bytes DL (21 = 2, boat width is 2 bytes, physical address lower 2 bits) AI and AO = 10 at the SO timing. Signals 152 BEo and BEt are set to active level 1. 'Also, the number of active bytes E3(2)=2 is output as active byte number information 123 at timing 81. The data block placement control device 131 has a transfer data length of 2
Since the byte and physical addresses AI and AO are 10, the correspondence between DPi and BFj shown in Attached Table 1, that is, DP
O and BFo, DPt and BF'l, DP2 and B F O.

A corresponding control signal 141 instructing to connect DP3 and BFI is output at timing 81. As a result, DP
i, BFj, and OLk are connected correspondingly by a multiplexer 133 and a shifter 135 as shown in FIG.
Since BEl and l[0 of the byte selection signal 152 are active, the third operand data is selected at the timing of Sl.
The 1st to 16th bits are output to the 15th to Oth bits of the data bus.

At the end of the second bus cycle T = 2, the transfer data length holding unit f137 calculates the number of bytes of transfer data in the next bus cycle, and calculates the number of bytes of transfer data in the next bus cycle,
Since 2=0, the transfer bus cycle related to this operand data is ended. The shift control device 161 is 8
Number of bytes shifted in the primary bus cycle f at timing 3
: Update to dB(1)=O. The physical address generation device 102 holds the address of the next operand data at timing 83. In this way, the 4-byte operand data is directly converted to 00000000 (starting from the lower byte).
Address H to 00000003 Stored in memory at address H.

Next, as a second example, we will discuss the case where 2 bytes = 16 bits of data are read from address 000300011 (address 000300011).The peripheral data bus port width of this area is 2 bytes as shown in Appendix 3.For explanation, Block correspondence diagram of Figure 5 ■ (C) and attached table 5 corresponding to Figure 5 (A) 0
(A) (11) and the timing chart in FIG. 6 are used.

At timing 83 immediately before the first bus cycle T=1, the physical address generator [102] holds the address 0ff030001H of the transfer destination of this operand data.

The address discrimination circuit 111 discriminates the area of this address, and uses the address area information 113 to register the boat width holding register 1.
I'll let you know on 12. The vote width holding register 112 holds T=
At the timing of SO 1, the vote width information 121 of 2 bytes is output. Physical address generation device 102
outputs a physical address onto the address bus 104 at the SO timing of T=1. On the other hand, the instruction decoder 103
Since the initial value LO of the operand data length from LO indicates 2 bytes, the transfer data length holding device 137 stores the number of transfer data bytes DL(1)=LO=2 as the transfer data length information 1.
43 and is output at the SO timing.

Byte selection control unit [138] has a boat width of 2 bytes, a transfer data length of 2 bytes, and the lower 2 bits A of the physical address.
Since x and Ao are 0.1, BEI of the byte selection signal 152 is set to active level 1 and output from the timing of SO according to the relationship shown in Attached Table 2. The number of bytes AB(1) of the active data bus at this time is 1, and the byte selection control device 138 outputs this as active byte number information 123 at timing 81.

On the other hand, the shift control device 161 outputs the number of shift bytes S B (1)=0 as the shift control signal 142 at the beginning of the bus cycle with T=1. In addition, the data block arrangement control device 131 controls the physical address's lower two bits AI and AO (01 and 1), the number of transfer data bytes DL (
1) = 2, so the correspondence between DPi and BFj shown in the attached table, that is, DPO and BFQ, DPI and B FQ%D
P2 and BFl.

Control signal 14 corresponds to connecting DP3 and BFO.
1 is used to instruct the multi-brefsor 133. Also, since the byte selection signal 1520BEI is active, D
Only PI is connected to the 15th to 8th bits of external data bus 105. As a result, the 15th to 8th bits of the data bus are connected to OLO through DPI and BF'O, as shown in FIG. 5(g). Since the read/write control signal 409 is at a high level and instructs reading, the memory S connected to the %BMI, that is, the 15th to 8th bits of the external data bus 105, is activated at the timing of Sl when the strobe signal becomes active. Read data is output onto the data bus 104 from the memory element connected to the memory device. This data is stored in the OLO block of operand latch 136 through the connections described above. thus,
The lower 1 byte at address 00030001H of the 2-byte data is stored in the lowest byte block of the operand latch 136.

At the end of 1゛=1, the transfer data length holding device 137 calculates the number of bytes of transfer data in the next bus cycle, and calculates the number of bytes of transfer data in the next bus cycle, and calculates the number of bytes of transfer data in the next bus cycle. 1←
Since it is 0, it is decided to enter the second bus cycle related to the transfer of this operand data. At timing 83 of T=1, the shift control device 161 changes the number of shift bytes to S B (2) = 8 B (1) + AB (1) = 0 +
2 = 2 and output as the shift control signal 142. At timing 83 when T=1, the physical address generation device 102 updates the physical address to address 00030002H since AB(1)=l. The updated address is transferred to the address bus 10 at the SO timing of T=2.
Output on 4.

In the second bus cycle T=2, the same operation as in the case of T=1 is performed, as shown in FIG. 5(C).

The upper 1-byte data at address 00030002H of the 2-byte data is OL1 of the operand latch 136.
stored in blocks. This process is the same as in the case of T-1, so the explanation will be omitted. However, the number of active bytes UAB(2)=1.

At the end of T=2, the transfer data length holding device 137 calculates the number of transfer bytes in the next bus cycle, and DL(3)=DL(
2)=AB(2)=1-1=0, so the end of the transfer bus cycle related to this operand data is determined. At this point, operand latch 136 has its lower two
Byte data block OLI, (00030 to JLO
The 16-bit data in 001H is stored.

The shift control device 161 at timing 83 of T=2,
The number of shift bytes in the bus cycle for next operand transfer is S.
Update n(1)=Q. Physical address generator k1
02 holds the address of the next operand data at timing 83. In this way, the path width control device & of this embodiment completes the operand data read operation.

In addition, operations can be easily inferred when the operand data length, the address of the transfer partner, the data bus port width of the transfer partner, reading, and writing are different.

〔Effect of the invention〕

As explained above, the present invention provides the address determination means and the port width holding means, thereby eliminating the need for the interpretation of the port width response signal and data block rearrangement, which were required in the conventional bus width control device. One clock can be removed. Therefore, there is no need to specially extend one pass cycle for path width control, and the performance of instruction execution can be improved.

In addition, since the port width information is held internally, the active data bus selection signal can be generated at the beginning of the bus cycle, and unlike conventional bus width control devices, a complex external decoding circuit is not required. I don't. Therefore, a microcomputer system can be configured with a small number of parts, which is very effective in improving implementation efficiency and reliability. Nowadays, high-performance, highly functional, long-length computers are being used in a variety of systems, the bus of the present invention allows flexible systems to be built with a small number of parts without sacrificing performance. The practical value of width control devices is enormous.

Attached table 1 Attached table 2 Attached table 3 Attachment 5 (5) Attachment 5@

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the application of the embodiment, and FIG. 3 (c)
(c) is a block correspondence diagram for showing the operation of one embodiment;
FIG. 4 is a timing chart diagram of one embodiment, FIG. 5 (C) [phase] is a corresponding block diagram showing another operation of one embodiment, and FIG. FIG. 7 is a block diagram of a conventional example, FIG. 8 is a block diagram showing application of the conventional example, and FIG. 9 is a timing chart of the conventional example. 102...Physical address update means, 111...
... Address discrimination means, 112 ... Data no (sport: width information holding means, 137 ... Transfer data length holding means tR1138 ... Data nok sport selection means, X... ...Data arrangement control means. Agent Susumu Uchihara, patent attorney, 8 Iku (A no 3rd Iku Hassun Iku, ni/-11111-8--11111-- -Yo T$2 (A) Go to Figure 85 Susaiku J 56 Sf S2 53 SOS (S2 S3
riD Tsuku Bamboo Diagram (Sakaki IlU) Saitchi 9 Diagram ('L 釆I Row)

Claims (1)

[Claims] A data bus port width information holding means divides the address space into a plurality of areas and holds data bus port width information for each area, and determines in which area of the address space a physical address related to data to be transferred exists. address determination means; transfer data length holding means for holding the length of data to be transferred; data bus port selection means for selecting a data bus port to be used for data transfer; The data bus port selection means has a data arrangement control means that corresponds to a bus port, and a physical address update means that updates a physical address by the address corresponding to the transferred data, and the data bus port selection means selects the physical address of the transfer destination and the length of the data. A bus width control device that selects a data bus port to be used based on the width of the bus.