JPS62230183A - Synchronizing signal reproducing circuit - Google Patents

Abstract

PURPOSE:To prevent the influence to be given on a burst signal by reproducing synchronizing signals uniforming the tip level of synchronizing signal of descramble signals with scramble signals synchronous offset processed to horizontal synchronizing signals in decoder side. CONSTITUTION:A pulse indicating pedestal period out of offset processed horizontal synchronizing signals is applied from the first controlling circuit 40 to a transistor Tr1, and output signals from the emitter side of a Tr4 having slicing function to horizontal synchronizing signals of descrambled video signals are applied to sample hold capacitors C1, C2 through analog gates A1, A2. The difference of voltage of these capacitors C1, C2 is detected by an operational amplifier 70, and applied to the base of Tr2, and feedback operation is made to make the pedestal level of video signals supplied to Tr5 a fixed level, and the pedestal level ofdescrambled video signals is kept at a fixed level.

Description

[Detailed Description of the Invention] (Technical Field of the Invention) The present invention relates to a synchronization signal regeneration circuit, and in particular, even if the synchronization signal tip level (sync tip level) is set to a predetermined constant level, it does not affect the burst signal. The present invention relates to a synchronization signal reproducing circuit capable of reproducing a synchronization signal without image deterioration.

(Technical Background of the Invention and Problems thereof) Generally, in paid broadcasting on CATV and the like, the transmitted video signal is scrambled to prevent unauthorized viewing. Examples of such scrambling processing for a video signal include suppression of a horizontal synchronizing signal (tank offset) and inversion of the polarity of a video signal. From the viewpoint of security against eavesdropping, it is desirable to randomize the timing of sync offset in the video scrambling by suppressing the horizontal synchronization signal.

The video signal that has been scrambled using a zinc offset on the encoder side is descrambled on the decoder side by restoring the offset-processed horizontal synchronization signal. In this case, even though the pedestal levels of the restored video signals are aligned, the leading edge levels of the horizontal synchronization signals are not aligned. This is mainly due to distortion in the transmission system between the encoder side and the decoder side, nonlinear distortion of the amplifiers on the encoder side and the decoder side, and the like.

For example, if a normal scrambled signal resulting from sync offset processing is a signal as shown in Fig. M5 (a), if there is the above distortion, the signal waveform will be as shown in Fig. Inconsistency occurs in the leading edge level of the horizontal synchronization signal. That is, in the same figure, the levels shown by people are uneven. FIG. 6 shows a signal obtained by descrambling the scrambled signal in which the leading edge levels of the horizontal synchronizing signal are uneven. As can be seen from the figure, a voltage level difference of signal level B is generated between the synchronization signals even if the signal has been subjected to discra/pull processing.

The descrambled video signal shown in FIG. 1 above is transmitted to a television receiver via an RF modulator. In this case, when performing synchronization separation in a television receiver, if the leading edge levels of the descrambled video signal are uneven, this may induce malfunction of a synchronization separation circuit having a time constant circuit, for example. For this reason, even though descramble processing has been performed, the synchronization is disturbed and a normal reproduced image cannot be obtained.

In addition, when the above-mentioned F modulator is of a type that clamps the leading edge level of the synchronizing signal to prevent overmodulation, an offset voltage level occurs in the DC voltage of the video signal, which is transmitted to the television receiver. When played back, a so-called Venetian blind in which the C brightness differs depending on the scanning line appears on the playback screen.

As described above, if the video signal pedestal level and the leading edge level of the synchronization signal cannot be made equal to each other on the decoder side with respect to the scrambled video signal, the descrambled reproduced image will deteriorate.

Furthermore, on the decoder side, depending on the time constant of the sync separation circuit, as shown in FIG. 79, if the sync signal width is inappropriate (in FIG. ), the burst signal is distorted (Figure 7 (C)) 6 [Summary of the Invention] In the invention, the sync offset is applied to the video scramble signal which has been sync offset processed to the horizontal synchronizing signal. Horizontal synchronizing signal leading edge level control means for level shifting at processing timing is provided on the output side of the video amplification transistor to perform descrambling.

Further, a buffer transistor is provided on the output side of the video transistor, and the input level of this buffer transistor is forcibly shifted to a predetermined level during the period of the horizontal synchronization signal. This restores the horizontal synchronization signal of the video signal that has been subjected to tank offset processing.

[Purpose of the invention]

The present invention is a slight improvement on the above point, and is based on the following: At least a scrambled signal that has been subjected to synchronization offset processing with respect to a horizontal synchronization signal is processed by aligning the leading level of the synchronization signal of the descrambled signal on the decoder side to generate a synchronization signal. It is an object of the present invention to provide a synchronization signal reproducing circuit which reproduces the synchronization signal and prevents the influence on the burst signal by setting the pulse width of the reproduction synchronization signal to an appropriate value.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment in which a synchronization signal reproducing circuit according to the present invention is applied to a decoder side of a video scrambling system that randomly performs sync offset processing on a synchronization signal.

In the figure, a signal (FIG. 2(a)) obtained by randomly processing the horizontal synchronizing signal with sync offset is applied to the input terminal IN. The offset data for which horizontal synchronization signal is used for sync offset is the vertical blanking interval (VBI)
However, in order to increase confidentiality, encryption processing is performed as necessary before transmission.

The data superimposed on the VBI in the scrambled image signal applied to the input terminal IN is separated by a data extraction circuit 10, and the vertical synchronization signal is separated by a vertical synchronization separation circuit 20. A normal horizontal synchronization signal that has not been subjected to sync offset processing is intermittently extracted by a normal horizontal synchronization signal separation circuit 30. Then, the data separated by the data extraction circuit 10 generates a timing pulse for sync offset processing by the first control circuit 40 (FIG. 2 Φ)). This timing pulse is
This is a signal indicating whether or not the horizontal synchronizing signal C in the scramble signal shown in ) is subjected to offset processing, and is applied to the terminal T. The timing pulse pulse for sync offset processing applied to this terminal T1 is supplied to the pace side of the transistor Tr1, and this transistor Tr,
turns on at the timing of the above pulse. In synchronization with the on/off of the transistor frl, a transistor Tr,
The conduction of the transistor Tr and the transistor Tr contribute to aligning the pedestal level of the offset horizontal synchronizing signal.

That is, from the first control circuit 40, the pedestal period tf pulse of the offset-processed horizontal synchronization signal is applied to the transistor Tr. The output signal from the emitter side of the transistor Tr, which exhibits a slicing function for the horizontal synchronizing signal of the descrambled video signal, is applied to the sample and hold capacitors C1, C, via analog gates At, At. In this case, a pulse indicating the pedestal period of the offset-processed video signal and a pulse indicating the pedestal period of the normal signal are applied from the second control circuit 60 to each of the analog games) At+A*. Therefore, each of the sample and hold capacitors Ct and Ct is at the pedestal level of the offset-processed video signal.

The pedestal level of the normal video signal is sampled and held. The difference between the terminal voltages of these capacitors Ct=Ct is detected by the operational amplifier 70, and this operational amplifier 7
0 output 6c, the transistor Tr.

A feedback operation is performed to keep the pedestal level of the video signal supplied to the transistor Tr at a constant level. This feedback operation maintains the pedestal period of the descrambled video signal at a constant level.

As mentioned above, the pedestal level of the descrambled signal is made equal by the above-mentioned coral action, but
It is also necessary to align the leading edge levels of the descramble signals.

In order to align the leading edge levels of the synchronization signals of the descrambled video signals, the synchronization signals of the descrambled video signals are once expanded and then sliced at a predetermined level. ) A horizontal synchronization signal is applied to the base of the transistor Tr from the first control circuit 40 via the terminal T, and expands the synchronization signal portion of the descrambled video signal. That is, the sync signal level is made conductive at the timing of the horizontal sync signal of the above transistors Tr and t for the horizontal sync signal of all C of the descrambled video signal shown in tvc3 (a) ((b) of the same figure. The synchronization signal part is expanded as shown in FIG. The slice level is controlled by the variable resistor vRt connected to the pace side of the transistor Tr (determined by the emitter potential of the transistor Tr according to ζ).

In this case, this is performed only when performing a disk 2 sample operation on a scrambled signal, but if the transmitted signal is not a scrambled signal, the synchronizing signal expansion and slicing operations are stopped.

This control is performed by the terminal T of the second control circuit 60.

This is done using an identification signal that indicates whether or not the transmitted signal generated at the time is a scrambled signal.・When the identification signal indicates that the C transmission signal is not a scrambled signal, all of the transistors Tr, Tt°6 are set to a position, and the C synchronization signal expansion operation and slicing operation are performed. Both operations are stopped.

Although raising the leading edge level of the descrambled video signal is essential for reproducing the synchronization signal of the descrambled signal, it is desirable that the synchronization signal expansion operation be stopped during the vertical synchronization signal period. This is caused by the delay in the time constant of the horizontal synchronization separation circuit and the switching time of the transistors, resulting in a delay in the switching of the transistor Tr, which causes a sag in the time corresponding to the cutting pulse interval, and the pedestal This is because it affects the feedback operation that keeps the level constant.

Further, the switching time delay has a negative effect on the burst signal as described above.

The transistor 111r deals with these nine problems.

, and this transistor Tr is a capacitor co.

From the time constant Vζ determined by the resistor, a pulse with a delayed fall (Fig. 4(b)) is generated as shown in Fig. 4(C) with respect to the horizontal synchronizing signal part of the ideal video signal shown in Fig. 4(a). Convert the pulse width to the indicated pulse width. Therefore, influence on the burst signal is prevented.

The conduction of the transistor 'I'r is controlled by a vertical synchronizing pulse generated by the first control circuit 40 in addition to the time constant circuit constituted by the above-mentioned CG+C0.

By controlling the conduction of the transistor Illr in response to the vertical synchronizing pulse in this manner, the feedback operation for making the pebbletal level constant can be made constant.

〔Effect of the invention〕

As described above, the synchronization signal reproducing circuit according to the present invention does not affect the descramble signal or the C burst signal, and also does not impair the feedback operation that keeps the pebble level constant. It is capable of reproducing synchronization signals.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a synchronization signal reproducing circuit according to the present invention, and FIGS. 2, 3, and 4 are waveform diagrams for explaining the operation of FIG. 1. FIG. 5, FIG. 6, and FIG. 7 are waveform diagrams for explaining conventional synchronization signal reproducing circuits. Agent Patent Attorney Yudo Noriyuki Chika Yukio Yuyama Figure 4 Figure 6 Figure 70

Claims (1)

[Claims] A video amplification transistor whose input is a video scramble signal in which a horizontal synchronization signal portion specified by random data is given a level deviation by a predetermined level, and a buffer transistor whose input is the output of this video amplification transistor. a horizontal synchronizing pulse generating means for generating a horizontal synchronizing pulse according to the random data; and conduction in response to the output pulse of the horizontal pulse generating means to generate a level shift change corresponding to the bias level in the video scramble signal. horizontal synchronizing signal leading edge level control means for expanding the horizontal synchronizing signal by applying it to the horizontal synchronizing signal in the buffer transistor; 1. A horizontal synchronizing signal reproducing circuit characterized in that: