JPS62224176A - Synchronizing signal recovery circuit - Google Patents

Abstract

PURPOSE:To recover a horizontal synchronizing signal whose tip levels are arranged to a uniform level stably by slicing the horizontal synchronizing signal expanded once at a prescribed DC level. CONSTITUTION:A video scramble signal is inputted to a terminal IN and a synchronizing separator circuit 10 separates a horizontal and a vertical synchronizing signal. A data superimposed during the vertical blanking period by a data extracting circuit 11 is fed to a data recovery circuit 9 to generate a timing pulse for offset processing and polarity inversion processing, a video inversion circuit 1 restores the polarity of the video signal and a synchronizing offset circuit 3 outputs a signal whose offset level is recovered. The horizontal synchronizing signal expanded by the synchronizing offset circuit 3 and a synchronizing signal expansion circuit 5 is sliced by a slice circuit 6 by using the tip level of a vertical synchronizing signal sampled by a sample holding circuit 7, and a descramble video signal whose pedestal level and tip level are arranged to a prescribed value is obtained at the output terminal OUT of an output circuit 12 to recover the horizontal synchronizing signal.

Description

[Detailed Description of the Invention] (Technical Field of the Invention) The present invention relates to a synchronization signal reproducing circuit, and in particular, to a horizontal synchronization signal, a DC level is biased according to random data, and a scrambled video scramble signal is descrambled. The present invention relates to a synchronization signal reproducing circuit suitable for.

(Technical Background of the Invention and Problems thereof) Generally, in paid broadcasting on CATV and the like, scrambling processing is performed on the paid broadcasting signal in order to prevent unauthorized viewing. Scrambling processing for such a video signal includes, for example, suppression of a horizontal synchronizing signal, polarity inversion processing of a video signal, and the like. These scrambling processes for video signals are usually performed at random timing from the viewpoint of security against unauthorized viewing. Furthermore, from a security perspective, it is desirable to use multiple scrambling processes in combination without relying on a single scrambling process.

Video scrambling by polarity reversal processing of video signals inverts the video (H number) with respect to a predetermined quasi-DC level during the picture period, and inverts the brightness.

Scrambling is performed based on color shift.

In addition, image scrambling (hereinafter referred to as sync offset), which is performed by performing offset processing or compression processing on the horizontal synchronization signal and making the synchronization state unstable, causes skew distortion in the raw image. Video scrambling can be done with a simple circuit.

In either of these polarity reversal processing and sync offset methods, in order to increase secrecy, the timing of the scrambling processing must be performed at random timing according to random data. This also applies when both scrambling methods are used together.

The control data for randomly performing the scrambling process in this way is normally provided during the vertical retrace interval (VBI).

Superimpose. The control data is, for example, the initial value of a 1M sequence random number code generator, and the decoder side detects the timing of scrambling processing performed on the encoder side using this control data.

When decoding a video signal in which the above control data is superimposed on VBI and scrambled by polarity inversion processing and sync offset processing, the inversion reference DC level of the above polarity inversion processing and the pedestal of the horizontal synchronization signal subjected to sync offset processing are used. The problem is how to play the levels.

If the inversion reference level for descrambling the polarity-inverted video scramble signal is not set correctly on the decoding side, the brightness level of the descramble signal will fluctuate, causing distortion in the reproduced image.

On the other hand, if the pedestal level is not correctly reproduced on the decoder side for the scrambled signal subjected to sync offset processing, this also causes flicker to occur in the reproduced image.

In this way, in both scrambling systems that use both polarity reversal processing and sync offset processing, and scrambling systems that only perform either one of the scrambling processes, if a predetermined DC level is not reproduced on the decoder side, a descrambled image will result. Flicker occurs and the reproduced images of paid broadcasting are impaired.

Further, the descrambled video signal is modulated with a carrier of a predetermined channel frequency via a F modulator and then transmitted to a television receiver. In this case, 几F
When the modulator is of a type that clamps the leading edge level of the horizontal synchronizing signal to prevent overvariation M, if the leading level and pedestal level of the horizontal synchronizing signal of the descrambled signal are uneven, the pattern (8 This induces an offset constant pressure in the DC level of the signal, which results in further aggravation of flicker in the descrambled image.

As mentioned above, on the decoder side, it is necessary to reliably perform DC reproduction of the horizontal synchronizing signal leading edge level and pedestal level.

(Object of the Invention) The present invention has been made in view of the above points, and provides a signal reproducing circuit suitable for reproducing a horizontal synchronization signal from a scrambled video signal by sync offset processing, polarity inversion processing, etc. The purpose is to

(Summary of the Invention) In the present invention, when an input video signal has been subjected to synchronization offset processing, for example, the horizontal synchronization signal is expanded once at the timing of the horizontal synchronization signal, and then sliced at a reference DC level. By using the leading edge level of the horizontal synchronizing signal, which is relatively less susceptible to noise, as the reference DC level, it is possible to make the horizontal synchronizing signal leading edge level after the slice processing a stable level.

As a result, a horizontal synchronization signal with a stable DC level is reproduced.

(Practice of the Invention) Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a synchronization signal expansion circuit according to the present invention.

FIG. 6 is a circuit diagram showing an example in which a video scramble signal using both tank offset processing and polarity inversion processing is applied to descrambling.

Sink offset processing according to random data.

The video scramble signal subjected to polarity inversion processing is applied to the video input terminal IN. The scrambled video signal applied to the video input terminal IN is applied to the video inversion circuit 1, and is also applied to the sync separation circuit 2. and data extraction time 'P#
Added to r3.

The synchronization separation circuit 2 separates a horizontal synchronization signal (horizontal synchronization signal without sync offset) and a vertical synchronization signal, and the data extraction circuit 3 separates data superimposed on VBI.

The data extracted by the data extracting circuit 3 is applied to a data reproducing circuit 4, which generates timing pulses such as offset processing timing and polarity inversion processing timing. The inversion pulse indicating the timing of the polarity inversion process obtained by the data extraction circuit 3 is descrambled for the polarity inversion process by switching and controlling the video inversion circuit 1 to invert the polarity of the scrambled video signal. will be carried out. Due to this.

At the output of the video inverting circuit 1, a video signal with restored polarity is obtained.

The video No. 1g whose polarity has been restored is applied to the synchronous offset circuit 5, and the data reproduction circuit 4 outputs a signal whose offset level has been restored according to the timing of the offset data to the synchronous offset circuit 5. be done.

The reference DC level in each of the polarity inversion process and inversion process is set by the inversion level detection circuit 6 and the offset DC level regeneration circuit 7, respectively. The synchronous offset circuit 5 works together with a synchronous signal expansion circuit 8 to perform a synchronous signal expansion operation. and the expanded horizontal sync signal.

A descrambled video image is sliced by the slice circuit 10 based on the reference level in VBI sampled by the sample hold circuit 9, and output to the output terminal OUT of the output circuit 11 with the pedestal level, level, and tip level all aligned to a constant value. Get a signal.

In this way, the synchronization signal is reproduced from the descrambled sleep image signal, and the operation of aligning the tip level and pedestal level of the horizontal synchronization signal to a constant level, and also aligning the polarity inversion level to a constant level. For every,
This will be explained next with reference to waveform diagrams.

Control operation of polarity inversion level> The scrambled video signal applied to the input terminal IN of the video inversion circuit 1 undergoes a polarity restoration operation by a double balanced differential amplifier constituted by transistors Q1 to Q6. The scrambled video signal (FIG. 2(a)) is applied to the base of the transistor Q of the video inversion circuit 1, and is detected by the inversion level detection circuit 6 at the base of the transistor Q forming a differential pair therewith. An inverted level detection signal is added. Here, an in-phase output is obtained from the emitter follower type transistor Q of the image inversion circuit 1, and an in-phase output is obtained from the emitter of the transistor Q. That is, an unscrambled signal is derived from the transistor Qa by polarity inversion processing, and a video signal whose polarity is restored by inverting the polarity of the scrambled video 1g by polarity inversion is derived from the transistor Q.

A resistor R1° and a resistor 11 are connected between the emitters of the transistors Q, , Q, and the connection point thereof is connected to the positive phase input terminal of the operational amplifier Q of the inversion level detection circuit 6. Further, the emitter of the transistor Q is connected to each of the analog gates Q+o + Q+t. , Qll is connected to an offset pedestal pulse (see FIG.
b) ), the normal pedestal pulse (second
Continuity control is performed according to the diagram (C).

Therefore, the capacitors C, , C of the inversion level detection circuit 6.

The 4-7 cent pedestal level and the normal pedestal level are each sampled.

Here, in the scramble processing for the video signal on the encoder side, the polarity of the video signal is inverted at a level of 50 IRE for the polarity inversion processing, as shown in Figure 3 (a), and for the sync offset processing, the polarity of the video signal is normally inverted. Pedestal level of horizontal synchronization signal (OIRE) of 80 I
Processing to offset to the RE level is performed.

The inversion level jetting circuit 6 generates an inversion level for restoring the polarity of the scrambled video signal whose polarity has been inverted using the pedestal level subjected to the irj offset processing.
Detected by

That is, the transistor Q of the video inversion circuit 1 has a normal pedestal level (OIRE), and the emitter of the transistor Q has an offset pedestal level (80
A signal at the level of IRE) is derived and the resistance ratio, . and R1
A level signal of 50I⇠E is obtained at the connection point □.

However, the above resistance ratio. and 几1. The ratio of resistance values is 5:3. And the above resistance ratio. 5Q of J74 points of Toban, l
The signal of IIltE is the positive phase of the operational amplifier Q -1゛1
°d is applied to the terminal. On the other hand, there is also a variable resistor at the negative phase input terminal of the operational amplifier Q9. The sliding terminal is connected. This variable resistance ratio. analog goo) Qlo -Qt
t is connected.

These analogues) Q+o -Qll are the offset pedestal pulses (Fig. 2(b), Fig. 3(b)), respectively.
), the conduction is controlled according to the normal pedestal pulse (Fig. 2(c), Fig. 2a(c)), and the video signal on the emitter side of the transistor Q is applied to each of the capacitors C, ,C, The pedestal level inside is sampled.

For this reason, the analog gate Ql. The average level of the offset pedestal level (80I) is detected at the capacitor C1, and the normal pedestal level (OIRE) is detected at the analog gate Q11 and the capacitor C6.

Also, the variable resistor R, is the above 80IRFi and oIR
The level of E is divided by resistors so that a level signal of (50 kE) is obtained at the sliding terminal. Variable resistance ratio, thus obtained. The DC level signal obtained on the slider (5
0 engineering E) is applied to the negative phase input terminal of the upper gt operational amplifier Q.

The operational amplifier Q0 has an inversion level (50IRE) detected instantaneously and successively, and an inversion level (50IRE) detected on average according to the data reproduced by the data reproduction circuit 4.
) and the error 1 due to this detection result.
The d voltage is applied to the base of the transistor Q6 of the image inverting circuit 1. The above error voltage is fed back to the video inverting circuit, and even if the DC potential is biased due to transmission distortion in the transmitted scrambled video signal, the video inverting level is corrected by the feedback action from the offset pedestal level and normal pedestal level. This reduces the occurrence of flicker in the descrambled image. In this case, decoding control for sync offset processing, inversion of the picture,
The non-inversion control is performed by controlling the inversion/non-inversion control pulses (FIG. 2(d), 3
(Fig. 2(d)), offset control pulse (Fig. 2(e))
, FIG. 3(e)).

Offset DC playback operation> The descrambled video signal has its pedesmel level,
If control is not performed so that the leading edge levels of the synchronizing signals are each at a predetermined constant level, flicker will occur in the reproduced image due to fluctuations in the DC potential. For this reason, it is necessary to perform appropriate DC reproduction for both the pedestal level and the leading edge level of the horizontal synchronizing signal.

First, regarding the offset DC regeneration operation, the emitter follower transistor Q1. of the output circuit 11. Of the emitter outputs, the pedestal level is sampled and held by the offset DC reproduction circuit 7. A capacitor C6 connected to the analog gate of the offset DC regeneration circuit 7, a capacitor C connected to the analog gate
1, the offset pedestal level of the descrambled video signal (ideally 0 process E) and the pedestal level of the normal video signal are sampled. At this time, the analog game) QB and Qt4 are the offset pedestal pulse (Fig. i2 (t))) and the normal pedestal pulse (the second
Figure (C)).

Descrambled video signal with offset processing! (7)
The pedestal level signal is applied to the negative phase input terminal of the operational amplifier Q, while the pedestal level of the normal signal is applied to the positive phase input terminal, and the level difference between the two is detected by the upper operational amplifier Q. The pedestal level differential voltage output by the operational amplifier Qtt is added to the pace of the transistor Qtm of the synchronous offset circuit 5.

A transistor Q14 is connected in series to this transistor Qss.
are connected, and the transistors Q1. turns on in response to the offset pulse (FIG. 3(e)). Therefore, the synchronous offset circuit 5
Output DC level of video amplification transistor 80I) IE
A feedback operation is performed in which the pedestal level of the offset horizontal synchronizing signal is made equal to the pedestal level of the normal signal by shifting by a level corresponding to .

By the above feedback operation, the pedestal level of the descrambled video signal is made equal to a predetermined constant level, but it is also necessary to make the leading edge level of the horizontal synchronizing signal equal.

<Horizontal synchronization signal leading edge level control operation> As mentioned above, if the leading edge levels of the horizontal synchronization signals are not aligned, when a descrambled video signal is received by a television receiver, the time constant circuit will inducing malfunction in the operation of the horizontal synchronization separation circuit. Further, the descrambled video signal is typically transmitted to a television receiver after being modulated at a predetermined channel frequency by a F modulation circuit. When the horizontal synchronizing signal of the descrambled video signal is clamped to prevent overmodulation using the F modulator described above, if the leading edge levels of the horizontal synchronizing signal of the descrambled video (i) are uneven, the two The operation causes a DC offset in the picture signal, causing flicker in the reproduced picture.

Furthermore, the leading edge level of the horizontal synchronizing signal of a scrambled or descrambled video signal is easily affected by transmission distortion, non-linear distortion of amplification, or noise, and is essentially prone to level fluctuations.

In this embodiment, the horizontal synchronization signal leading edge level of the descrambled video signal is aligned.

VBI in scrambled video signal arriving at reference DC level
Use the DC level at .

In other words, the horizontal synchronization signal part is expanded once, and then the reference level in the VBI is used to generate the expanded synchronization signal (g
By slicing the signal, the leading edge level of the descrambled horizontal synchronizing signal is made uniform.

The horizontal synchronizing signal expansion operation described above is performed by conducting conduction control l of the transistor Q1° constituting the synchronizing signal expansion circuit 8 provided on the pace side of the transistor Qss of the output circuit 11. That is, a pulse during the horizontal synchronization signal period is applied to the base of the transistor Q111, and the transistor Q1. expands all horizontal synchronization signals (second
Figure (f)).

On the other hand, the sample and hold circuit 9 samples and holds the vertical synchronization signal leading edge level at the timing of the rising edge of the cut pulse in the VBI of the descrambled video signal (FIG. 2(f)). This vertical synchronization signal period is relatively unaffected by noise.

Suitable for detecting stable reference DC level. The reference DC level obtained by the sample and hold circuit 9 is applied to the base side of the transistors Q and 6 constituting the synchronous slice circuit 10, and is a slice level for slicing the horizontal synchronous signal expanded by the synchronous signal expansion circuit 8. used as. For this reason, the output circuit 11 receives a horizontal synchronization signal ((0) in FIG. 2) whose tip level is aligned to a uniform level by the synchronization slice circuit 10. is 1
Although it generates various timing pulses.

Basically, the normal horizontal synchronization signal 1 of the transmitted scrambled video signal itself. A desired timing pulse is generated by the vertical synchronization signal and data superimposed on VBI.

After the scrambled video signal is applied to the input terminal IN,
Synchronous separation circuit 2. It is applied to the data extraction circuit 3.

In the synchronization separation circuit 2, the normal horizontal synchronization signal from the input video scramble signal is transferred to the transistor Qzs +
Q*a + time constant circuit C,,,R1! , (width in Figure 2), excluding the part indicated by the arrow). The sync signal corresponding to the offset processed horizontal sync signal is:

A horizontal synchronization reproducing circuit 12 provided on the output terminal OUT side of the output circuit 11 satisfies the horizontal synchronization signal separated from the descrambled video signal. and,
Corresponding to the normal horizontal synchronization signal and the offset synchronization signal obtained by the synchronization separation circuit 2, both the horizontal synchronization signals reproduced by the horizontal synchronization regeneration circuit 12 are applied to the OR circuit Qn, and all the horizontal synchronization signals are reproduced (the Figure 2 (h)).

By doing this, the normal horizontal synchronization signal becomes noise l
Even if it cannot be extracted from this.

The missing portion is filled by the reproduced horizontal synchronization signal.

In addition, the offset pedestal pulse (Fig. 2(b))
), /- malpedestal pulse (Fig. 2(C)).

The inversion/non-inversion control pulse (FIG. 2(d)), offset pulse (FIG. 2(e)), etc. are used to convert the data extracted from the VBI by the data extraction circuit 3 into the data reproduction circuit 4.
It can be obtained by decoding with .

In this case, the data reproducing circuit 4 operates as the OR circuit Q!
If the structure has an injection lock type oscillator that oscillates according to the output of The above oscillator is driven.

The oscillator has a predetermined phase due to the flywheel effect.

sustain oscillation at the frequency.

That is, even if data is missing, the oscillator is excited by the normal horizontal synchronizing signal, and the descrambling operation can be ensured.

(Effects of the Invention) As described above, according to the synchronization signal regeneration circuit according to the present invention, the horizontal synchronization signal once expanded is referenced to the stable DC potential in VBI every lζ when reproducing the horizontal synchronization signal. Since the slice is performed at a predetermined DC level, a horizontal synchronizing signal whose leading edge level is stably aligned to a uniform level value is reproduced.

Further, in the synchronization signal reproducing circuit according to the present invention.

Once the vedestal level is adjusted to a predetermined level, the horizontal synchronization signal is expanded and sliced at a predetermined level.The synchronization signal is processed to equalize the levels of the final level, hetestal level, and sync tip level. .

Furthermore, since the level at which the horizontal synchronization signal is sliced is determined according to the feedback operation by sampling and holding the top level of the vertical synchronization signal from the playback signal, the top level of the playback synchronization signal follows the incoming video signal. can be maintained at a stable level.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the synchronization signal reproducing circuit according to the present invention, and FIGS. 2 and 743 are waveform diagrams for explaining the operation of FIG. 1. 2... Vertical synchronization separation circuit. 4...Horizontal synchronization timing pulse generation means. 7...DC regeneration means. 8...Horizontal synchronization signal expansion circuit, 9...Reference DC level setting means. 10...Slice circuit. Qls...buffer amplifier. Agent Patent Attorney Nori Chika Ken Shu Kanshu Yukio Yuyama

Claims (2)

[Claims] (1) Vertical synchronization signal separation means for separating a vertical synchronization signal from an input video signal, reference DC level setting means for extracting the level of the vertical synchronization signal and setting a reference DC level, and the separated vertical synchronization signal horizontal synchronization timing pulse generation means for generating a horizontal synchronization timing pulse by taking at least as an input, and horizontal synchronization for expanding the input video signal at a timing corresponding to the horizontal synchronization pulse generation means and generating an expanded horizontal synchronization signal. a signal expansion circuit, and performs a slicing operation on the output of the horizontal synchronization signal expansion circuit according to the reference DC level determined by the reference DC level setting means to output a horizontal synchronization signal whose tip level is uniformized to a predetermined constant DC level. 1. A synchronous signal reproducing circuit comprising at least a slicing circuit. (2) A video buffer amplifier that performs a buffer operation on an input video signal, a sample hold means that samples and holds the pedestal level on the output side of this video buffer amplifier, and a signal obtained by this sample hold means that is transferred to the video buffer amplifier. DC reproduction means that feeds back to the input side of the amplifier to maintain a pedestal level at a constant level, vertical synchronization signal separation means that separates a vertical synchronization signal from the input video signal, and horizontal synchronization timing pulse using the separated vertical synchronization signal. horizontal synchronization timing pulse generation means for generating a horizontal synchronization timing pulse; a horizontal synchronization signal expansion circuit for expanding the input video signal at a timing corresponding to the horizontal synchronization timing pulse and generating an expanded horizontal synchronization signal; A synchronization signal reproducing circuit comprising at least a slicing circuit for slicing a synchronization signal at a predetermined level, and obtaining a horizontal synchronization signal whose pedestal level and tip level have been processed to a uniform level on the output side of the buffer amplifier.