JPH11103440A - Circuit for preventing vtr recording - Google Patents

Circuit for preventing vtr recording

Info

Publication number
JPH11103440A
JPH11103440A JP9263414A JP26341497A JPH11103440A JP H11103440 A JPH11103440 A JP H11103440A JP 9263414 A JP9263414 A JP 9263414A JP 26341497 A JP26341497 A JP 26341497A JP H11103440 A JPH11103440 A JP H11103440A
Authority
JP
Japan
Prior art keywords
pulse
circuit
signal
recording prevention
vtr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9263414A
Other languages
Japanese (ja)
Inventor
Toshio Imai
俊夫 今井
Masahiro Ito
昌浩 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GOTENBA NIPPON DENKI KK
NEC Corp
Original Assignee
GOTENBA NIPPON DENKI KK
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GOTENBA NIPPON DENKI KK, NEC Corp filed Critical GOTENBA NIPPON DENKI KK
Priority to JP9263414A priority Critical patent/JPH11103440A/en
Publication of JPH11103440A publication Critical patent/JPH11103440A/en
Pending legal-status Critical Current

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  • Television Signal Processing For Recording (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a VTR recording preventing circuit which is easily and inexpensively incorporated into a TV receiver or a TV monitor, etc. SOLUTION: A synchronization separating circuit 1 separates a composite synchronizing signal S2 (vertical and horizontal synchronizing signal after removing a video part) from a TV video signal S1. A delay circuit 2 outputs a pulse S3 which is given prescribed delay within the range of the pulse width of a horizontal synchronizing signal. A pulse generating circuit 3 generates the pulse S4 for preventing video recording, which can be inserted to the inside of the horizontal synchronizing pulse by receiving the pulse S3. A synthesizing circuit 4 inserts the pulse S4 into the whole horizontal synchronizing pulses including the vertical feedback erasion time of the TV video signal S1 and transmits it to VTR as a video recording prevention-processed output TV video signal S5.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はVTR録画防止回路
に関し、特にVTR(ビデオテープレコーダ)によって
録画できないようにテレビ映像信号を処理するVTR録
画防止回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VTR recording prevention circuit, and more particularly to a VTR recording prevention circuit for processing a television video signal so that recording cannot be performed by a VTR (video tape recorder).

【0002】[0002]

【従来の技術】従来は、ビデオテープに記録する映像信
号に対して録画防止処理を行っている。録画防止処理さ
れたビデオテープを一般のVTRで再生したときは、V
TRの同期走査サーボ系に擾乱が発生して録画再生が不
可能になるようにしている。例えば、特開平1−238
287号公報には、製品ビデオテープの無断複製を防止
するVTRが開示されている。これによれば、入力テレ
ビ映像信号の垂直同期信号近傍の複数の水平走査期間
に、振幅が変化する水平同期信号に類似した類似水平同
期信号を挿入すると共に、ほぼ全ての水平同期信号のブ
リーズウェイ区間(水平同期立上がり部分からカラーバ
ースト信号の前までの区間)にほぼ100%IREレベ
ルのパルスを挿入し、ビデオテープに記録している。
2. Description of the Related Art Conventionally, recording prevention processing is performed on a video signal recorded on a video tape. When a videotape that has been subjected to recording prevention processing is played back on a general VTR,
Disturbances occur in the synchronous scanning servo system of the TR so that recording and reproduction become impossible. For example, JP-A-1-238
No. 287 discloses a VTR for preventing unauthorized duplication of a product video tape. According to this, during a plurality of horizontal scanning periods near the vertical synchronizing signal of the input television video signal, a similar horizontal synchronizing signal similar to the horizontal synchronizing signal whose amplitude changes is inserted, and the breathway of almost all the horizontal synchronizing signals is inserted. A pulse of almost 100% IRE level is inserted in a section (a section from a horizontal synchronization rising portion to before a color burst signal) and recorded on a video tape.

【0003】[0003]

【発明が解決しようとする課題】上述した従来例では、
ビデオテープ再生時にVTRの同期走査サーボ系に擾乱
を発生させるために、垂直同期信号の近傍に振幅が変化
する類似水平同期信号を挿入したり、水平同期信号のブ
リーズウェイ区間に100%IREレベルのパルスを挿
入したテレビ映像信号を生成してビデオテープに記録し
ている。このため、回路構成が複雑化し、高価になると
いう問題点を有している。
In the above-mentioned conventional example,
In order to generate a disturbance in the synchronous scanning servo system of the VTR during video tape reproduction, a similar horizontal synchronizing signal whose amplitude changes near the vertical synchronizing signal is inserted. A television picture signal with a pulse inserted is generated and recorded on a video tape. For this reason, there is a problem that the circuit configuration is complicated and expensive.

【0004】本発明の目的は、VTRに入力するテレビ
映像信号に対して録画防止処理を行うことにより、TV
放送受信機やTV受像機等に簡単かつ安価に組み込むこ
とができ、録画させたくない放送番組のテレビ映像信号
に対しても容易に録画防止処理を行うことができるVT
R録画防止回路を提供することにある。
[0004] It is an object of the present invention to provide a TV video signal input to a VTR by performing a video recording prevention process.
A VT that can be easily and inexpensively incorporated into a broadcast receiver, a TV receiver, or the like, and can easily perform a recording prevention process on a television video signal of a broadcast program that the user does not want to record.
An R recording prevention circuit is provided.

【0005】[0005]

【課題を解決するための手段】本発明のVTR録画防止
回路は、テレビ映像信号の垂直帰線消去期間を含む全て
の水平同期パルス内に、水平同期パルスの幅よりも狭く
且つ映像レベルに達する録画防止用パルスを挿入する。
具体的には、入力テレビ映像信号から垂直,水平同期信
号からなるコンポジット同期信号を分離する同期分離回
路と、この同期分離回路の出力信号に基づき水平同期パ
ルス幅以内の所定の遅延を与える遅延回路と、この遅延
回路の出力信号に基づき水平同期パルス幅よりも狭い録
画防止用のパルスを生成するパルス生成回路と、前記録
画防止用パルスを前記入力テレビ映像信号の垂直帰線消
去期間を含む全ての水平同期パルス内に挿入する合成回
路とを有する。
SUMMARY OF THE INVENTION A VTR recording prevention circuit of the present invention has a width smaller than the width of a horizontal synchronization pulse and reaches a video level in all horizontal synchronization pulses including a vertical blanking period of a television video signal. Insert a recording prevention pulse.
More specifically, a sync separation circuit for separating a composite sync signal composed of a vertical and horizontal sync signal from an input television video signal, and a delay circuit for providing a predetermined delay within a horizontal sync pulse width based on an output signal of the sync separation circuit A pulse generation circuit for generating a recording prevention pulse narrower than a horizontal synchronization pulse width based on an output signal of the delay circuit; and a method for generating the recording prevention pulse including a vertical blanking period of the input television video signal. And a synthesizing circuit to be inserted into the horizontal synchronizing pulse.

【0006】[0006]

【発明の実施の形態】次に本発明について図面を参照し
て説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0007】図1は本発明の一実施形態を示すブロック
図である。テレビ映像信号S1から垂直,水平同期信号
からなるコンポジット同期信号S2を分離する同期分離
回路1と、水平同期パルス幅以内の所定の遅延を与える
遅延回路2と、水平同期パルス幅よりも狭い録画防止用
のパルスS4を生成するパルス生成回路3と、録画防止
用パルスS4をテレビ映像信号S1の垂直帰線消去期間
を含む全ての水平同期パルス内に挿入する合成回路4と
を有している。
FIG. 1 is a block diagram showing an embodiment of the present invention. A sync separation circuit 1 for separating a composite sync signal S2 composed of a vertical and horizontal sync signal from the television video signal S1, a delay circuit 2 for providing a predetermined delay within the horizontal sync pulse width, and recording prevention narrower than the horizontal sync pulse width And a synthesizing circuit 4 for inserting the recording prevention pulse S4 into all the horizontal synchronization pulses including the vertical blanking period of the television video signal S1.

【0008】ところで、VTRは、入力するテレビ映像
信号から同期信号を分離して同期検出し、サーボ系を制
御して録画再生を行っている。しかし、VTRの同期検
出は極めて鋭敏であるため、コンポジット同期信号の中
に異質なパルスが混入している場合、一般のTV受像機
やTVモニタでは画面表示に影響の出ない程度であって
も、同期検出エラーが生じてサーボ系に擾乱が発生し、
録画再生が不可能になる。
The VTR separates a synchronization signal from an input television video signal, detects synchronization, and controls a servo system to perform recording and reproduction. However, since the VTR synchronization detection is extremely sensitive, if a different type of pulse is mixed in the composite synchronization signal, even a general TV receiver or TV monitor will not affect the screen display. , A synchronization detection error occurs and disturbance occurs in the servo system,
Recording and playback become impossible.

【0009】本発明は、一般のTV受像機やTVモニタ
では画面表示に何ら支障はないが、VTRに対しては録
画が不可能になる程度に、同期信号に異質なパルスを挿
入することにより、回路構成を簡素化している。
According to the present invention, a general TV receiver or a TV monitor does not hinder the screen display at all, but inserts an extraordinary pulse into the synchronizing signal to the extent that recording cannot be performed on a VTR. The circuit configuration is simplified.

【0010】同期分離回路1は、図2(a)に示すよう
なコンポジット同期信号S2(映像部分を除いた垂直,
水平同期信号)を分離する。遅延回路2は、図2(b)
に示すように、水平同期信号のパルス幅以内の所定の遅
延幅を有するパルスS3を出力する。パルス生成回路3
は、遅延回路2からのパルスS3を受け、図2(c)に
示すように、水平同期パルス内に挿入できる録画防止用
のパルスS4を生成する。合成回路4は、図2(d)に
示すように、パルスS4をテレビ映像信号S1の垂直帰
線消去期間を含む全ての水平同期パルス内に挿入し、録
画防止処理済みの出力テレビ映像信号S5としてVTR
へ送出する。
The sync separation circuit 1 includes a composite sync signal S2 (a vertical sync signal excluding a video portion) as shown in FIG.
Horizontal sync signal). The delay circuit 2 is shown in FIG.
As shown in (1), a pulse S3 having a predetermined delay width within the pulse width of the horizontal synchronization signal is output. Pulse generation circuit 3
Receives the pulse S3 from the delay circuit 2 and generates a recording prevention pulse S4 that can be inserted into the horizontal synchronization pulse as shown in FIG. 2C. As shown in FIG. 2D, the synthesizing circuit 4 inserts the pulse S4 into all the horizontal synchronizing pulses including the vertical blanking period of the television video signal S1, and outputs the recording-prevented output television video signal S5. As VTR
Send to

【0011】このように垂直帰線消去期間を含む全ての
水平同期パルス内にパルスを挿入することにより、擬似
的に垂直同期信号の同期位置を乱したことになる。テレ
ビ映像信号S5をTV受像機やTVモニタに供給した場
合、TV受像機やTVモニタではブロッキング発振回路
を使用した甘い同期検出をしているので何ら支障はな
く、通常の表示画面が得られる。しかし、テレビ映像信
号S5をVTRに供給した場合、同期分離、位相差比較
において、垂直同期部分の挿入パルスによってサーボ同
期系が乱れ、また、水平同期パルス部分に挿入されたパ
ルスによってハーフパルスHキラーが乱れ、ドラム回転
制御系に乱れが生じて正常な動作を維持できなくなるた
め、録画不能となる。
By inserting a pulse in all the horizontal synchronizing pulses including the vertical blanking period, the synchronous position of the vertical synchronizing signal is disturbed in a pseudo manner. When the television image signal S5 is supplied to a TV receiver or a TV monitor, the TV receiver or the TV monitor performs a soft synchronization detection using a blocking oscillation circuit, so that there is no problem and a normal display screen can be obtained. However, when the television video signal S5 is supplied to the VTR, in the synchronization separation and the phase difference comparison, the insertion pulse of the vertical synchronization part disturbs the servo synchronization system, and the pulse inserted in the horizontal synchronization pulse part causes the half pulse H killer. And the drum rotation control system is disturbed, so that normal operation cannot be maintained.

【0012】図3は本発明の一実施例を示す回路図であ
る。
FIG. 3 is a circuit diagram showing an embodiment of the present invention.

【0013】入力テレビ映像信号S1は2つの回路系に
分岐し、一方は、入力バッファアンプ5、クランプ回路
7を介して合成回路4へ供給され、他方は、入力バッフ
ァアンプ6、クランプ回路8を介して同期分離回路1へ
供給される。同期分離回路1から出力されるコンポジッ
ト同期信号S2は、遅延回路2に供給される。
The input television video signal S1 branches into two circuit systems, one of which is supplied to a synthesizing circuit 4 via an input buffer amplifier 5 and a clamp circuit 7, and the other is supplied to an input buffer amplifier 6 and a clamp circuit 8. The signal is supplied to the synchronization separation circuit 1 via the synchronization separation circuit 1. The composite synchronization signal S2 output from the synchronization separation circuit 1 is supplied to the delay circuit 2.

【0014】遅延回路2は単安定マルチバイブレータ2
1からなり、コンポジット同期信号の立下がり(水平同
期パルスの開始点)でトリガをかけ、抵抗22とコンデ
ンサ23とで定まる一定時間幅のパルスS3を出力す
る。パルス生成回路3も単安定マルチバイブレータ31
からなり、パルスS3の立下がりでトリガをかけて、抵
抗32とコンデンサ33とで定まる一定時間幅のパルス
S4を出力する。
The delay circuit 2 is a monostable multivibrator 2
A trigger is applied at the falling edge of the composite synchronization signal (start point of the horizontal synchronization pulse), and a pulse S3 having a fixed time width determined by the resistor 22 and the capacitor 23 is output. The pulse generation circuit 3 is also a monostable multivibrator 31
A trigger is generated at the falling edge of the pulse S3, and a pulse S4 having a fixed time width determined by the resistor 32 and the capacitor 33 is output.

【0015】このパルスS4は合成回路4に供給され、
入力バッファアンプ5およびクランプ回路7を経由して
きた入力テレビ映像信号S1に合成される。ここで、合
成回路4は、パルスS4に応じて動作するスイッチ41
と、所定電圧を設定する可変電圧源42と、出力バッフ
ァアンプ43とを有している。スイッチ41がパルスS
4に応じて入力テレビ映像信号S1と可変電圧源42と
に切り替わることにより、入力テレビ映像信号S1に所
定レベルのパルスが挿入される。このようにすることに
より、パルスS4を入力テレビ映像信号S1に直接合成
するのと同じ処理を行うことができる。
This pulse S4 is supplied to a synthesizing circuit 4.
It is combined with the input television video signal S1 that has passed through the input buffer amplifier 5 and the clamp circuit 7. Here, the synthesizing circuit 4 includes a switch 41 that operates according to the pulse S4.
And a variable voltage source 42 for setting a predetermined voltage, and an output buffer amplifier 43. Switch 41 is pulse S
By switching to the input television video signal S1 and the variable voltage source 42 in response to No. 4, a pulse of a predetermined level is inserted into the input television video signal S1. This makes it possible to perform the same processing as directly combining the pulse S4 with the input television video signal S1.

【0016】図4は本発明のVTR録画防止回路を評価
するために構成した機器接続図である。
FIG. 4 is a device connection diagram configured to evaluate the VTR recording prevention circuit of the present invention.

【0017】信号源11はBSチューナ、CSチューナ
の映像出力信号を使用し、信号源11の映像出力信号を
そのままVTR15に供給した場合と、VTR録画防止
回路13を通して供給した場合とを比較した。また、V
TR録画防止回路13の出力側にTVモニタ14を接続
して表示画面をチェックした。
The signal source 11 uses the video output signals of the BS tuner and the CS tuner, and a comparison is made between a case where the video output signal of the signal source 11 is supplied to the VTR 15 as it is and a case where the video output signal is supplied through the VTR recording prevention circuit 13. Also, V
The display screen was checked by connecting the TV monitor 14 to the output side of the TR recording prevention circuit 13.

【0018】遅延回路2の抵抗22およびパルス生成回
路3の抵抗32並びに可変電圧源42の設定値を調整し
て、挿入パルスの位置、挿入パルスの幅,挿入パルスの
レベルを変化させた。この結果、録画防止効果が最大に
なったのは、挿入パルス位置が同期信号の立下がりエッ
ジから1.3μs程度の所であり、挿入パルス幅が0.
5μs、挿入パルスレベルが100%IREであった。
このとき、VTR15では全く録画不能となり、再生画
像は黒画面となった。しかし、TVモニタ14には何ら
影響は出なかった。
The position of the insertion pulse, the width of the insertion pulse, and the level of the insertion pulse are changed by adjusting the set values of the resistor 22 of the delay circuit 2, the resistor 32 of the pulse generation circuit 3, and the variable voltage source 42. As a result, the recording prevention effect was maximized when the position of the insertion pulse was about 1.3 μs from the falling edge of the synchronization signal, and the insertion pulse width was 0.3 μs.
5 μs, the insertion pulse level was 100% IRE.
At this time, recording was not possible at all in the VTR 15, and the reproduced image was a black screen. However, the TV monitor 14 was not affected at all.

【0019】なお、挿入パルス位置は同期信号の立下が
りエッジから0.2μs以上、挿入パルス幅は0.5μ
s〜1μsであれば有効である。また、従来例にあるブ
リーズウェイ区間に100%IREとなるパルスを加え
た場合、TVモニタ画面上に雑音が発生することがあっ
た。また、水平同期のブリーズウェイ区間だけに100
%IREとなるパルスを加えても、完全に録画不能にす
ることはできなかった。
The position of the insertion pulse is 0.2 μs or more from the falling edge of the synchronization signal, and the insertion pulse width is 0.5 μs.
It is effective if s to 1 μs. In addition, when a pulse of 100% IRE is added to the conventional breatheway section, noise may be generated on the TV monitor screen. Also, 100 only in the horizontal synchronization Breezeway section
Even if a pulse for% IRE was applied, recording could not be completely disabled.

【0020】[0020]

【発明の効果】以上説明したように本発明によれば、V
TRに供給するテレビ映像信号の垂直帰線消去期間を含
む全ての水平同期パルス内に、水平同期パルスの幅より
も狭いパルスを挿入することにより、TV受像機やTV
モニタに何ら支障を与えることなく、VTRによる録画
を不可能にすることができ、簡単かつ安価なVTR録画
防止回路を提供できる。
As described above, according to the present invention, V
By inserting a pulse narrower than the width of the horizontal synchronizing pulse into all the horizontal synchronizing pulses including the vertical blanking period of the television video signal supplied to the TR,
The recording by the VTR can be disabled without any trouble to the monitor, and a simple and inexpensive VTR recording prevention circuit can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】図1に示した各回路の出力信号波形を示す図で
ある。
FIG. 2 is a diagram showing an output signal waveform of each circuit shown in FIG.

【図3】本発明の一実施例を示す回路図である。FIG. 3 is a circuit diagram showing one embodiment of the present invention.

【図4】本発明のVTR録画防止回路を評価するために
構成した機器接続図である。
FIG. 4 is a device connection diagram configured to evaluate the VTR recording prevention circuit of the present invention.

【符号の説明】[Explanation of symbols]

1 同期分離回路 2 遅延回路 3 パルス生成回路 4 合成回路 21,31 単安定マルチバイブレータ 41 スイッチ 42 可変電圧源 S1 テレビ映像信号 S4 録画防止用パルス DESCRIPTION OF SYMBOLS 1 Synchronization separation circuit 2 Delay circuit 3 Pulse generation circuit 4 Synthesis circuit 21, 31 Monostable multivibrator 41 Switch 42 Variable voltage source S1 TV picture signal S4 Recording prevention pulse

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 VTR(ビデオテープレコーダ)によっ
て録画できないようにテレビ映像信号を処理するVTR
録画防止回路であって、前記テレビ映像信号の垂直帰線
消去期間を含む全ての水平同期パルス内に、前記水平同
期パルスの幅よりも狭く且つ映像レベルに達する録画防
止用パルスを挿入する手段を有することを特徴とするV
TR録画防止回路。
1. A VTR for processing a television video signal so that it cannot be recorded by a VTR (video tape recorder).
A recording prevention circuit, comprising: a means for inserting a recording prevention pulse narrower than the width of the horizontal synchronization pulse and reaching a video level in all horizontal synchronization pulses including a vertical blanking period of the television video signal. V characterized by having
TR recording prevention circuit.
【請求項2】 前記録画防止用パルス挿入手段は、入力
テレビ映像信号から垂直,水平同期信号からなるコンポ
ジット同期信号を分離する同期分離回路と、この同期分
離回路の出力信号に基づき水平同期パルス幅以内の所定
の遅延を与える遅延回路と、この遅延回路の出力信号に
基づき水平同期パルス幅よりも狭い録画防止用のパルス
を生成するパルス生成回路と、前記録画防止用パルスを
前記入力テレビ映像信号の垂直帰線消去期間を含む全て
の水平同期パルス内に挿入する合成回路とを有している
ことを特徴とする請求項1記載のVTR録画防止回路。
2. The recording prevention pulse insertion means according to claim 1, wherein said recording separation pulse insertion means separates a composite synchronization signal composed of a vertical and horizontal synchronization signal from an input television video signal, and a horizontal synchronization pulse width based on an output signal of said synchronization separation circuit. A delay circuit for providing a predetermined delay within, a pulse generation circuit for generating a recording prevention pulse narrower than a horizontal synchronization pulse width based on an output signal of the delay circuit, and the input television video signal 2. The VTR recording prevention circuit according to claim 1, further comprising a synthesizing circuit that inserts into all the horizontal synchronization pulses including the vertical blanking period.
【請求項3】 前記合成回路は、前記録画防止用パルス
に応じて動作するスイッチと、所定電圧を出力する可変
電圧源とを有し、前記スイッチが、前記録画防止用パル
スに応じて前記入力テレビ映像信号および前記所定電圧
のいずれかに切り替わることを特徴とする請求項2記載
のVTR録画防止回路。
3. The synthesizing circuit includes a switch that operates in response to the recording prevention pulse, and a variable voltage source that outputs a predetermined voltage, wherein the switch controls the input in response to the recording prevention pulse. 3. The VTR recording prevention circuit according to claim 2, wherein the circuit is switched to one of a television image signal and the predetermined voltage.
【請求項4】 前記遅延回路は、前記コンポジット同期
信号の立下がり(水平同期パルスの開始点)でトリガを
かけ、抵抗とコンデンサとで定まる一定時間幅のパルス
を出力する単安定マルチバイブレータを有することを特
徴とする請求項2記載のVTR録画防止回路。、
4. The delay circuit has a monostable multivibrator that triggers on a falling edge of the composite synchronization signal (a start point of a horizontal synchronization pulse) and outputs a pulse having a fixed time width determined by a resistor and a capacitor. 3. The VTR recording prevention circuit according to claim 2, wherein ,
【請求項5】 前記パルス生成回路は、前記遅延回路か
ら出力されるパルスの立下がり(開始点)でトリガをか
けて、抵抗とコンデンサ33とで定まる一定時間幅の前
記録画防止用パルスを出力する単安定マルチバイブレー
タを有することを特徴とする請求項2記載のVTR録画
防止回路。
5. The pulse generation circuit triggers on the falling edge (start point) of the pulse output from the delay circuit, and outputs the recording prevention pulse having a fixed time width determined by a resistor and a capacitor 33. 3. The VTR recording prevention circuit according to claim 2, further comprising a monostable multivibrator that performs the recording.
JP9263414A 1997-09-29 1997-09-29 Circuit for preventing vtr recording Pending JPH11103440A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9263414A JPH11103440A (en) 1997-09-29 1997-09-29 Circuit for preventing vtr recording

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9263414A JPH11103440A (en) 1997-09-29 1997-09-29 Circuit for preventing vtr recording

Publications (1)

Publication Number Publication Date
JPH11103440A true JPH11103440A (en) 1999-04-13

Family

ID=17389169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9263414A Pending JPH11103440A (en) 1997-09-29 1997-09-29 Circuit for preventing vtr recording

Country Status (1)

Country Link
JP (1) JPH11103440A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100433819C (en) * 2004-12-28 2008-11-12 河海大学常州校区 Method of scrambling process for analog video signal and scrambling circuit
US7782314B2 (en) * 2003-05-29 2010-08-24 Fujitsu Component Limited Device and system for synchronizing image signals transmitted with superimposed signals

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7782314B2 (en) * 2003-05-29 2010-08-24 Fujitsu Component Limited Device and system for synchronizing image signals transmitted with superimposed signals
CN100433819C (en) * 2004-12-28 2008-11-12 河海大学常州校区 Method of scrambling process for analog video signal and scrambling circuit

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