JPS62230057A - Vertical field-effect transistor - Google Patents
Vertical field-effect transistorInfo
- Publication number
- JPS62230057A JPS62230057A JP61074890A JP7489086A JPS62230057A JP S62230057 A JPS62230057 A JP S62230057A JP 61074890 A JP61074890 A JP 61074890A JP 7489086 A JP7489086 A JP 7489086A JP S62230057 A JPS62230057 A JP S62230057A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- breakdown resistance
- effect transistor
- vertical field
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract description 18
- 238000009413 insulation Methods 0.000 abstract 4
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は縦型電界効果トランジスタに関し、特に高い静
電破壊耐量が得られる縦型電界効果トランジスタに関す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a vertical field effect transistor, and particularly to a vertical field effect transistor that can provide high electrostatic breakdown resistance.
従来、縦型電界効果ｌ・ランジスタは、ゲート絶縁膜と
して酸化膜を用いていた。Conventionally, vertical field effect transistors have used an oxide film as a gate insulating film.
すなわち第２図に示すように、ドレイン高濃度基板１の
一主面にドレインのエピタキシャル層２が形成され、そ
の主面にチャネル形成領域３及びソース４が形成され、
その表面にゲート酸化膜５゜デー１〜電極７及び層間絶
縁膜８．ソース電極９゜トレイン電極１０が形成されて
構成されていた。That is, as shown in FIG. 2, a drain epitaxial layer 2 is formed on one main surface of a high drain concentration substrate 1, a channel forming region 3 and a source 4 are formed on the main surface,
A gate oxide film 5° 1 to electrode 7 and an interlayer insulating film 8 are formed on the surface thereof. A source electrode 9° and a train electrode 10 were formed.
し発明が解決しようとする問題点ｌ
１述した従来技術の縦型電界効果トランジスタでは、酸
化膜の比誘電率が比較的低いため、第３図に示すように
、静電破壊耐量は人力容量に比例するため、静電破壊耐
量の向Ｆに効果のある入力容￥の増大を行うためには酸
化膜の膜厚を薄くしなければならないが、酸１ヒ膜の膜
厚を薄くすると酸１ヒ膜部での電界強度が大きくなり、
絶縁破壊耐量が低下し、静電破壊耐量かあまり向−ヒし
ないという欠点があった。Problems to be Solved by the Invention 1 In the conventional vertical field effect transistor described above, the dielectric constant of the oxide film is relatively low, so as shown in Therefore, in order to increase the input capacitance, which is effective in increasing the electrostatic breakdown resistance, the thickness of the oxide film must be made thinner. The electric field strength at the 1st membrane increases,
It has the disadvantage that dielectric breakdown strength is reduced and electrostatic breakdown strength is not very strong.
本発明の目的は、単層デーｌ−絶縁膜の欠点を除去し、
絶縁破壊耐量を低下させずに入力容斌を増大させ、静電
破壊耐量の向、ヒされた縦型電界効果トランジスタを提
供することにある。The purpose of the present invention is to eliminate the drawbacks of a single layer dielectric film,
It is an object of the present invention to provide a vertical field effect transistor which increases input capacity without reducing dielectric breakdown strength and has improved electrostatic breakdown strength.
ｒ問題点を解決するための手段１
本発明の縦型電界効果Ｉ・う〉ジスタは、−主面にソー
ス及びゲートを有し、裏面にドレインを有する縦型電界
効果トランジスタにおいて、ゲート絶縁膜として酸化膜
と酸化膜に比較し比誘電率及び絶縁破壊耐量が約１．５
倍大きい窒化膜よりなる２層の絶縁膜を有している。Means for Solving Problem 1 The vertical field effect transistor of the present invention is a vertical field effect transistor having a source and a gate on the main surface and a drain on the back surface. As compared to oxide film, relative permittivity and dielectric breakdown strength are approximately 1.5.
It has a two-layer insulating film made of a nitride film that is twice as large.
次に、本発明の実施例について図面を参照して説明する
。第１図は本発明の一実施例の縦型電界効果型トランジ
スタの断面図である。第１図に於て１はドレインの高濃
度基板、２はトレインのエピタキシャル層、３はチャネ
ルを形成するドレインとは反対導電影領域、４はドレイ
ンと同導電形のソース領域、５は約３００人の酸化膜、
６は約２００人の窒化膜である。すなわちゲーＩ・絶縁
膜は３００人の酸化ｒｙＡ５と酸化膜に比較して絶縁破
壊耐量が同等で比誘電率の大きい窒化膜の２層構造とな
っている。この様にすることで従来均一酸化膜５００人
で５００ｐＦ程度の入力容量を持っていた素子が約１．
２倍６００ρＦの入力容量となり、それにつれて静電耐
量も約１７％の向上を達成している。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a vertical field effect transistor according to an embodiment of the present invention. In FIG. 1, 1 is the highly doped substrate of the drain, 2 is the epitaxial layer of the train, 3 is the conductive shadow region opposite to the drain forming the channel, 4 is the source region of the same conductivity type as the drain, and 5 is about 300 human oxide film,
6 is a nitride film of about 200 people. That is, the GaI insulating film has a two-layer structure of 300 oxide ryA5 and a nitride film which has the same dielectric breakdown strength and a higher dielectric constant than the oxide film. By doing this, a device that conventionally had an input capacitance of about 500 pF with a uniform oxide film of 500 people can be reduced to about 1.
The input capacitance is doubled to 600 ρF, and the electrostatic withstand capacity is also improved by about 17%.
また、７はゲート電極、８は層間絶縁膜であり、９はソ
ース電極である。Further, 7 is a gate electrode, 8 is an interlayer insulating film, and 9 is a source electrode.
［発明の効果ｊ
以ト説明した様に本発明はゲート絶縁膜を酸化膜と絶縁
破壊耐量が同等で比誘電率の大きい窒化膜を用いること
により絶縁破壊耐量を低下させずに入力容量を増大させ
、その結果として静電破壊耐量を向上させることが出来
るという効果が得られる。[Effects of the Invention j As explained above, the present invention increases the input capacitance without reducing the dielectric breakdown strength by using a nitride film, which has the same dielectric breakdown strength as an oxide film and a high dielectric constant, as the gate insulating film. As a result, the electrostatic breakdown resistance can be improved.
第１図は本発明の一実施例の縦型電界効果トランジスタ
の断面図、第２図は従来の縦型電界効果トランジスタの
断面図、第３図は静電破壊耐量と入力容量の関係を示す
図である。
ｌ・・・ドレイン高濃度基板、２・・・トレインのエピ
タキシャル層、３・・・チャネル形成領域、４・・・ソ
ース、５・・・酸化膜、６・・・窒化膜、７・・・ゲー
ト電極、Ｓ・・・層間絶縁膜、９・・・ソース電極、１
０・・・ドレイン電極。Fig. 1 is a cross-sectional view of a vertical field effect transistor according to an embodiment of the present invention, Fig. 2 is a cross-sectional view of a conventional vertical field effect transistor, and Fig. 3 shows the relationship between electrostatic breakdown resistance and input capacitance. It is a diagram. l...Drain high concentration substrate, 2...Epitaxial layer of train, 3...Channel formation region, 4...Source, 5...Oxide film, 6...Nitride film, 7... Gate electrode, S... interlayer insulating film, 9... source electrode, 1
0...Drain electrode.
Claims (1)
する縦型電界効果トランジスタにおいて、ゲート絶縁膜
が酸化膜と窒化膜の２層よりなる事を特徴とする縦型電
界効果トランジスタ。A vertical field effect transistor having a source and a gate on one main surface and a drain on the back surface, wherein the gate insulating film is made of two layers: an oxide film and a nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61074890A JPS62230057A (en) | 1986-03-31 | 1986-03-31 | Vertical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61074890A JPS62230057A (en) | 1986-03-31 | 1986-03-31 | Vertical field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62230057A true JPS62230057A (en) | 1987-10-08 |
Family
ID=13560417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61074890A Pending JPS62230057A (en) | 1986-03-31 | 1986-03-31 | Vertical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62230057A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5617074A (en) * | 1979-07-10 | 1981-02-18 | Thomson Csf | Field effect transistor and method of manufacturing same |
-
1986
- 1986-03-31 JP JP61074890A patent/JPS62230057A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5617074A (en) * | 1979-07-10 | 1981-02-18 | Thomson Csf | Field effect transistor and method of manufacturing same |
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