JPS62227277A - Clamping circuit for television signal - Google Patents

Abstract

PURPOSE:To reduce waveform distortion included in the synchronizing signal of a TV input signal, and to improve a clamping capacity, by providing plural number of clamp pulse generation circuits having different clamp pulse widths, and a control circuit which selects those clamp pulse widths. CONSTITUTION:A TV input signal (a) is inputted to a buffer l for the first, and a DC component is eliminated by a capacitor 2, and it is inputted to a buffer 3 simultaneously with a clamp pulse (b), then an output signal (c) being obtained. The clamp pulse (b) becomes a clamp pulse signal (b) in such a way that pulses (d), (e), and (f) having differenct pulse widths are outputed through respective NAND gates 8 by three control signals (g)-(i) outputted from a control circuit 4, and synthesized. When a clamp is performed by a clamp pulse (n) narrower than the width of the synchronizing Pulse of an input signal (m), a waveform distortion (s) is generated at the synchronizing signal part of a waveform (p) after clamped, and no sufficient time averaging for a clamp level setting is prepared, however, when the clamping is performed by a pulse (q) almost equal to the synchronizing pulse width of the input signal, a waveform distortion (t) included in the synchronizing signal part of a waveform (r) after clamped, is reduced, and the time averaging for the setting of the clamp level can be prepared sufficiently. Thereby, the clamping can be performed exactly.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television signal processing circuit, and more particularly to a clamp circuit for stabilizing the DC level of a television signal.

2. Description of the Related Art Conventionally, this type of clamp circuit has used a method of clamping the base level of a synchronizing signal using a clamp pulse in order to stabilize the DC level of a television signal.

Generally, the synchronization signal of a television signal consists of three components: a horizontal synchronization pulse, an equalization pulse, and a vertical synchronization pulse.
Each pulse is 0.08H.

0.04H,0,43)1()l: horizontal synchronization time), the clamp pulse l1liil& was determined to have a width suitable for the narrowest equalization pulse.

However, the clamping ability increases as the clamp width becomes wider.For example, when performing a horizontal sync pulse with a clamp pulse with a width suitable for the equalization pulse with the narrowest pulse width, as in the past, the sync signal part after clamping There were disadvantages in that waveform distortion occurred and sufficient time averaging could not be obtained when setting the clamp level.

The quality of this clamping ability is particularly important when digitally processing television signals.

Problems to be Solved by the Invention The purpose of the present invention is to solve the above-mentioned drawbacks, namely, when a horizontal or vertical synchronization pulse is clamped with a clamp pulse having a narrow pulse width, waveform distortion occurs in the synchronization signal portion after clamping, and level setting An object of the present invention is to provide a television signal clamping circuit which solves the problem of not being able to take a sufficient time average.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a plurality of clamp pulse generation circuits that generate clamp pulses with different pulse widths, and a television signal t-horizontal synchronizing pulse period 2. A control circuit that performs clamp control divided into three equalization pulse sections and a vertical synchronization pulse section, and a NAND gate that selects one of the clamp pulses from the plurality of clamp pulse generation circuits based on the output of this control circuit. The following configuration is adopted.

Operation Since the present invention is configured as described above, the control circuit generates a different control signal for each synchronization pulse section of the television signal, and the NAND gate generates a control signal from the control signal and the clamp pulses from the plurality of clamp pulse generation circuits. Select one of the clamp pulses.

Example Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, which shows a block diagram of a first embodiment of the present invention, the television signal clamping circuit of the present invention includes:
A main circuit in which input signal a passes through buffer 1, capacitor 2, and buffer 3 and is output as output signal C, and input signal a
a control circuit 4 which receives input and outputs three control signals g*he i, and clamp pulse generation circuits 5, 6.7 which generate three clamp pulses d, e, f, respectively,
Control signal g.

h, i and clamp pulses d, e, f, respectively, are inputted correspondingly to three NAND gates 8 which output their NAND outputs, and the outputs of these three NAND gates 8 are as follows. Combined signal buffer 3
input to the other terminal.

Furthermore, the pulse widths of the clamp pulses d, e, and f are as follows:
Horizontal sync pulse width 2 equalization pulse width, respectively.

It is predetermined to be suitable for vertical synchronization pulse 14. FIG. 2 is a timing diagram of these signals.

Next, the operation of this embodiment will be explained using FIGS. 1 and 2.

The television input signal a is first input to a buffer 1, a DC component is removed by a capacitor 2, and is input to a buffer 3 at the same time as the 2-amp pulse b, so that an output signal C is obtained.

Clamp pulse b consists of three types of pulses d with different pulse widths.
, e, f are three control signals g output from the control circuit 4.
V hl '' is outputted through each NAND gate 8 and synthesized to form a clamp pulse signal. That is, according to the timing diagram of FIG. The signal g becomes 118, and the complement of the clamp pulse d becomes the clamp pulse b by the NAND gate 8. In the equalization pulse section, the control signal becomes 111, and the complement of the clamp pulse e becomes the clamp pulse b by the NAND gate 8.
Further, in the vertical synchronization pulse section l, the control signal i becomes 61m, and the complement value of the clamp pulse f becomes the clamp pulse b by the NAND gate 8.

FIG. 3 is an enlarged view of the synchronizing pulse, and the operation of the clamp will be explained using this FIG. When clamping the input signal mf, if you clamp it with a clamp pulse n narrower than the width of the synchronization pulse of the input signal m, the waveform after clamping p
A waveform 7s occurs in the synchronization signal portion of , and sufficient time averaging cannot be obtained due to the clamp level setting.

On the other hand, when clamping with a clamp pulse q that is almost equal to the sync pulse of the input signal, the waveform it included in the sync signal part of the waveform r after clamping is smaller than the previous waveform distortion S and is at the clamp level. Sufficient time average for setting can be obtained.

The relationship between the clamp pulse n and the post-clamp waveform p corresponds to the case where the horizontal synchronizing pulse is clamped with a clamp pulse having a width suitable for clamping the equalization pulse,
The relationship between the clamp pulse q and the post-clamp waveform r corresponds to the case where the horizontal synchronizing pulse is clamped with a clamp pulse having a pulse width suitable for the horizontal synchronizing pulse. That is, it can be seen that when the clamp pulse q is wide, the waveform distortion is smaller and the time average for setting the clamp level can be sufficiently obtained. Therefore, this embodiment has the advantage of ensuring reliable clamping.

FIG. 4 is a block diagram showing a second embodiment in which the width of the clamp pulse is 28, and FIG. 5 is a timing diagram thereof.

As shown in the fourth factor, this second embodiment does not have the clamp pulse generation circuit 7 in contrast to FIG. The selection is made using the NAND gate 8. Therefore, for clamping the horizontal synchronizing pulse, a clamp pulse d suitable for clamping the horizontal synchronizing pulse is selected, and the operation is exactly the same as in the first embodiment, and the same advantages are obtained. The vertical synchronization pulse uses a clamp pulse e suitable for clamping the equalization pulse. Therefore, although the clamping width is narrow and the clamping ability cannot be improved in one vertical synchronization period in Figure 5, the proportion of vertical synchronization pulses in the image signal is much larger than the proportion of horizontal synchronization pulses in the image signal. Considering the fact that the number is small, there is an advantage that the circuit configuration becomes simple.

Effects of the Invention As explained above, according to the present invention, by including a plurality of clamp pulse generation circuits having different clamp pulse widths and a control circuit for selecting the clamp pulse generation circuits, one equalization pulse in the horizontal synchronization pulse section can be generated. section.

The vertical synchronization pulse section can be divided into three sections, and each section can be clamped to the base level of the synchronization signal using one of the pulse widths, and the waveform distortion contained in the synchronization signal of the television input signal can be clamped. This has the effect of reducing the amount of stress and increasing the clamping ability.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of the first embodiment of the present invention;
The figure is a timing diagram of each signal in Figure 1, Figure 3 is an enlarged explanatory diagram when clamping the synchronization pulse, and Figure 4 is a block circuit diagram of the second embodiment when the width of the clamp pulse is two types. , FIG. 5 is a timing diagram of each signal in FIG. 4. 1...Buffer, 2...Capacitor,
3... Buffer, 4... Control circuit, 5
, 6, 7... Clamp pulse generation circuit, 8...
...Nand Gate, 9...Or Gate, a
...Input signal, b, u...Control clamp pulse, C, V...Output signal, d, e, f...
...Generated clamp pulse from 5 and 6.7 respectively, g + he i ... control signal, j ...
...Horizontal synchronization pulse section, k... Equalization pulse section,! -...Vertical synchronization pulse section. b------One choice talent, one half Xta, Otsu,
7---Clambuhares d, e, f/) origin trgJ,
S2, i, i ---1 system 7 wholesale signal Figure 1 u----'4 7 and 6 Kulbha tsu more, +,, 6
---Classic Bunno\tsu Us d, e/) JE birth f each J,
Figure 4.

Claims (1)

[Claims] In a clamp circuit that inputs a television signal and a clamp pulse for clamping the base level of the synchronization signal in this television signal and stabilizes the DC level, a plurality of clamp pulses that generate clamp pulses with different pulse widths are used. A clamp pulse generation circuit, a control circuit that performs clamp control by dividing the television signal into three sections, a horizontal synchronization pulse section, an equalization pulse section, and a vertical synchronization pulse section, and a control signal output from this control circuit. and a NAND gate for selecting one of the clamp pulses from the plurality of clamp pulse generation circuits.