JPS62226711A - Oscillation circuit - Google Patents

Abstract

PURPOSE:To suppress the current of a signal input section to a permissible value and to improve the power voltage characteristic of the oscillation frequency by setting the value of each gate capacitance of p-and n-channel MOSFETs in a CMOS inverter of the 2nd stage smaller than each gate capacitance of the lst stage inverter by a prescribed value only. CONSTITUTION:The dimension W/L of the p-and n-channel MOSFETs 1,2 in the lst stage inverter I1 is selected larger in a range where its input current is permitted. Further, the dimension W/L of the p-and n-channel MOSFETs 3,4 of the 2nd stage inverter I2 is selected smaller than that of the lst stage by a prescribed value only. Thus, the gate capacitance 11b of the inverter I2 of the 2nd stage being the output load capacitance of the lst stage inverter I1 is decreased. In selecting the W/L of the p-and n-channel MOSFETs 3,4 constituting the 2nd stage inverter I2 smaller than that of the lst stage in this way, the capacitance C1 of the gate capacitance 11b of the 2nd stage inverter I2 is lowered and the increasing tendency of the propagation delay time T is compensated.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an oscillation circuit in which the oscillation frequency is defined by the values of a capacitor and a resistor, and is particularly intended to stabilize the oscillation frequency against fluctuations in power supply voltage. It is.

[Technical background of the invention and its problems] As a conventional oscillation circuit, there is one shown in FIG. 7, for example (Japanese Patent Publication No. 12763/1983).

Figure 7: Middle tube numbers 24, 26, and 28 are p-channel M, respectively.
OSFET (hereinafter referred to as pMoS), 25.27
．． 29 is nMO3, and each pair of 0MO8 and nMO8, 24, 25.26, 27.28, and 29, constitutes each CMOS inverter (hereinafter simply referred to as an inverter) 21, 22, and 23 from the first stage to the third stage. These are connected in cascade.

For cascade connection, for example, the second stage inverter 22
The input terminal 22a of the inverter 21 becomes the output terminal of the first stage inverter 21. Hereinafter, the input end of the next stage inverter will also be referred to as the output end of the previous stage inverter.

Each inverter 21, 22, 23 has J3 [Pur pM.

The sources of S24, 26, and 28 are connected to the input terminal 12 of power supply voltage Vdd, and the sources of nMO825, 27, and 29 are each grounded.

A positive feedback capacitor 13 is connected between the input end 21a of the first-stage inverter 21 and the output 123a of the second-stage (even-numbered stage) inverter 22.
1 input terminal 21a and the third stage (odd stage) inverter 3
A negative feedback resistor 14 is connected between the output terminal 23b and the output terminal 23b.

The output terminal 23b of the third stage (RN stage) inverter 23 serves as an output terminal for the oscillation pulse signal.

It is assumed that the capacitor 13 is not initially charged, and at the current time 1=0, the power input terminal 12
If the driving power supply voltage Vdd is applied stepwise to 1), one of the MOSs 24, 26, and 28 turns on.

Assuming that the pvos 24 turns on, the output terminal 22a of the first stage inverter 21 rises to the Vdd potential,
Next, nMO827 and pMO828 are turned on in sequence, and the output terminal 23a of the second stage inverter 22 is set to the ground potential, 3
The output terminal 23b of the inverter 23 in the second stage is at the Vdd potential.

Therefore, due to the potential difference between the Vdd potential at the output terminal 23b of the third stage inverter 23 and the ground potential at the output terminal 23a of the second stage inverter 22, the capacitor 13 is charged via the resistor 14, and the capacitor 13 is charged through the resistor 14. Input end 21
The potential of a gradually rises from the ground potential, and the inverter 2
When the logical threshold voltage Vdd/2 of 1 is reached, the first stage inverter 21 is inverted and its output 122a becomes the ground potential.

Next, the second and third stage inverters 22 and 23 are each inverted, and the output terminal 23a of the second stage inverter 22 changes to the Vdd potential, and the output terminal 23b of the third stage inverter 23 changes to the ground potential.

Due to this change of the output terminal 23b to the ground potential, the charge in the capacitor 13 is transferred through the resistor 14, and the potential of the input terminal 21a decreases to Vdd/2.
The first stage inverter 21 is inverted again and its output terminal 22a
is about Vddffi. Next, the inverters 22 and 23 in the second and third stages are each inverted, and the output terminal 23a of the inverter 22 in the second stage becomes the ground potential, and the output E23b of the inverter 23 in the third stage becomes the Vdd potential. As a result, the capacitor 13 is charged again.

As described above, the differential and integral voltage waveforms generated by the positive feedback capacitor 13 and the negative feedback resistor 14 are transferred to the first stage inverter 2.
1 input saw signal, each inverter 21, 22, 23 repeats the inversion operation and oscillation operation occurs, and the capacitor 13 and the resistor 1 are connected from the output terminal 23b of the final stage inverter 23.
A pulse oscillation signal having a frequency defined by the value of 4 is output.

As described above, in this type of oscillation circuit, a differential and integral voltage waveform signal is input to the first-stage inverter 21, so the current flowing through this signal input section becomes considerably large. For this reason, when the oscillation circuit is combined with other digital circuits, the proportion of power consumed by the oscillation circuit becomes considerably larger than the power consumed by the digital circuit as a whole.

In order to reduce the current in the signal input section of the first stage inverter 21, it is necessary to
The value of W/L (W: channel width, L: channel ring) of 's24 and nMO825 may be shifted to a smaller value.

However, if the W/L of the first-stage inverter 21 is made smaller, the transmission delay time in the first-stage inverter 21 becomes
The time constant determined by the positive feedback capacitor 13 and the negative feedback resistor 14 is so large that it is not negligible, and this transmission delay time is dependent on the power supply voltage, so that the power supply voltage Vdd is For example, there is a problem in that when the voltage drops below a predetermined voltage value, the oscillation frequency fluctuates in a lower direction.

[Object of the Invention] The present invention has been made based on the above circumstances, and provides an oscillation circuit that can suppress the current in the signal input section of the first stage inverter to a permissible value and improve the power supply voltage characteristics of the oscillation frequency. The purpose is to

[Summary of the invention] In order to achieve the above object, the present invention provides a pair of 0MO8
A plurality of inverters consisting of 0MO8 and nMO8 are connected in cascade, and a positive feedback capacitor is connected between the input terminal of the first stage inverter and the output terminal of the even-numbered stage inverter. A resistor for negative feedback is connected between the input terminal of the first stage inverter and the output terminal of the odd-numbered stage inverter, and the plurality of inverters are driven by the power supply voltage and are regulated by the values of the capacitor and resistor. In an oscillation circuit that oscillates a signal with a frequency of 2
The value of each gate capacitance of 0MO8 and nMO8 in the inverter in the first stage is expressed as l) M in the inverter in the first stage.
OS1J3J: By setting the required value smaller than the value of nMO8, the output load of the first stage inverter is reduced, and the transmission when the current of the signal input section of the first stage inverter is reduced. The tendency of the delay time to increase is compensated for by decreasing the output load capacity, and the oscillation frequency is stabilized against fluctuations in the power supply voltage.

[Embodiments of the Invention] Examples of the present invention will be described below with reference to FIGS. 1 to 6.

In FIG. 1, etc., circuit elements that are the same as or equivalent to the circuit elements shown in FIG.

First, to explain the configuration, Fig. 1 middle mark @1.3.5.7.
9 is each 0MO8, 2, 4, 6, 8, and 10 are each nMO8, and each of these elements is formed on the same semiconductor chip.
2.3, 4.5, 6.7, 8.9, and 10 constitute 0MO3 inverters 11 to 15 from the first stage to the fifth stage, and these are connected in cascade. The output terminal f of the fifth stage (final stage) inverter I5 serves as the output terminal for the oscillation pulse signal.

15 is a resistor for protecting the gate of the first stage inverter 11, 16
．． 17 is a diode, and these resistor 15 and each diode 16, 17 are formed by a diffusion layer on the main surface of the semiconductor chip.

11a to 11f are capacitances existing at the input terminals and output terminals a to f of each inverter II to 15, and each inverter 1
ff111a-1 present at the input terminals a-e of 1-]5
1e mainly constitutes each inverter 11 to I5.
MO81,3,... and nMO82,4,...
is formed by the gate capacitance of

And in this example, the first stage inverter! The value of each W/l- of pMO81 and nMO82 at + is set large within a range that allows the input current value. Along with this, the second stage inverter 1
The values of each W/l- of pMO83 and nMO84 in 2 are set smaller than the respective W/L values of pMO81 and nMO82 in first-stage inverter 1 by a required value, and the output Ω load capacity of first-stage inverter 11 is Hanging 2
The gate capacitance ff111b of the inverter (2) in the second stage is reduced.

Next, by setting the value of W/L as described above, the tendency for the propagation delay time to increase when the current at the signal input section of the first stage inverter 11 is reduced is compensated by the decrease in its output load capacity. Explain why.

First stage inverter now! Assuming that the current flowing into the gate capacitance fi11 lb of the second stage inverter I2, which has a positive output load capacity, is In, this current Itl is expressed by the following equation.

In-(βp/2)・(Vdd-V in-Vthp)2-(βn/2)(Vin-Vthn)2...<1> Here, βp1βn is each gain constant of pMO8XnMO8, βn=( (μpεox)/1ox) ・(Wl)/11)) βn= ((μnεOX)/1ox) ・Wn/L n ) μp, μn: p, n Carrier mobility of each MO3 wp/Lp, Wn/Ln : p, n channel width of each MO8/channel t7 channel quality εOX: dielectric constant tox of gate oxide film: thickness of gate oxide film vthp, vthn: p, n threshold voltage vin of each MO8: first stage impark 11 Input voltage Vdd: power supply voltage Among the above constants or values, β = βp = βn Vth = Vthp = Vthn V i n = (Vdd/2) + Δvin (ΔV i
n: 1iQL! I! fJli ['ffi pressure Vd d
/ 2 k')) Then, the above equation (1) becomes ri=β(2Vth-Vdd) ・ΔV i n-<2
).

If the change in output voltage is ΔV, first stage inverter 1
1 increases the output load capacitance fallb by this ΔV in the vicinity of the logic threshold voltage. - Must be discharged or discharged.

Here, the change in the input voltage of the first stage inverter 10 Δ■i
n to ΔV i n=--t=(3)
K: constant representing the slope t = time situation, then the above equations (2) and (3) IJ1 et al. (VCld
/2)+∆V Coffinf dV Vdd/2 -/β(2Vth-Vdd)K-td t...
(4), and from the above equation (4), the first stage inverter 1
The time required for the output voltage to change by the voltage ΔV corresponding to Vin due to the change in the input voltage, that is, the transmission delay time T, is determined by the following equation.

T-mnuΣrττgo'- / [β(Vdd-2Vth)K) ・(5) However, C1
:Capacitance value of gate capacitance 11b of second-stage inverter 2 From the above equation (5), in order to reduce the current at the signal input section of the first-stage inverter I+, if the value of W/L of 0MO81 and nMO82 is reduced, As the value of the gain constant β becomes smaller, the propagation delay time T tends to increase. However, as mentioned above, since the values of W/L of pMO83 and 0MO34 constituting the second stage inverter I2 are set even smaller than those of the first stage, the gate capacitance ff1llb of the second stage inverter 12 is The capacitance value C is reduced, thereby compensating for the increasing tendency of the transmission delay time ]°.

Furthermore, the relationship in equation (5) above is applied b to the second-stage inverter ■2, so this inverter I2 is (i1
If the values of W/L of each of the 0MO33 and nMO84 that form one are set small as described above, the value of the gain constant β becomes small, and the transmission R-lag time T tends to increase.

However, regarding the second stage inverter 12, the above (3)
Expressing the slope in the equation, due to the amplification effect of the first-stage inverter ■1, the value of the constant in the first-stage inverter I becomes K(K'). Regarding the inverter 2, even if the value of β in the equation (5) becomes small, the transmission delay time ■ does not increase due to an increase in the constant representing the slope.

As mentioned above, the values of W/L of pMO83 and nMO84 which constitute the second stage inverter 2 are the same as those of pM○S1 and nMO82 which constitute the first stage inverter +.
As a result, if the capacitance value of the gate capacitor ff111a of the first stage inverter 11 is C1o, then C0o > C1.

Note that it is desirable to set the W/L of MOS 1 and nMO82 in the first stage inverter + to a large value within the range that allows the current of the signal input section. If the value of C1o is set to a large value and the value of C1o becomes more noticeable to some extent, then if we compare this with Cf of capacitor 3 for positive feedback, we find that the relationship Cf>Cio, so this gate capacitance value Clo has very little effect on changes in oscillation frequency.

In addition, WpI, Wnl: Channel width of the first stage p, n8 MO3 Wnl, Wnl: Channel width of the second stage p, n MO8
l channel width Ll)+, Ln+: CH of each MO8 of first stage p and n
y channel lengths Lp2, Ln2: Assuming the channel lengths of the second stage p and n MO3, the channel length is normally designed with the minimum dimension according to the 91 rule, Lp+ = I-n+ = Iyp2 = Ln2 = L
= (6), so in this embodiment, each W of each of p and n MOs 31 and 2 in the first stage inverter 11 is
/L and p, r1MO in the second stage inverter I2
Each W/L of 33 and 4 is W n + / L > W n 2 / LWp+
/L>Wnl/L is set.

Next, put [
The following describes the value of W/L.

Here, while the inverter of the conventional example shown in FIG. 7 has three stages, the inverter of this embodiment shown in FIG. 1 has five stages.
It is arranged in stages. The main reason for this is that when attempting to obtain a relatively low oscillation frequency, the value Cf of the positive feedback capacitor +113 needs to be set too large. For this purpose, it is better to use a buffer instead of directly supplying the charge current from the output terminal C of the second stage inverter I2, which has a small W/L value for pMO8 and nMO3, to the capacitor 13. . In order to have this buffer function, each inverter 13.
14 is connected, and the fourth stage (even stage) inverter 14
The output terminal e of is connected to the capacitor 13.

Further, a fifth stage inverter I5 is connected, and an output terminal f of this fifth stage (odd stage) inverter I5 is connected to the resistor 14.

Assuming that the time required to charge or deplete the positive feedback capacitor 13 is "f", this time Tf is expressed by the following equation.

Tf=2-Cf/(β-(Vdd-Vth)2)...
・(7) Therefore, β−[(μεox)/1ox) ・(W/L) Vth: p, n The threshold voltage of each MO8 The W/L value W4/L4 of the fourth stage inverter I4 is the above The time Tf in equation (7) is Cf-Rf'>Tf,! = is set so that However, Rf is the resistance value of the resistor 14.

In addition, the W/L value W3/L3 of the third stage inverter I3 is
When the value of the second stage inverter W/L is divided by W2/L2, W3 /l-3=J (W2 /l-2) (W4
/L4).

Furthermore, the W/L value W5/L of inverter I5 of 5 stages 1]
5 is set to a value such that its on-resistance is sufficiently smaller than the resistance value Rf of the resistor 14 in negative feedback operation.

Next, the operation will be explained using (Δ) to (F) in FIG.

(A) to (F) in FIG. 2 show the waveforms of the potentials at points a-f in FIG. 1, respectively. In FIG. 2, v'1 and Vf2 indicate the forward voltages of the diodes 16 and 17, respectively.

The fact that the oscillation operation occurs due to the inverting operation of each inverter 1 to I5 is almost the same as that shown in FIG. 7, and the point t1 between 14 in FIG.
O81 is on, and accordingly G) nMO8 from the second stage onward
4, pMO35, nM.

This shows a state in which S8 and pMO89 are sequentially turned on. In this state, the output I of the fifth stage inverter I5
The capacitor 13 is charged via the resistor 14 due to the potential difference between the Vdd potential of f and the 07!2 position (ground potential) of the output terminal e of the fourth stage inverter I4.

As a result of this charging, the potential at the input terminal a of the first-stage inverter r+ rises, and when it becomes different from the logical threshold voltage vth2Vdd/2 of the inverter 11 at time t2, the first-stage inverter 11
is inverted, and the potential at point b is inverted from the Vdd potential to the O potential. Next, each of the inverters 12 to I5 in the second to fifth stages is inverted, and the output %i of the fourth stage inverter I4 is
e is the Vdd potential, and the potential of the output terminal f of the fifth stage inverter 15 changes to the ON level.

The inversion of the output e4e of the inverter 14 to Vddff1 is fed back to the input terminal a of the first stage inverter 11 through the converter 1 node 13, and the potential of the input terminal a becomes Vdd+
The potential becomes Vf+. At this time, as mentioned above, the potential of the output terminal f of the fifth stage inverter I5 has changed to about 0m, so the charge in the capacitor 13 is discharged through the resistor 14, and at time t4, the potential of the output terminal f of the fifth stage inverter I5 has changed to about 0 m. The potential is Vth;
When the voltage drops to Vdd/2, the first stage inverter 11 is inverted again, and the potential at its output terminal becomes Vdd potential.

Next, the inverters I2 to I5 in the second to fifth stages are inverted, and the output terminal e of the inverter I4 in the fourth stage becomes 01.
The potential of the output terminal f of the fifth stage inverter I5 is Vdd.
Changes to electric potential.

The inversion of the output terminal e of the fourth stage inverter 14 to the O potential is fed back to the input terminal a of the first stage inverter 11 through the capacitor 13, and the potential of the input +'f4 a becomes -vf.
It becomes 2. At this time, the potential of the output terminal f of the fifth stage inverter I5 has changed to the Vdd potential, so the resistor 1
4, the capacitor 13 is charged again, and the potential at the input terminal a approaches the logic threshold voltage vth. Thereafter, the above operation is repeated to generate an oscillation operation.

In such an oscillation operation, each W/L of 0MO81J3 and nMO84 in the first stage inverter 11
The value of is set to a value that can suppress the input current value due to the input voltage of the differential and integral waveform shown in Figure 2 (A) to an allowable value, so the power consumption in the oscillation circuit will be particularly large. can be avoided.

In addition, p in the second stage inverter I2
The values of W/L of MO33 and nMO84 are as follows: l) MOS 1 and nMO8 in the first stage inverter I+
2 is set smaller than each W/L value by the required value,
The capacitance value Cl of the second-stage inverter I2 in the equation (5) is set smaller by a required value. Therefore, the value of the transmission delay time T in the first-stage inverter 11 is approximately 1 (
Even if the power supply voltage Vdd fluctuates, the oscillation frequency can be stabilized.

Next, l) MOS3 and nMO in the second stage inverter I2 are explained using specific numerical examples using FIGS. 3 to 6.
It will be further explained that when the value of each W/L of 84 is set small by a required value, the transmission delay time T becomes small and the oscillation frequency is stabilized against fluctuations in the power supply voltage Vdd.

Figure 3 shows a test circuit showing only the first and second stage inverters I+ and +2 in Figure 1, and Figure 4 shows a triangular wave test input input to input point a in Figure 4. Voltage Vin, (△) and (B) in FIG. 5 show the output waveform of the first stage inverter 11 near the threshold voltage at the time of rising and falling of the input voltage Vin, and (△) in FIG.
), (B), the symbols (a), (b), and (c) are
pMO83 and nM in second stage inverter I2
Each case is shown in which the values of each W/L of O34 are set as shown in the following table.

(Unit: μm) The test results under the above conditions are shown in (A) and (B) in Figure 5.
), the W/L at the second stage inverter I2
When the value of is set small, the delay time T in the vicinity of the logic threshold voltage becomes small both at the rise and fall of the input voltage vin.

Fig. 6 qualitatively shows the oscillation period of the oscillation circuit when the value of W/L in the second stage inverter I2 is set to a small value and when it is set to a large value, based on the input voltage of the input terminal a. It is something that If the W/L of the second stage inverter 12 is set to human, the oscillation period will be improved.

If the value of W/L in the second stage inverter I2 is set to a large value, the gate capacitance value C! As the frequency changes, the oscillation frequency becomes more susceptible to fluctuations in the power supply voltage Vdd.

J3 In the above embodiment, the inverter is set to five stages, but the present invention is not limited to this number of stages, and may be set to six or more stages. If the capacitance value of 13 is small, it can be configured in three stages.

[Effect of the invention] As explained above, according to this invention, a pair of 0MO8
A plurality of inverters consisting of 0MO3 and nMOS are connected in cascade, and a positive feedback capacitor is connected between the input terminal of the first stage inverter and the output terminal of the even-numbered stage inverter. An n-feedback resistor is connected between the input terminal of the inverter and the output terminal of the odd-numbered stage inverter, and the second stage l) MOS and nMOS in the inverter, pMO in the first stage inverter
3 and nMOS by the required value, the output load capacitance l of the first stage inverter is reduced,
The tendency for the propagation delay time to increase when the current in the signal input section of the first-stage inverter is reduced is compensated for by the decrease in the output Q capacity, and the current in the signal input section of the first-stage inverter is suppressed to an allowable value. In addition, it has the advantage that the oscillation frequency can be stabilized against fluctuations in the power supply voltage.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the oscillation circuit according to the present invention, FIG. 2 is a timing diagram showing the potentials of the output ends of each inverter, etc.
The figure is a partial circuit diagram showing the inverters up to the second stage of the circuit in Figure 1, Figure 4 is a waveform diagram showing the input voltage for testing to analyze the transmission delay time, and Figure 5 is for the same test. An output characteristic diagram showing the output waveform of the first stage inverter with respect to the input voltage, Figure 6 is a characteristic diagram showing the change in oscillation cycle with respect to W/L change in the second stage inverter, and Figure 7 is a conventional oscillation circuit. FIG. 1.3.5.7.9: 0MO8° 2.4.6.8.10: nMOS. 12: Power supply voltage input terminal, 13: Capacitor, 14: Resistor, 1+ -I5: CMOS inverter, a: First stage CM
Input terminal of OS inverter, e: 4th stage (even stage) C
Output terminal of MOS inverter: Output terminal of 5th stage (odd stage) CMOS inverter. Figure 2 Figure 3 Section 6 Figure 7

Claims (1)

[Claims] A pair of p-channel MOSFET and n-channel MOS
A plurality of CMOS inverters composed of FETs are connected in cascade, and a capacitor is connected between the input terminal of the first stage CMOS inverter and the output terminal of the even-numbered stage CMOS inverter, and the capacitor is connected between the input terminal of the first stage CMOS inverter and the output terminal of the even-numbered stage CMOS inverter. In an oscillation circuit that connects a resistor to the output terminal of an odd-numbered CMOS inverter and oscillates a signal with a frequency determined by the values of the capacitor and resistor, the p-channel MOS in the second CMOS inverter
The value of each gate capacitance of FET and n-channel MOSFET is calculated as p-channel M in the first stage CMOS inverter.
An oscillation circuit characterized in that the gate capacitance of each of an OSFET and an n-channel MOSFET is set to be smaller by a required value than the value of each gate capacitance.