JPS62222343A - Virtual computer system - Google Patents

Abstract

PURPOSE:To improve an instruction processing capacity by holding the identification information of a guest virtual computer for a prescribed time and comparing identification information with held information when the execution of the guest virtual computer is started and starting the execution of the computer in accordance with the comparison result. CONSTITUTION:A guest virtual computer (VM) mode register 5, an ACT-VM identification information (VMID) register 7, etc., are connected to an instruction executing part 1, and the register 7 is connected to a comparator 13 directly or through a LAST-VMID register 12, and a register 5, the circuit 13, etc., are connected to an address conversion buffer (TLB) write control part 2. When the execution of the guest VM is started, the guest VM is executed immediately if contents of registers 5 and 7 coincide with each other, and the valid field of a guest entry of the TLB 3 is invalidated to execute the guest VM; and when the execution of the guest VM is terminated, the identification information VMID of this VM is stored in a register 12 from the register 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a virtual computer system, and particularly to processing of an address translation buffer that holds address translation information of a host computer or a guest virtual machine.

[Conventional technology]

In a virtual machine system, the host control program usually issues a virtual machine execution start command (hereinafter referred to as the SIE command).
After this is executed, the operation of the virtual machine (hereinafter referred to as VM) is started. For example, IBM's 370/XA architecture is known as a virtual machine architecture.
For details, see Publication No. 12680.

FIG. 2 shows the instruction format of the SIE instruction. The SIE command is
The 7M state descriptor (hereinafter referred to as SD) located by its B2 and D2 fields is specified as an operand. In FIG. 2, 58 is an SIE instruction, 59 is a main storage area, and 60 is a 7M state descriptor (SD).

Central processing unit? The instruction execution unit 2 (hereinafter referred to as CPU) uses the main memory bag! (below,
The information specified in each field of the SD (referred to as MS) is set in the hardware resources of the CPU, and the CPU is operated as a guest VM.

As shown in FIG. 2, the hardware resources set at this time include the guest mode register, PSW, control register (CR), general purpose register (GR), prefix, and MS extent register. on the other hand,
The host state is saved within the CPU. In this way, S
D describes the architecture of the guest VM from the perspective of guest instructions.

Guest VMs started by SIE commands.

Emulate a guest program until an interrupt event or interception occurs.

An interrupt event is a case that requires host processing, such as an input/output interrupt or an external interrupt.

Interception occurs when, for example, an instruction that requires host processing is executed. For some privileged instructions, whether or not to cause interception can be specified using the interception mask field in the SD. When an interrupt event or interception occurs, the guest VM exits, the CPU goes into host mode, is restored to the state it was in when it started executing the SIE instruction, and the instruction counter in the PSW is set to SI
Indicates the next command after the E command.

One of the important technical issues in virtual computer systems is:
This is a way to express the guest's "main memory." A guest VM started with a SIE instruction uses two modes: page storage mode and priority storage mode.

FIG. 3 shows address space mapping in page storage mode. Guest virtual address (GV) 6
1 is translated to the guest's absolute address (GA) 62 by guest address translation. Check that this GA 62 is within the MS extent specified by the SD. The MS origin is added to the GA to determine the host virtual address (HV) 63. The HV is translated to a host absolute address (HA) 64 by host address translation.

In priority storage mode, the guest's absolute address remains as is\
Treated as the absolute address of the host.

The CPU has an address translation buffer to perform address translation at high speed. In either mode, the entry in the address translation buffer (TLB) contains G
A pair of V and HA is registered. Therefore, TLB in GV
By referring to , HA can be immediately determined.

TL in a virtual computer system with the above architecture
The B configuration is described in detail in Japanese Unexamined Patent Publication No. 57-212680. There, a guest field of 1 bit is provided in each TLB entry, and it is set to "O" when host address translation information is registered, and "1" when guest VM address translation information is registered.
It becomes possible to identify host entries and guest entries, and address translation information for the host and one guest VM is held simultaneously in the TLB.

[Problem that the invention seeks to solve]

In the conventional technology, the number of guest VMs that can be held in the TLB is limited to one, so when executing a certain guest VM,
It is not possible to hold entries for other guest VMs in the TLB. In the above-mentioned Japanese Patent Laid-Open No. 57-212680, when execution of a guest VM ends due to two interrupt events or interception, all guest entries of the guest VM are invalidated. Therefore, when the guest vM is restarted by the SIE command, a new address translation will occur when accessing the page corresponding to the entry registered in the TLB when the guest VM was previously terminated, resulting in an increase in instruction processing performance. This results in significant overhead.

FIG. 4 explains this, and in the conventional technology, guest V
When ending the execution of M (at the end of the execution of the guest program ! and
The same guest VM (guest program I)
When the program (2) is started again, the TLB barge at the end of execution of the guest program I is unnecessary, and an additional overhead is generated in terms of instruction processing performance.

An object of the present invention is to provide a virtual computer system that improves instruction processing performance by purging TLB guest entries only when truly necessary. In 2N, the case where it is truly necessary to purge the TLB guest entry is when two consecutively started guest VMs are different.

(Means for Solving the Problems) The present invention provides a guest VM that represents the guest VM corresponding to the guest entry held in the TLB, from the time the execution of the guest VM ends, until the next execution of the guest VM starts. Last guest VM identification information register (referred to as LAST-VMID register) to hold VM identification information (referred to as VMID)
and an act guest VM identification information register (ACT-
VMID register), means for comparing the LAST-VMID register and ACT-VMID register, and TLB guest entry purging means for retaining or purging the TLB guest entry in response to the comparison result.

[For production]

Execute the SIE command in the host management program and
When starting M, the guest VM (7) VMI that was executed last time
The value of the LAST-VMID register holding D,
ACT-V that stores the guest VM you are trying to start
Compare the values in the MID register. When the two match, the guest entry in the TLB is kept as is and the guest VM starts running. When the two do not match, all guest entries in the TLB are purged and execution of the guest VM is started. In addition, the VM to the LAST-VMID register
The ID is set, for example, at the end of execution of the guest VM, and is retained during execution of the host program.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in particular, the TL of the central processing unit (CPU) of the virtual computer system.
Only the parts related to the B reference are shown.

In FIG. 1, the instruction execution unit 1 includes a guest 7M mode register (G mode register) 5. Valid bit (
V bit) register 6, ACT-VMID register 7,
Guest segment, table origin register (
GST○ register) 8, host segment table origin register (H8TO register) 9, real mode (R mode) register 10, and TLB reference address register 11 are connected. ACT-V
MID register 7 is further connected to LAST-VMID register 12 .

As mentioned above, execution of the guest VM begins when the SIE instruction is executed in the host program. Guest VM
The identification information is the SD address.

The value of the VMID field in the SD can be considered, but
Below, we will use the SD address as guest VM information (VMID)
An example will be explained below.

The instruction execution unit 1 sets the G mode register 5 to “1” to process the SIE instruction, and sets the SD address to ACT-V.
The value of the CR1 field in the SD (MS origin) is set in the 08TO register 8 in MIDL/DIST. G
When mode register 5 is "0", the CPU operates as a host computer, and when mode register 5 is "1'", it operates as a guest virtual machine.6 When execution of the guest VM is terminated due to an interrupt event or interception in the guest program, G
The mode register 5 is reset to 10'' by the instruction execution unit 1. The GST register 8 is used for guest address translation and identifies the guest address space.H3TO
Register 9 is used for host address translation and identifies the host address space.

H5TO register 9 and 08To register 8.

It is updated when the instruction execution unit 1 executes an LCTL instruction (an instruction for rewriting a control register) in the host program and guest program, respectively.

The R mode register 10 indicates whether the TLB reference is made by a virtual address or a real address.

When the instruction execution unit 1 refers to the TLB 3 by reading an instruction or reading an operand, for example, it sets the address register 11 and the R mode register 10 and issues a TLB reference request.

In this embodiment, the TLB 3 is set-associative 6, that is, it is addressed by a column address, and one or more entries selected by the column address are called a row. In this example, the number of columns is 512. TLB with 1 row and 51.2 entries in total
Although it is a composition.

The method of the present invention can be easily inferred for other configurations as well.

The address is a 31-bit address with bits 1-31. The column address is bits 11-1 of the address.
9. In the TLB 3, the column address section 24 of the address register 11 is decoded by the address decoder 14, and one entry to be referenced is selected.

Each entry in TLB3 is a valid field (V).

Guest field (G), real address field (R)
, a control field (C), a segment table origin field (STO), a virtual address field (VA), and an absolute address field (PA). In FIG. 1, the number of bits in each field is shown in parentheses.

(2) Field is a 1-bit field indicating whether the entry is valid or invalid. “1” when the entry is valid
When it is invalid, it becomes 11 Q It.

The C field indicates whether the entry is a host or guest VM.
This is a 1-bit field indicating which address translation information is included. The R field, which is "0" for the host and 111 It for the guest VM, is a 1-bit field that indicates whether the entry is referenced by a real address or a virtual address. When it is 11071, it indicates a reference by a real address, and when it is It l PI, it indicates a reference by a virtual address.

The C field is a 1-bit field indicating that the entry is address translation information using a common segment. In the host mode, this field becomes "1" when the common segment bit of the referenced segment table entry is 17111 in each of the host address translation and the guest VM mode in the guess 1 to address translation.

The STO field represents the segment table origin at the time of address translation of the entry.

In the I8M370/XA7 architecture, bits 1-25 of STO represent the address, and one field is 25.
It's bit.

The VA field is the bits other than the column address in the page frame address of the TLB reference, that is,
This is a 10-bit field that stores bits 1-10.

The PA field specifies the absolute address page frame.
Stores 19 bits of address part.

The TLB hit determination unit 4 includes comparison circuits 15 to 18, AND
Gate 20. It is composed of an OR gate 19 and a NOT gate 21. Comparison circuit 15 compares C field output 46 of TLB 3 and output 32 of G register 5, and outputs It 11+ when they match. Comparison circuit 15 generates TLB hit conditions specific to the VM system. That is, in the host mode (G mode register 5 is "o"), the C field 46 of the TLB entry read is l'Q 11,
Or guest VM mode (G mode register 5 is 11)
1 It ) and the C field 46 of the read TLB entry is "1", the condition for a TLB hit is met. OR
Gate 19 generates a T LB hit condition for the address space. That is, when the TLB entry is a common segment (the C field of the TLB is "1.'") or the STO value of the TLB entry matches the current STO output 44, the OR game 1-19 km "1" is output. . In addition, as the current STO output 44, the GSTO output is selected by the selector 22 corresponding to the G mode register 5.
Either output 36 or FSTO output 37 is selected. AND gate 20 generates TLB hit signal 56
is generated, and the TLB miss signal 5 is generated by the NOT gate 21.
7 is generated. T'LB hit signal 56 and TLB
PA field-output 51 is forwarded to the cache controller. The TLB miss signal 57 is transferred to the address translation section.

The TLB write control unit 2 controls TLB registration and invalidation of TLB entries by address translation. During TLB registration, the C field, R field, ST○ field, and VA field are each stored in G mode register 5.
, the R register 10, the select output 44 of ST○, and the values of the address register 11 are stored. Further, the C field and the PA field store values transferred from the address translation section. In addition, the ■ field contains the currently executing guest VM (7) VMID (ACT-VMID register 7) and the last executed guest VM VMID (
When the LSAST-VMID register 12) matches, the comparison circuit 13 becomes "1", and at that time, when the V register is 5'1", "1" is stored in the ■ field of the TLB 3.

When starting execution of the guest VM, the instruction execution unit 1 sets the G mode register 5 to "1", compares the ACT-VMID mode register 7 and the LAST-VMID register 12, and when they match, that is, the comparator circuit 13 When it is "1", the guest VM is immediately executed, and when there is a mismatch, that is, when the comparison circuit 13 is "0", the guest VM is executed after setting the V field of the guest entry of TLB3 to IKOI+.

When finishing the execution of the guest VM, the instruction execution unit 1 resets the G mode register 5 to “0” and changes the state of the CPU to S.
Restoring the state to the state at the time of execution of the IE instruction, and
M's VMID from ACT-VMIDL/Dystaf to LA
Store in ST-VMIDL/register 12. However, P.S.
The instruction address counter of W points to the next instruction after the SIE instruction. At this time, the guest entry in TLB3 is maintained as is.

With the above configuration, the guest entry in TLB3 contains the VMID of the newly executed VM and the VM ID of the previously executed VM.
It becomes possible to purge after detecting a mismatch of MIDs. Generally, a host management program has multiple guest Vs.
Manage M, issue SIE commands sequentially, and start guest VMs. As mentioned above, when dispatching from a host to a guest VM or from a guest VM to a host VM, all entries in the TLB are preserved. Therefore, when a certain guest VM is executed continuously after terminating the guest VM, unnecessary purging of guest entries in the TLB is prevented,
The activation of address translation in the guest VM can be suppressed to the minimum necessary number of times.

〔Effect of the invention〕

According to the present invention, in a virtual computer system, a guest VM identification information holding means is provided to enable identification of a guest VM started by an SIE instruction and a VM in a TLB guest VM entry. It is possible to eliminate unnecessary purging of TLB guest VM entries when the VMs in the TLB guest VM entries match, and improve the processing performance of the guest VM.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a part of the central processing unit of a virtual computer system particularly related to TLB and TLB reference in an embodiment of the present invention, and FIG. 2 is a diagram showing SIE commands and VM state descriptors. FIG. 3 is a diagram showing address conversion in the guest VM, and FIG. 4 is a diagram showing execution of the guest VM with an SIE instruction during host program execution. 1. Instruction execution unit; 2.・TLB write control unit 3
...TLB, 4...TLB hit determination unit 5...
・Guest mode register, 7...ACT-VMI
D register, 8...Guest mode register, 9.
...Host STO register 11...Address register, 12-LAST-VMIDL/register, 5
6...TLB hit signal, 57...TLB miss signal, 58...SIE command. 59... Main memory, 60... State descriptor. Figure 1 TLIII: "TL8"

Claims (1)

[Claims] (1) Equipped with a central processing unit and a main memory for supporting at least one guest virtual machine, storing a state descriptor of the guest virtual machine in the main memory, and receiving a guest virtual machine execution start instruction from the main memory. Specifying the state descriptor of the storage device, setting the central processing unit to the state indicated by the state descriptor, and starting execution of the guest virtual machine, the central processing unit sets the address of the host computer or guest virtual machine. In a virtual computer system that is equipped with an address translation buffer that holds translation information and is configured to refer to the address translation buffer while a host computer or a guest virtual machine is running, the identification information of a guest virtual machine is stored at least in the guest virtual machine. A method is provided to retain data from the end of execution of a computer until the start of execution of the next guest virtual machine, and when the execution of the guest virtual machine starts,
After comparing the retained guest virtual machine identification information with the identification information of the guest virtual machine that starts execution, and retaining or purging the guest entry in the address translation buffer according to the comparison result, A virtual machine system characterized by starting execution of a guest virtual machine.