JPS62222333A - Method and device for microprogram processing - Google Patents

Abstract

PURPOSE:To quickly process a composite instruction of complicated control with simple hardware by decomposing the composite instruction into single function instructions and distributing them to a microprogram sequence to execute them. CONSTITUTION:An address 11 is given from a program counter 1 to program memories 2 and 3. A selector 4 selects the instruction read memory 2 or 3 according as branch is executed or not. A register 5 takes in a selected instruction and delays it by one step. A controller 6 decodes the instruction taken into the register 5 and gives control indication to each part. An instruction 16 to be executed is the instruction of the address delayed in the register 5 by one step. Therefore, the instruction is an instruction I in the non-branch destination instruction memory if the address is N-1, and the instruction is an instruction II stored in the branch destination instruction memory if the address is N+3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram processing method and apparatus, and particularly to a microprogram processing method and apparatus suitable for processing complex instructions.

[Conventional technology]

Microprogram control methods have been influenced by larger memory capacities, lower memory prices, and advances in software.
Widely used for various processing and various controls. among them,
A conventional example will be explained using an example of a semiconductor logic integrated circuit testing apparatus that is considered to be most suitable for the present invention.

Semiconductor logic integrated circuits have various logic functions.

Test equipment is available to test these logical functions and characteristics.

The test equipment includes a test pattern generator that generates a test flat turn, a test signal generator that receives the pattern of the pattern generator and generates a test signal for a semiconductor logic integrated circuit, and a semiconductor integrated circuit that responds to the test signal. The test section receives a response signal from the circuit, checks and analyzes the response signal, and tests the semiconductor logic integrated circuit.

The main function of this test equipment is performed by a computer. The test turn generator generates turns according to the microprogram control method. Hereinafter, a conventional example will be explained in detail using a test turn generator as an example.

Figure 9 shows the principle of generation of the test pattern. test·
Setan Memory includes the tests required for the exam! Write down the turn. In the figure, the test turn consists of 7 bits. The repetition count memory contains the number in the corresponding address of the test/9 turn memory. Write down the number of consecutive turns. For example, for the test pattern '1011001' in the start address of the test lean memory, the number of repetitions in the same corresponding address in the repetition number memory is set to 'oooooooo'. Therefore, the number of repetitions is zero. Similarly, Tess) A? Turn ゝ01
00000 'Repeat count' 000010
1 ', the number of repetitions will be 5.

As described above, in testing semiconductor logic integrated circuits, it is often necessary to repeatedly generate the same test nine turns over several cycles.

In order to monitor the number of repetitions, a counter is provided, and the contents of the repetition number memory are read into this counter.
Each time it is repeated, it is decremented (-1), and the process is repeated until the contents of the counter become zero. This conventional example includes one described in Japanese Patent Publication No. 53-39729.

Furthermore, in response to the demand for higher functionality of test and turn generation, testing was conducted using a microprogram control method.
/J? Repeated turns and sashimi routines were implemented. This is from the literature (IEICE Technical Report, SSD 80-45,
1980 rLsI Memory Test Test Turn Generator", 4-zo 5-6). Figure 10 shows the above microphone C! A test pattern generator using Grodarum control method is shown.

Here, the repeated occurrence of the same pattern mentioned earlier is ``RE''.
This is done by a microinstruction called PEAT J. Program counter 1 is at address 1 for instruction memory 7.
1 and the microinstruction "rREPEAT 5 times" is read from the instruction memory 7, the controller (mainly hardware with a decoding function) 6 instructs the program counter l to hold with the control signal 14, and the counter 8 A control signal 18 instructs to load a repetition number of 20 times. After this, the controller 6 instructs the counter 8 to decrement by the control signal 18, and continues to hold the program counter 1 until the counter 8 outputs the zero detection signal 19, and executes the REPEAT command.

This REPEAT instruction is a type of compound instruction targeted by the present invention.

The test/nine turn memory 9 sends the test/nine turn, which is the content of the address indicated by the address 11, to the test signal generator 9A. The test signal generator 9A receives the test turn and creates a test signal corresponding to the test/four turns.

The semiconductor integrated circuit 9B receives this test signal, performs processing or response corresponding to the test signal, and sends the result to an inspection section (not shown). The test section compares the test signal and the response signal to test the functions of the integrated circuit 9B.

[Problem that the invention seeks to solve]

In the conventional example, there was a problem in processing complex instructions such as REPEAT instructions and LOOP instructions.

@11 As shown in the diagram, the content of control differs depending on the rREPEAT REPEAT command. That is, when executed for the first time, the PC (program counter) is instructed to hold, and the counter is instructed to load. From the second time onward, the PC is instructed to perform conditional control, and the counter is instructed to decrement. REPEA as above
The T command is a combination of two types of control contents, and when it is executed, the control unit needs to determine whether it is the first execution or not before determining the control contents. For this reason, the control section becomes extremely complex, and it becomes difficult to execute it at high speed.

As described above, the compound instruction targeted by the present invention has a plurality of control contents, and its contents are determined by its history.

Figure 12 shows REPIi: LOOP 5TART, which is a frequently used instruction like AT, and is another compound instruction.
Indicates a command. The operation of LOOP is that the LO
Load the number of times into the counter with OP 5TART and LO
At OP END, the counter is decremented, and if the counter is not 0, the process branches to LOOP 5TART again. From the second time onward, LOOP 5TART does not perform any control on the counter. LOOP END decrements the color and if it is zero, advances to the next address. In this way, the LOOP 5TART instruction is a complex instruction whose control contents differ depending on whether it is executed for the first time. Furthermore, LOOP instructions may be nested as shown in FIG. Therefore, the controller 6 shown in FIG. 10 has to memorize "first or not" for all LOOPs and make each determination every time the LOOP 5TART command is read, making it extremely complicated. I end up. Furthermore, it becomes difficult to increase the operating speed.

Although it is not suitable as a conventional example, there is a ``Give line system for microprogram controlled equipment'' described in Japanese Patent Laid-Open No. 59-128642, which is based on the same idea as the present invention. The purpose of this conventional example is to prevent dummy cycles that occur when speeding up with a mother ideal line configuration in a microprogram controlled device. In order to achieve this objective, when an instruction is stored in the microprogram memory, it is stored in a position that is one step ahead in accordance with the execution order, and is executed in a pipeline configuration.

The purpose of this conventional example is to prevent dummy cycles, and is not intended to simplify complex instructions as in the present invention.

There is no perspective on how to deal with complex commands. Furthermore, a circuit for identifying the number of instruction executions is required and the configuration is complicated. That is, when executing a compound instruction, the execution section must identify the number of times and change the control content accordingly, as in the prior art example, which complicates the configuration of the execution section.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprogram processing method and apparatus that enable high-speed execution of complex instructions with complex control using simple hardware.

[Means for solving problems]

The first invention is the REPEAT instruction and LOOP 5TAR
Compound instructions such as T instructions are broken down and treated as a chain of single-function instructions, each single-function instruction is distributed in a microprogram processing sequence, and then this distributed microprogram is sequentially processed. I made it run.

However, distribution means distributing and storing in the microprogram memory. Furthermore, in order to execute an instruction stored in the microprogram memory, instead of executing the read instruction as is, it is necessary to delay it one step and execute the instruction read at the address one step before. However, if the command is complex, the number of steps is not limited to one step, and generally one step is sufficient.

Furthermore, the second invention provides a non-branch target memory that stores non-branch target micro-instructions that are assigned the same address and a branch target memory that stores branch target micro-instructions, and stores a compound instruction in this memory. It is broken down into single-function instructions and stored separately. On the output side of these two memories, there is provided a selector for selecting one of the outputs, an ideal line register that takes in the output of the selector and delays it by a predetermined step, and a controller that decodes the microinstructions in the register. Ta.

[Effect]

In the first invention, microinstructions are read out one after another from a microprogram memory and executed, and in the case of compound instructions, single-function instructions are each read out and executed sequentially. This allows complex instructions to be executed easily.

In the second invention, the non-branch target memory and the branch target memory are accessed at an address specified by the program counter,
It was decided to read out the microinstructions, select one of them with a selector, then perform a predetermined step delay through a pipeline register, and output it to a controller for decoding. Compound instructions are broken down into single-function instructions and distributed and incorporated in non-branch target memory and branch target memory.
The above execution procedure is executed sequentially.

〔Example〕

FIG. 1 shows an embodiment of the test turn generator according to the present invention. This test turn generator consists of the following configuration.

Test/mother turn memory 9: Stores various tests/turns. This addressing is the same as the microprogram memories 2,3. test·! The contents of the turn are as shown in FIG.

Test signal generator 9A...Test/turn memory 9
receives the output test saturn and creates a corresponding test signal.

Semiconductor logic integrated circuit 9B: This is an integrated circuit to be tested, which takes in the output test signal from the test signal generator 9A and sends the response or result to an inspection section (not shown).

Delogram counter...Micro program memory 2
, 3 addresses are created. The address contains clock 1
There are two types of addresses: an address that is created by incrementing the count 7' (+1) every time a 5 is issued, and a branch address that is sent from line 20. In a normal microinstruction, +
1, and replaces the branch address at the time of a branch microinstruction and when the branch condition is met.

However, branch addresses are not used in microinstructions that are decomposed from compound instructions.

Microprogram memory 2.3...Memory 2 stores microinstructions that do not have a branch destination, and memory 3 stores microinstructions that have a branch destination. Both memories 2 and 3 have the same address, and program counter 1
is accessed by the output address 11 of , and the microinstruction within that address is read.

Selector 4: The selector 4 selects and takes in either the read microinstruction 12 of the memory 2 or the read microinstruction 13 of the memory 3. The selection is made by the selection signal 21 of the controller 6.

・! Ideline renostar 5: Latch the read microinstruction selected by the selector 4 and delay it by l steps. Furthermore, no! The ideal line register 5 generates a branch address 20.

Controller 6...The controller 6 is a kind of decoder, /!
Decoding microinstructions from Eveline Renosta. As a result of the decoding, various control signals are generated depending on the contents of the microinstruction. Among the control signals, one of the control signals related to the operation of the embodiment is a selection signal 21. The other one is a control signal 14 that causes the contents of the program counter 1 to be held. In addition, it generates various control signals.

FIG. 2 is an explanatory diagram of allocation of micro instructions to the micro program memories 2 and 3. 81 in FIG. 2 is an example of storing the execution procedure of a certain microprogram, and the address ``81'' is
"N-2" has "instruction A", "N-1" has [instruction Bj, rN
"Compound command" for J.

"Instruction CJ" was stored in "N+1", "conditional branch instruction D" was stored in rN+2J, and "instruction E" was stored in "N+3".

The execution procedure of this microprogram is shown at 82 in FIG. Execution progresses from instruction A → instruction B → compound instruction → instruction C → conditional branch instruction, and depending on the contents of the conditional branch instruction (depending on whether the branch condition is met or not), it returns to the compound instruction or executes instruction E. Move to one of the following.

Here, it is assumed that the compound instruction is composed of a single-function instruction and a single-function instruction (2). Therefore, microinstructions are allocated as shown at 83 in FIG. A non-branch target instruction memory 2 and a branch target memory 3 constitute a microprogram memory that stores micro instructions.

The non-branch destination instruction memory 2 stores non-branch destination instructions, that is, microinstructions that do not correspond to branch destinations.

Single-function command workers belong to this type.

The branch destination instruction memory 3 stores branch destination instructions, that is, microinstructions corresponding to the branch destination. Single-function instructions ■ belong to this type.

The two memories 2, 3 are addressed identically.

Furthermore, each instruction is stored one step earlier than 81 in FIG.

FIG. 3 is an explanatory diagram of an example of the allocation of microinstructions. In order to allocate the contents of the left microprogram memory to the right microprogram memories 2 and 3, advance storage editing is performed. In this case, if the microprogram is as shown in the execution order example, advance storage editing is performed as shown in the figure. As a result, microinstructions are allocated to the memories 2 and 3 as shown on the right.

It will be explained in further detail.

A compound instruction is a combination of an instruction and ■.When proceeding from the previous address (N-1), execute the instruction, and when proceeding by branching from another address, execute the instruction ■. shall be taken as a thing. Now, when the execution order is as shown at 82 in Figure 2, one step before address N-1 is N-2, and one step before address N there are two possibilities, N-1 and N+2. Yes, one step before address N+1 is N,
One step before address N+2 is N+1. Therefore, the storage location of each instruction is not at the address originally corresponding to 81 in FIG. 2, but at the location where the order of 82 in FIG. 2 is reversed by one step, that is, the compound instruction corresponding to address N is stored at address N-1. It will be stored at address N+2. The storage position thus constructed is shown at 83 in FIG. In the figure, there are two non-branch destination instruction memories 2 and branch destination instruction memories 3 because they are conditional branch instructions.

In Sl, the conditional branch instruction is 1 at address N+2, and S
As shown in FIG. 2, there are two types of branching: one branching from N+2 to N and the other branching to N+3. Therefore, by advancing the instruction storage position by one step, two instructions will be stored at sea address N+2: the instruction corresponding to the branch destination address N, and the instruction corresponding to the subsequent address N+3. Two types of memory, non-branch destination instruction memory and branch destination instruction memory, are provided corresponding to such conditional branch instructions.

As described above, in order to execute the instruction stored in the preceding position, it is sufficient to delay the read instruction by one step and then execute it. Since the storage position of the instruction is advanced by one step, it is natural that the correct instruction can be obtained by delaying the instruction by one step after reading.

The embodiment of FIG. 1 will be described assuming that microinstructions such as 83 in FIG. 2 are stored in the microprogram memories 2 and 3.

From program counter l to micro program memory 2
, 3 is given address 11. The selector 4 selects from which of the non-branch destination instruction memory 2 and the branch destination instruction memory 3 an instruction is to be read, depending on whether or not a branch is to be executed.・
The arm ideal line register 5 delays the instruction by one step by taking the instruction selected for reading. The controller 6 interprets the instructions taken into the mother Eveline register 5 and gives necessary control instructions to each part. If configured like this,
The command 16 interpreted and executed by the controller 6 is delayed by one step by the guideline restarter 5. Therefore, when program counter 1 is outputting N as an address, the instruction output from pipeline register 5 is 1.
This is the one read before the step. If the address one step before this was N-1, the output of the no-blank register 5 is the instruction stored at address N-1 in the non-branch destination instruction memory. Yes, and if the address one step before was N+3, then this is the instruction ■ stored at address N+2 in the branch destination instruction memory.

As described above, by replacing the complex instruction stored in the preceding position with an instruction of a simple function according to the storage position, it becomes possible to execute the complex function even if the control unit makes a complicated judgment.

Hereinafter, the specific operation of the present invention will be explained in detail using the REPEAT command as an example with reference to FIGS. 4 and 5.

Pl in FIG. 4 shows an example of a program including a REPEAT instruction, and it is assumed that instructions A and B are instructions that do not cause a branch. At this time, instruction A is executed at address N-1, then address N is repeated several times by the REP EAT instruction at address N, and then the process advances to address N+1 and instruction B is executed. Reversing this order, one step before address N-1 is address N-2, one step before address N is address N-1 and address N itself (by repeating itself), One step before address N+1 is address N. Therefore, if these instructions are stored in the preceding position, the result will be K as shown in P2 in FIG. Here, the REPEAT instruction, which is a compound instruction stored at address N-1, is a single-function REPEAT instruction that has the function of the first execution shown in FIG.
REPEA replaced with L instruction and stored at address N
The T instruction is replaced with a single-function REPEAT n instruction having the functions shown in FIG. 11 from the second execution onward. FIG. 5 shows how the instructions that have been pre-stored and replaced in this way are executed in the configuration shown in FIG. When program counter 1 is outputting address N-2 in step E of FIG. 5, instruction A is read from the previously stored non-branch instruction memory. At the next step I+1, the output of the program counter I becomes N-1, and REPEAT I is read from the non-branch target instruction memory. Further, the instruction A read earlier is taken into the mother Eveline resolver 5. Since the instruction A is a non-branching instruction, the controller 6 instructs the program counter 1 to p+1 using the control signal 14. At the next step I+2, the glogram counter 1 outputs N. The previously read REPEAT n instruction is taken into the /'P ideal line register 5. As a result, the controller 6 instructs the program counter 1 and the repetition counter (not shown) to control the first time of the REPEAT command. In this step, instruction B is read from the non-branch destination instruction memory previously stored at address N, and the REPEAT In instruction is read from the branch destination instruction memory. The controller 6 instructs the selector 4 to select the output 13 of the branch destination instruction memory in order to perform repetition by the REPEAT I command output from the 4-line register. At the next step I+3, the program counter 1 outputs the address N again, and the noquiline restarter 5 takes in the REPEAT In instruction read from the branch destination instruction memory 3. The controller 6 interprets the RF:PEAT In command and instructs each unit on the control contents for the second and subsequent REPEAT commands shown in FIG. If the repetition counter (not shown) is zero, the repetition is repeated and the selection signal 21 instructs the selector 4 to select the output 13 of the branch destination instruction memory. If the repetition counter (not shown) becomes zero in the next step I+4, the controller 6 instructs the gramogram counter 1 to increment by 1 using the control signal 14, and the selector 4 receives the selection signal 21. Instructs to select output 2 of the non-branch destination instruction memory. Then, at the next step I+5, the output of the glogram counter 1 becomes N+1, and the instruction B is taken into the I-line register 5, and the command is output from REPEAT.

As described above, according to this embodiment, the number of executions is conventionally stored, and based on the judgment, i) REPEAT, which is a compound instruction that had two types of control contents, is divided into two simple instructions, REPEAT I and REPEAT IF. It can be broken down into functional commands and executed, and as a result, the controller does not need to make any judgments, allowing a simple controller configuration without sacrificing functionality. Earlier, the LOOPSTART instruction was also explained as a compound instruction.

By pre-storing this instruction as shown in Ql and Q2 in Fig. 6, the LOOP 5TABT n instruction with the first function shown in Fig. 12 and the LOOP 5TART In instruction with the second and subsequent functions are created. It can be decomposed into

Further, according to the present invention, it is possible not only to simplify the conventional instructions described above, but also to easily realize complex instructions having complex functions that were previously unimaginable.

FIG. 7 shows an example of the execution of the NSC instruction, which is a new compound instruction. Here, the NSC instruction is a NOP/subroutine combination instruction (NOP/5UBROUTI).
NE COMBINATION instruction) and 1
When proceeding from the previous address, it acts as a NOP instruction and proceeds to the next address. Furthermore, when a branch is proceeded from another address, this is an instruction to perform a subroutine branch to another address as a 5UBROUTINE instruction. The execution order of R1 in FIG. 7 is N-3→N-2
->N-1-+N (NOP operation) ->N+1 ->N+2 (branch to N) ->N (subroutine to N+4) ->N+4 When advance storage is performed, the result will be as shown in R2 in FIG. 7. Here, the NOP function of the NSC instruction is stored as a NOP instruction in the non-branch destination instruction memory at address N-1, and
The ROUT I NE function is stored in the branch destination instruction memory at address N+4 as a 5UBROUTINE instruction.

Figure 8 shows how this program is executed by the device shown in Figure 1.
As shown in the figure.

As described above, according to the present invention, it is possible to easily execute compound instructions, which were conventionally considered to be complex and difficult to control, thereby speeding up the operation. As a comparison, in the past, it was necessary to memorize the execution history of each loop nesting shown in FIG. Just run it as is.

Further, in the present embodiment, the explanation has been made assuming that the command is preceded by one step, but if the command is stored in a position that is one step ahead, even more complicated control becomes possible.

〔Effect of the invention〕

According to the present invention, a compound instruction with a complex function can be converted into a simple -
- It has the effect of being able to be executed at high speed with software.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of microinstruction allocation in this embodiment, FIG. 3 is a diagram showing an example of its creation procedure, and FIG. A diagram explaining an example of allocation, FIG. 5 is a processing time chart,
FIG. 6 is a diagram illustrating an example of allocation using the LOOP command,
Fig. 7 is a diagram explaining an example of allocation using another NSC instruction, Fig. 8 is a processing time chart, Fig. 9 is a diagram showing the conventional test/flat turn concept, and Fig. 1O is a diagram illustrating the conventional test/flat turn concept. The diagrams showing the configuration, FIG. 11, FIG. 12, and FIG. 13 are diagrams for explaining the processing of the conventional example. l...Program counter, 2...Non-branch destination instruction memory, 3...Branch destination instruction memory, 4...Selector, 5
・・・No2 Ideale Reno Star, 6... Controller, 9.
...Test turn memory, 9A...Test signal generator, 9B...Logic integrated circuit. Agent Patent attorney Tadashi Akimoto Actual tower 1 figure rate 2 Figure a@+benkima I tento tower 3 Figure tower 4. Figure 57 6 Figure 7 Figure 8 Figure Selection I Angzy
・・・---・Test 9th area Test patuso inspection 10th area Figure 11

Claims (1)

[Claims] 1. A complex microinstruction forming a microprogram is decomposed into single-function microinstructions and stored in a microprogram memory together with other microinstructions, and the microprogram memory is used to store the contents of a program counter. A microprogram processing method that accesses and reads according to a value, and decodes and executes the read microinstruction. 2. The program counter is assigned the same address, stores non-branch target micro-instructions and branch-destination micro-instructions among the micro-instructions that make up the microprogram, and stores complex micro-instructions among the micro-instructions. A microprogram memory consisting of a microprogram memory for non-branch destinations and a microprogram memory for branch destinations in which instructions are divided into single-function microinstructions and stored separately for either non-branch destinations or branch destinations; a selector for selecting either one of the microinstructions read when the non-branch destination microprogram memory and the branch destination microprogram memory of the program memory are accessed according to the content value of the program counter; A microprogram processing device comprising a pipeline register that latches and outputs a microinstruction after a predetermined delay, and a controller that decodes the microinstruction output from the pipeline register and outputs a control output.