JPS62219989A - Manufacture of semiconductor light emitting device - Google Patents

Manufacture of semiconductor light emitting device

Info

Publication number
JPS62219989A
JPS62219989A JP6291186A JP6291186A JPS62219989A JP S62219989 A JPS62219989 A JP S62219989A JP 6291186 A JP6291186 A JP 6291186A JP 6291186 A JP6291186 A JP 6291186A JP S62219989 A JPS62219989 A JP S62219989A
Authority
JP
Japan
Prior art keywords
layer
high resistance
inp
grown
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6291186A
Other languages
Japanese (ja)
Inventor
Mitsuru Sugawara
充 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6291186A priority Critical patent/JPS62219989A/en
Publication of JPS62219989A publication Critical patent/JPS62219989A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To sufficiently suppress leakage current that does not pass an active layer and obtain a laser with a low threshold, a high efficiency and a large output by forming a high resistance layer below the sides of the active layer. CONSTITUTION:A high resistance InP layer 2 is grown on a first conductivity type semiconductor, for example, an N<+>-InP substrate 1. A stripe mask 3 made of SiO2 is formed thereon and the high resistance layer of a light emitting portion forming region is partially removed by etching. Then, after the SiO2 mask 3 is removed, the first conductivity type N-InP layer 4 is grown flat so as to embed the whole high resistance layer and further an InGaAsP active layer 5 and a second conductivity type P-InP layer 6 are continuously grown. The SiO2 stripe mask is formed above a portion wherein the high resistance layer is absent and an etching is applied in a mesa configuration until the high resistance layer is reached. Then, both sides of the mesa thus formed are embedded with an N-type InP layer 8 and further, after the SiO2 mask is removed, a P-type InP layer 9 is grown so that an upper surface becomes flat. Thus, a laser with a low threshold, a high efficiency and a large output power is obtained.

Description

【発明の詳細な説明】 〔概 要〕 本発明は、活性層の側部下方に高抵抗層を形成すること
Kより活゛性層を通らない漏れ電流を十分に抑制し、低
しぎい値、高効率、高出力のレーザな得るも□のである
。□ 〔産業上の利用分野〕 本発明は半導体発光装置の製造方法に係り、特に低しき
い値電□流、高出力、高効率の半導体レーザが得られる
方法に@する。
[Detailed Description of the Invention] [Summary] The present invention is capable of sufficiently suppressing leakage current that does not pass through the active layer by forming a high resistance layer below the side of the active layer, and achieving a low threshold value. It is also possible to obtain a high-efficiency, high-output laser. □ [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor light emitting device, and is particularly directed to a method for obtaining a semiconductor laser with a low threshold current, high output, and high efficiency.

〔従来の技術及び発明が解決しようとする問題点〕高出
力、高効率の動作をする埋込み型半導体レーザとして、
第2−のような構造のものが報告されている。この構造
の場合、活性層への電流閉じ込めは、ストライプ状の活
性層[部を埋込んだ部分に形成されるp−n接合(矢印
)によって行われている・しかしながら、このp−n接
合は、ある印加電圧以上で急激に大きな電流が流れるた
めに、電流閉じ込め層としての効率が著しく低下してし
まう欠点を有していた。
[Problems to be solved by the prior art and the invention] As an embedded semiconductor laser that operates with high output and high efficiency,
A structure similar to No. 2 has been reported. In this structure, current confinement in the active layer is achieved by a p-n junction (arrow) formed in the striped part of the active layer.However, this p-n junction However, since a large current suddenly flows when the applied voltage exceeds a certain level, the efficiency as a current confinement layer decreases significantly.

本発明は、埋込み型半導体レーザに対して活性層を通ら
ない漏れ電流を昼印加電圧まで十分圧抑制し、低しきい
値電流、高出力、高効率の半導体レーザを提供するもの
である。
The present invention provides a buried semiconductor laser with a low threshold current, high output, and high efficiency by sufficiently suppressing leakage current that does not pass through the active layer up to the daytime applied voltage.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によれば、上述の問題は、第1導電型の半導体基
体上に発光部形成領域にストライプ状の溝が形成された
高抵抗半導体層と、これを埋める第1導電型の第1の半
導体層を形成した後、活性層及び第2導電型の第2の半
導体層を成長させ、前記高抵抗半導体層が形成された領
域の第2の半導体層、活性j−及び第1の半導体層を該
高抵抗半導体層に達するまで部分的にエツチング除去し
てストライプ状に形成し、該ストライプ状の第1の半導
体層及び活性層の側面並びに核高抵抗半導体層上に第1
4電型の第4の半導体層な形成することにより解決され
る。
According to the present invention, the above-mentioned problem can be solved by using a high-resistance semiconductor layer in which a stripe-shaped groove is formed in a light emitting part formation region on a semiconductor substrate of a first conductivity type, and a first conductivity type semiconductor layer that fills the stripe-like groove. After forming the semiconductor layer, an active layer and a second conductivity type second semiconductor layer are grown, and the second semiconductor layer, active j- and first semiconductor layer in the region where the high resistance semiconductor layer is formed are grown. is partially etched away until it reaches the high-resistance semiconductor layer to form a stripe shape, and the first semiconductor layer is etched on the side surfaces of the stripe-shaped first semiconductor layer and the active layer and on the core high-resistance semiconductor layer.
This problem can be solved by forming a fourth semiconductor layer of 4-electrode type.

〔作用〕[Effect]

本発明は、活性層の下部両側VCC低抵抗層形成するこ
とによって、従来のp−r1合による′tL流閉じ込め
と比較して非常に高い印加電圧まで漏れ電流を十分に抑
制し、低しきい値電流、窩出カ。
By forming VCC low resistance layers on both sides of the lower part of the active layer, the present invention can sufficiently suppress leakage current up to a very high applied voltage and achieve a low threshold compared to the conventional 'tL current confinement by p-r1 coupling. Value current, fossa output power.

高効率の半導体レーザが得られるようにしたものである
This makes it possible to obtain a highly efficient semiconductor laser.

〔実施例〕〔Example〕

第1図は本発明一実施例の製造方法を説明するための工
程断面図である。以下、図面を参照しつつ、本発明一実
施例を説明する。
FIG. 1 is a process sectional view for explaining a manufacturing method according to an embodiment of the present invention. Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

n”−InP基板1上に、LPE法によってFeドープ
高抵抗InP層21に約3μm成長させる。この上に、
<011>方向IC3μm幅の5io2カらなるストラ
イプマスク3を第1図aのように形成し、エツチングに
よって発光部形成領域の高抵抗層を部分的に除去する。
On the n''-InP substrate 1, an Fe-doped high-resistance InP layer 21 of about 3 μm is grown by the LPE method.
A stripe mask 3 made of 5io2 having a width of 3 μm in the <011> direction is formed as shown in FIG. 1A, and the high resistance layer in the light emitting part forming region is partially removed by etching.

次に5to2マスク3を除去した懐、第1図すのよ5−
K n −InPn種層に1高抵抗層をすべて埋めるよ
うに平坦に成長させ、さらK例えば厚さ0.5μmのI
nGaAsP活性層5.厚さ3μmのP−InP層6を
連続成長させる(尚、n−InP層上に回折格子を形成
し、活性層とn−InP層の間に光ガイド層を設けるこ
とによってDFBレーザとすることもできる)。その後
第1図Cのように、高抵抗層のない部分の上部に(01
1>方向に5μm@のSiO2ストライプマスク7を形
成し、高抵抗層に達するまでBrz : CHsOHm
液でメサ状にエツチングする。そして、このメサの両側
を第1図dのよ5 K n型InP層8で埋め込み、さ
らにSi0gマスクを取り除いた後、P形InP層を上
部が平坦になるように成長させる。これに、n型にA 
u −S n hP側KAu−Zn−Auで電極をとり
、共損器長300μmのレーザ素子を作成する。
Next, the pocket with 5to2 mask 3 removed, Figure 1 Sunoyo 5-
The K n -InPn seed layer is grown flat so as to fill the entire high resistance layer, and then the K n -InPn seed layer is grown flat to fill the whole high resistance layer, and then the K n -InPn seed layer is grown flat, for example, with a thickness of 0.5 μm.
nGaAsP active layer5. A P-InP layer 6 with a thickness of 3 μm is continuously grown (a DFB laser can be obtained by forming a diffraction grating on the n-InP layer and providing an optical guide layer between the active layer and the n-InP layer). can also be done). After that, as shown in Figure 1C, (01
1> Form a 5 μm @ SiO2 stripe mask 7 in the direction, and apply Brz: CHsOHm until reaching the high resistance layer.
Etch it into a mesa shape with liquid. Then, both sides of this mesa are filled with a 5 K n-type InP layer 8 as shown in FIG. In addition, A to n type
An electrode is made of KAu-Zn-Au on the u-S n hP side, and a laser element with a co-loss device length of 300 μm is created.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、活性層両側下部に高抵抗層を形成する
ことによって活性層を通らない漏れ電流を十分に抑制で
きるので、低しきい値、高効率。
According to the present invention, leakage current that does not pass through the active layer can be sufficiently suppressed by forming high-resistance layers below both sides of the active layer, resulting in a low threshold value and high efficiency.

高出力のレーザが得られる効果がある。This has the effect of producing a high-power laser.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明一実施例を説明するための工程断面図、
第2図は従来例を説明するための断面図である。 図において、lはn”−InP基板、2はInP高抵抗
層、3,7はSing マスク、4はn−InP層。 5はInGaAsP層、6はP −InP層、8はn−
InP層、9はp−InP層である。 ゝ−、/
FIG. 1 is a process sectional view for explaining one embodiment of the present invention,
FIG. 2 is a sectional view for explaining a conventional example. In the figure, l is an n''-InP substrate, 2 is an InP high resistance layer, 3 and 7 are Sing masks, 4 is an n-InP layer, 5 is an InGaAsP layer, 6 is a P-InP layer, and 8 is an n-
The InP layer 9 is a p-InP layer.ゝ-,/

Claims (1)

【特許請求の範囲】[Claims] 第1導電型の半導体基体上に発光部形成領域にストライ
プ状の溝が形成された高抵抗半導体層と、これを埋める
第1導電型の第1の半導体層を形成した後、活性層及び
第2導電型の第2の半導体層を成長させ、前記高抵抗半
導体層が形成された領域の第2の半導体層、活性層及び
第1の半導体層を該高抵抗半導体層に達するまで部分的
にエッチング除去してストライプ状に形成し、該ストラ
イプ状の第1の半導体層及び活性層の側面並びに該高抵
抗半導体層上に第1導電型の第4の半導体層を形成する
ことを特徴とする半導体発光装置の製造方法。
After forming a high-resistance semiconductor layer in which a striped groove is formed in a light emitting part formation region on a semiconductor substrate of a first conductivity type and a first semiconductor layer of a first conductivity type to fill this layer, an active layer and a first semiconductor layer of a first conductivity type are formed. A second semiconductor layer of two conductivity type is grown, and the second semiconductor layer, the active layer, and the first semiconductor layer in the region where the high resistance semiconductor layer is formed are partially grown until reaching the high resistance semiconductor layer. A fourth semiconductor layer of the first conductivity type is formed on the side surfaces of the striped first semiconductor layer and the active layer and on the high resistance semiconductor layer. A method for manufacturing a semiconductor light emitting device.
JP6291186A 1986-03-20 1986-03-20 Manufacture of semiconductor light emitting device Pending JPS62219989A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6291186A JPS62219989A (en) 1986-03-20 1986-03-20 Manufacture of semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6291186A JPS62219989A (en) 1986-03-20 1986-03-20 Manufacture of semiconductor light emitting device

Publications (1)

Publication Number Publication Date
JPS62219989A true JPS62219989A (en) 1987-09-28

Family

ID=13213910

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6291186A Pending JPS62219989A (en) 1986-03-20 1986-03-20 Manufacture of semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPS62219989A (en)

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