JPS62219835A - Interference compensation circuit - Google Patents

Abstract

PURPOSE:To miniaturize a compensation circuit by using an output of an integration device relating to the common mode component so as to control the amplitude adjustment of an adjustment circuit and controlling the phase adjustment of the adjustment circuit by an output of the integration device relating to the orthogonal component thereby using one phase detector to retrieve an interference signal. CONSTITUTION:A reception main signal from a main antenna 1 passes through a band pass filter 2 to improve the S/N and is converted into the If band by a frequency converter 3. Then an interference signal from an auxiliary antenna 4 for source signal reception of the interference component included in the main signal is given to a band pass filter 5, a local oscillator 7 in common use with the main signal and converted into the IF band by a fre quency converter 6. The phase and amplitude of the IF signal are adjusted and added (11) with the interference component in the main signal in opposite phase to cancel the interference component in the main signal. Further, the interference signal is branched by a variable phase circuit 8, phase detection is applied by a phase detector 23 by using a reference carrier 20 recovered by a main signal demodulator, operation is applied to the detector output after through a harmonic rejection filter 25 and the result is given to integration circuits 32, 33. Thus, DELTAgamma of a variable amplitude circuit 10 and DELTAtheta of a variable phase circuit 9 are controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the configuration of an interference compensation circuit that eliminates interference from other systems that a digital signal receives in a digital communication system.

(Conventional Circuit) An example of the configuration of a conventional interference compensation circuit (for example, Patent Application No. 6O-2
87881) is shown in FIG. Below, FIG. 4 will be explained. The main signal (here, a digital signal is considered) received from the main antenna 1 for main signal reception is subject to interference from other systems.

The signal passes through a bandpass filter 2 as required, and then is frequency-converted to a pIF band by a receiver 3.

On the other hand, in order to receive the signal that is a source of interference using the auxiliary antenna 4 and improve its s, /Ni as necessary, the signal is passed through a bandpass filter 5, and then a local oscillator 7 that is common to the main signal receiver is used. Then, the frequency is converted to the IP band by the receiver 6. A circuit 8 for varying the phase and amplitude of the interference signal;
10, and the interference component leaked into the main signal and the opposite phase 2
The interference component is canceled by adding the signals with equal amplitude by the adder 11. The variable phase circuit 8 and variable amplitude circuit 1
In order to control 0, first, after addition in the adder 11, the added signal is passed through a demodulator in order to detect the in-phase and quadrature components of the remaining interference components. In the demodulator, the regenerated reference carrier wave 20 is detected by the quadrature phase coherent detection circuit 12.13, and the in-phase component (output of 13) and quadrature component (output of 12
(output) all done. Those signals are filtered by harmonic removal filter 1
After passing through 4°15, the signal is passed through error signal generation circuits 102 and 103 for detecting residual interference components to obtain in-phase and quadrature error signals. On the other hand, the interference signal is divided into two parts after passing through a variable phase circuit, one of which is divided into two by quadrature phase detectors 22 and 2 to decompose the interference signal into an in-phase component and a quadrature component.
Enter 3. Here, the local oscillator used is the same as the main signal demodulator. The interference signal divided into in-phase and quadrature components is filtered through harmonic removal filters 24 and 25.
After passing through the identification circuits 27 and 28' using the timing signal of the main signal demodulator, the signal is binarized. This identification circuit will be necessary later in the case where digital processing is performed, but this circuit is not required when analog processing is performed. If the output of the error signal generation circuit is to be output as a digital signal, a digital converter may be used. That is, for example, when the main signal is a 16 QAM signal, the demodulated signal is not a 4-value signal, but has an output of 3 bits or more, so if it is sampled with a converter, the upper 2 bits will be identified as shown in Figure 5. A binary signal representing the result is obtained, with the third most significant bit representing the direction of the error. and,
A correlation is established between the identification results of the error signal of the in-phase and quadrature components and the interference signal of the in-phase and quadrature components.

That is, a signal obtained by exclusive ORing (EX-OR) 29.30 of the in-phase components or orthogonal components is passed through the integrator 38 to be used as a control signal for the variable amplitude circuit.

In addition, exclusive OR (EX-OR) 31, exclusive inverted OR (EX-OR) of in-phase and orthogonal components or orthogonal and in-phase components
-NOR) 32 is passed through an integrator 37 to be used as a control signal for the variable phase circuit.

(Problems to be Solved by the Invention) As explained above, conventional interference compensation circuits require a quadrature phase detector to detect interference signals as an external additional circuit, which increases the circuit size. It had the problem of becoming.

An object of the present invention is to use a phase detector instead of a quadrature phase detector to detect interference signals, thereby simplifying external additional circuits and realizing a simple interference compensation circuit.

(Means for Solving the Problems) The features of the present invention for achieving the above object include a main antenna for receiving a main signal, an interference signal receiving means, and a phase and amplitude of the output of the interference signal receiving means. an adjustment circuit that adjusts the relative relationship with the output of the main antenna; a synthesis circuit that synthesizes the outputs of the main antenna and interference signal receiving means adjusted by the circuit; and a reference that is reproduced from the output of the synthesis circuit and the main signal. A quadrature phase synchronized detector that decomposes a carrier wave into an in-phase component and a quadrature component as a total carrier input, two error signal generation circuits each receiving the in-phase component and quadrature component as input, and a signal generator coupled to the adjustment circuit and outputting a signal from the circuit. In contrast, a phase detector that performs multiphase detection using the same reference carrier as the orthogonal phase synchronized detector, and a correlation between the output of the phase detector and the output of the two error signal generation circuits are independently provided. comprising two multipliers and two integrators respectively connected to the outputs of the multipliers, the output of one of the integrators relating to the in-phase component controls the amplitude adjustment of the adjustment circuit; The interference compensation circuit controls the phase adjustment of the adjustment circuit by the output of the other integrator, which is related to the quadrature component.

(Example) An example of the present invention is shown in FIG. FIG. 1 will be explained in detail below. The main signal received from main antenna 1 is S
/N 1, if necessary, use a bandpass filter 2'f! I: After passing through, it is converted into the E-F band by the frequency converter 3. On the other hand, the interference signal received from the auxiliary antenna 4 for receiving the source signal of the interference component included in the main signal is S/
In order to improve 'N'e, after passing through a band pass filter 5 as necessary, the signal is converted into an IF band by a frequency converter 6 using a local oscillator 7 common to the main signal side. The interference component in the main signal can be eliminated by adjusting the phase and amplitude of the IF multiplied signal and adding 11 the same amplitude and opposite phase to the interference component in the main signal.

A quantitative explanation will be given below. The main signal is a 16 QAM signal,
It is assumed that the interference signal is an amplitude modulated wave. The main signal converted to the IF band can be expressed by the following equation.

Here, ak t bk= (±1.±3) prf is the in/out response of the entire system, T is the clock period, and ω is the carrier wave angular frequency of the main signal. At) is the amplitude component of the interference component, and since it is expressed in polar coordinates, it is f(t))O.

ω2 represents the angular frequency of the interference component, and θ represents the phase. on the other hand,
When the other input signal of the adder 11 is normally controlled, it is expressed by the following equation.

Y2(t)=(J'(t)+Δγ), ej(o)2
t+e+le+*) (2゜However, Δr, Δ
θ can be considered to be a sufficiently small value. Formula (1) and formula (2
) The result of the full addition is sent to the main signal demodulator 1. Quadrature phase synchronous detection (12, 13) is performed at OO, and harmonic removal filter 14
, 15t-, the in-phase and quadrature components are expressed by the following equations.

i, (t)=Σak-r(t-kT)+[-Δr-ca
! 1 (Δω to 10) ten t) fist Δθ・*(Δωt+θ
)]q 1(t)=Σbk・r(t-kT)+[knee Δ
r-picture (Δωt + θ) -7tt)・Δθ・Residence (Δω to 10) ) (4) Here, Δω
represents the difference between ω and ω2.

These four-level demodulated signals are input to an error signal generation circuit 102 #103 that detects residual interference components. As the error signal generation circuit, a converter having an output of 3 bits or more is usually used. As shown in FIG. 5, when a four-value signal is input, the upper two bits of the output indicate the identification result. Also, the upper 3rd bit is the shift direction of the signal point,
In other words, it represents the direction of the error. Therefore, the error signal can be extracted from the third most significant bit. The in-phase and quadrature component error signals are expressed by the following equations.

E guy 1) = -Δγ・person (ΔωL 10) 10 ft)・Δθ・
Spider (Δωt + θ) (5) E4t) = -Δγ・th(Δω
10) - fCt)・Δθ・(2) (Δω10) (6
) Also, the interference signal is multi-branched into 8, multiphase detection is performed on 23 using the reference carrier wave 20 regenerated by the main signal demodulator, and the output of the detector after passing through the harmonic removal filter 25 is given by the following formula. Become.

i2(t)=X−fCt)・Cxl5(Δω is 1θ′+
Δθ+π) keyed fct)・! (Δω is 10')
(7) Here, K is the gain of the variable amplitude circuit, θ
' represents the phase.

In order to detect the correlation between the error signal expressed by equations (5) and (6) and the interference signal expressed by equation (7), 30
By zz(t) X Ez(ri and 31 by j2
(t) x E4t) and integrates the circuit 32.
33, the following equation is obtained.

s 2(t)X Eilt)→f(t)−Δr'cos
(θ−θtsu (8)i〆t)XE4t)→f
2Ct)・Δθ(θ−θ') (9) Here, θ and θ' are the initial phases, and there is almost no need to consider their fluctuations, so if you initialize them so that θ = θ', From equation (8), Δr2 of variable amplitude circuit 10 equation (9)
However, it is possible to control Δθ of the variable phase circuit 9.

Next, another embodiment of the present invention is shown in FIG. The difference from FIG. 1 is that the output of the error signal generating circuit and the phase-detected interference signal are binarized and the correlation is detected digitally. For the detection output expressed by equation (3) and equation (4),
As a result of identification using the timing signal 22 regenerated by the demodulator, the error signal is expressed by the following formula % On the other hand, when the interference signal expressed by equation (7) is identified using the timing signal 22 regenerated by the main signal demodulator It is expressed by the following formula.

sgn (i2 (mT)) = -sgn (ccs (∆ω = 1θ')) (6) In order to take the correlation between αQ, α and equation (b), dizotal multiplication, that is, exclusive The following equation is obtained by taking the logical sum 30.31 and passing it through the integrator 32.33.

sgn(j2(mT乃X sgn(E<(mT))→-
sgn(-Δγ・■(θ−θ') + f(t)・Δ
θ・in (θ−θ′)) (6) sgn(i2(mT)
)
α◆Here, if we set θ−〇′ as before, then 2α1
The equation 2 α→ becomes the following equation.

sgn(j2(mT)) X sgn(E7(mT))
→sgn(Δγ)cLysgn(i2(mTnoX ag
n(E, (mT)) −+ sgn(Δθ) α4 Therefore, the amplitude of the variable amplitude circuit 10 is expressed as follows.

In addition, the phase of the variable phase circuit 8 can be controlled by formula α. I dedicate it to you.

Here, in order to apply Equations (8), (9), Equations (8), and (α), both the interference component leaked into the main signal and the interference signal received from the auxiliary antenna are shown in Figure 1 or 2.
It is necessary to adjust the absolute delay time immediately before the synthesizer 11 shown in the figure. For that purpose, Figure 1.

In FIG. 2, a delay circuit τ1 is required.

Furthermore, at the input point of the correlation circuit 30.31 in FIG. 1 or the correlation circuit 34.35 in FIG. 2, it is necessary to match the absolute delay times of the error signal and the interference signal. Therefore, τ
2 and τ3 delay circuits are required.

The explanation above has been given using a 16 QAM signal as an example of the main signal, but 4 PSK, 64 QAM, etc. are also the same except for the number of output bits of the A/D converter used in the error signal generation circuit. It is. Furthermore, although the explanation has been given using an example of an amplitude modulation signal as an interference signal, in the case of a frequency modulation signal, f(t)-ej of equation (1) or equation (2)
(cc>2t + o) instead of f, ej(m2(
t) - t + a) Also, in the case of a phase modulation signal, fe
j(02t+o(t)), and in the case of cw waves, f, e
j(ca2t+0) and can be processed in exactly the same way.

As a modification of the invention, the distributor 9 of FIG.
It is possible to provide the divider 9 after the variable amplitude circuit 10 and the divider 9 before the variable phase circuit 8, and even in such a case, the interference compensation circuit can be realized with the other completely same circuit configuration.

Although FIG. 1 or FIG. 2 shows an example of a configuration in which a variable amplitude circuit and a variable phase circuit are used in the IF band, the configuration is exactly the same even if the variable amplitude circuit and variable phase circuit are used in the RF band.

In the embodiment of the present invention shown in FIG. 1 or 2, the amplitude and phase of the interference signal received from the auxiliary antenna are adjusted to cancel the interference waves, but the amplitude and phase of the main signal received from the main antenna are adjusted. It goes without saying that interference waves can be canceled out in exactly the same way.

Furthermore, when adjusting the phase, the same effect can be obtained by adjusting the phase of the local oscillator used in the frequency converter instead of directly varying the phase of the signal.

In addition, in the embodiment of the present invention, in order to obtain an interference signal, an interference compensation circuit based on the principle of the present invention was prototyped and its compensation characteristics were measured. The results are shown in FIG. Here, a 16 QAM signal was used as the main signal, and a signal obtained by FM modulating a Cuff-Par signal was used as the interference signal.

The vertical axis in Figure 3 represents the signal-to-noise power ratio (C/N), and the horizontal axis represents the signal-to-interference power ratio (D/lJ). Rate=10
It shows the relationship between C/N and D/R at -4.

FIG. 3 shows an improvement effect of about 20 dB in D/lJ, confirming the effectiveness of the present invention.

As explained above, the present interference compensation circuit requires only one phase detector to detect the interference signal, and therefore the external circuit can be simplified, which is advantageous for downsizing the interference compensation circuit.

[Brief explanation of drawings]

Figures 1 and 2 are block diagrams showing an embodiment of the present invention, Figure 3 is a diagram showing the effects of the present invention, Figure 4 is a block diagram of a conventional interference compensation circuit, and Figure 5 is a four-level signal signal. FIG. 2 is an explanatory diagram of an error signal generation circuit for FIG. 1... Main antenna, 2, 5... Band pass filter,
3.6... Frequency converter, 4... Auxiliary antenna, 7
...Local oscillator, 8...Variable phase circuit, 9...Distributor, 10...Variable amplitude circuit, 11...Synthesizer, 1
2.13... Phase detector, 14.15... Low pass filter, 16.17... Identification circuit, 18.19...
- Subtractor, 20... Regenerated carrier wave, 21... 90° phase shifter, 22... Timer signal generation circuit, 23...
Phase detector, 25...Low pass filter, 26...
Identification circuit, 30°31... Multiplier, 32.33...
Integrator, 34, 35...EX-QR circuit, 100...
・Demodulator, 101...Control circuit, 102.103...
・Error signal generation circuit.

Claims (7)

[Claims] (1) A main antenna for receiving a main signal, an interference signal receiving means, an adjustment circuit for adjusting the relative relationship between the phase and amplitude of the output of the interference signal receiving means and the output of the main antenna, and adjustment by the circuit. a combining circuit that combines the outputs of the main antenna and the interference signal receiving means; a quadrature phase synchronous detector that inputs the output of the combining circuit and the reference carrier wave regenerated from the main signal and decomposes it into in-phase components and quadrature components; two error signal generation circuits each receiving an in-phase component and a quadrature component; and a phase detector coupled to the adjustment circuit to detect the phase of the signal from the circuit using the same reference carrier as the quadrature phase synchronized detector. and two multipliers each independently providing a correlation between the output of the phase detector and the output of the two error signal generation circuits, and two integrators each connected to the output of the multiplier. the output of one integrator associated with the in-phase component controls the amplitude adjustment of the adjustment circuit, and the output of the other integrator associated with the quadrature component controls the phase adjustment of the adjustment circuit. An interference compensation circuit characterized by: (2) The interference compensation circuit according to claim 1, wherein the adjustment circuit is constructed by cascading a variable phase circuit and a variable amplitude circuit. (3) The interference compensation circuit according to claim 1, wherein the adjustment circuit is realized by adjusting the output of a local oscillator. (4) The interference compensation circuit according to claim 1, wherein the interference signal receiving means includes an auxiliary antenna for receiving interference signals. (5) The interference compensation circuit according to claim 2, wherein the input of the phase detector is provided from the output of the cascade circuit. (6) The interference compensation circuit according to claim 2, wherein the input of the phase detector is provided from the input of the cascade circuit. (7) The interference compensation circuit according to claim 2, wherein the input of the phase detector is provided from the output of the variable phase circuit.