JPS62219655A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To manufacture a device proper to a high-density integrated logic circuit, which can improve the injection efficiency of a transistor for an injector, reactive currents thereof are reduced and which can be operated at high speed, by arranging each transistor in the longitudinal direction. CONSTITUTION:A first conductivity type first layer 2 is formed onto a substrate 1, and layer thickness is thinned selectively, leaving a first region constituting a transistor in the first layer 2 to shape a stepped section. A second conductivity type second layer 3 having forbidden band width equal to or larger than the first layer 2 is formed only in the recessed section of the stepped section, and a second conductivity type third layer 4 having forbidden band width smaller than the first layer 2 is shaped onto the layer 3 so as to bury a projecting section and the second layer 3. A first conductivity type fourth layer 5 having forbidden band width smaller than the third layer 4 is formed onto the third layer 4, and a second conductivity type fifth layer 6 is shaped onto the fourth layer 5. A first conductivity type diffusion region 7 is formed up to at least the fourth layer 5 from the surface of the fifth layer 6 so as to surround a second region corresponding to the upper section of said first region in the fifth layer 6, and an ohmic electrode is formed to the first layer 2, the second layer 3, the fifth layer 6 and the diffusion region 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device suitable for logic circuits that require high density integration and high speed.

Prior Art The structure of a conventional semiconductor device using silicon is shown in FIG. This structure is called an IIL circuit, and an equivalent circuit is shown in FIG. The n-type layer 102 formed on the silicon substrate p1, the first p-type diffusion layer 103 formed in the n-type layer 102, the first p-type diffusion layer 103, and the second p-type diffusion layer 104 in the lateral direction A vertical npn transistor 122 is configured by the n-type layer 102, the first p-type diffusion layer 103, and the n-type diffusion layer 105 formed in the first p-type diffusion layer. are doing. Normal injector 12
3 is connected to a constant voltage source and the emitter 124 is grounded, an inverter logic circuit is constructed using the pnp transistors 1213...- as a constant current source, with the base 125 as an input and the collector 126 as an output. In this example, the collector 126 is configured so that two outputs, C1 and 02, can be taken out.

The feature of this circuit is that since the npn transistor 122 is used as a so-called reverse transistor as shown in Fig. 3, the emitter 124 is shared, eliminating the need for collector separation in a general bipolar transistor integrated circuit. It is possible to

Problems to be Solved by the Invention Since the transistor 122 (npn) in the conventional example is formed as an inverse transistor, the concentration of the emitter layer is higher than the concentration of the base layer (corresponding to the p-type diffusion layer 103 in FIG. 3). In this case, the emitter injection efficiency does not increase and therefore the current amplification factor cannot be increased. Furthermore, attempts are made to increase the current amplification factor by reducing the base width, but as the base width becomes smaller, the base spreading resistance increases, making high-speed operation impossible.

a step of forming a first layer of a first conductivity type with a 0-nitride layer, and selectively leaving a desired first region constituting a transistor in the first layer; By reducing the layer thickness,
a step of forming a step portion in the first layer; a step of forming a second layer of a second conductivity type having a forbidden band width equal to or larger than that of the first layer only in the recessed portion of the step; forming a third layer of a second conductivity type having a forbidden band width smaller than that of the first layer so as to embed the convex portion and the second layer; smaller first
forming a conductive fourth layer; and forming a second conductive layer on the fourth layer.
forming a fifth layer of the first conductivity type from the surface of the fifth layer to at least the fourth layer so as to surround a second region above the first region of the fifth layer; a step of forming a diffusion region, the first layer, the second layer,
The method is characterized by including a step of forming an electrode using an ohmic contact metal in the fifth layer and the diffusion region, and arranging each transistor in a vertical direction.

In other words, by forming a vertical pnp (pnp) transistor, we can increase the injection efficiency of the transistor that serves as a constant current source, and by forming each layer constituting the transistor using an epitaxial growth method, we can freely select the concentration of each layer. Therefore, the current amplification factor of the npn transistor can be increased.

Also, the emitter layer of an npn reverse transistor is pnp)
Since it is also the base layer of the transistor, by increasing the thickness of only the region of this layer involved in transistor operation and increasing the thickness of other regions, the base resistance can be reduced without reducing the injection efficiency of the transistor. At this time,
By forming a petrojunction using an emitter layer as the base layer and a material with a narrower forbidden band width, the injection efficiency can be further increased, and the emitter layer is in contact with a thick region of the base layer that is not involved in the transistor region. By forming a current blocking layer having a wider forbidden band width than the base layer in the portion, the reactive current can be further reduced.

Effect: 6 b/' The effect of this technical means is as follows. That is, by making the transistor used as a constant current source vertical, it is possible to control the base width by controlling the film thickness using a liquid phase growth method, which has a good control side, and therefore it is possible to increase the injection efficiency. Also, since this base layer is also the emitter of the driving transistor, it is necessary to reduce the parasitic resistance of this layer, but the thickness of this layer is reduced only in the area related to transistor operation, and by increasing the thickness in other areas, the emitter resistance is reduced. can. Furthermore, in constant current transistors, the base layer material has a smaller forbidden band width than the emitter layer material, so it becomes a so-called wide gap emitter, which can increase injection efficiency, and the current blocking layer is made of a material with a larger forbidden band width than the base layer material. The reactive current used can be reduced.

Example Embodiments of the present invention will be described below based on the accompanying drawings.

FIG. 1 is a cross-sectional structural diagram of a semiconductor integrated circuit device manufactured by the method of the present invention. An injector layer 2 is formed on an InP substrate 1, which serves as an emitter of a transistor constituting an injector of a constant current source. The injector layer has a convex portion only in a region where a transistor is formed. Furthermore, a current blocking layer 3 for reducing reactive current is formed thereon so as to surround the region constituting the transistor. An emitter layer 4 of a driving transistor is formed thereon so as to bury the convex portion of the injector layer 2, and a base layer 5. The collector layer 6 is formed in this order. A base diffusion region 7 is formed in the collector layer from the surface to the base layer 5 so as to surround a predetermined collector region.

Here, since the emitter layer 4 is formed by burying the convex portion of the injector layer 2, the portion of the transistor component region 8 involved in the transistor operation is formed to have a thinner film thickness than other portions.

Collector electrode 9 using a metal that can form an ohmic contact. Base electrode 10. The semiconductor integrated circuit device of the present invention can be formed by forming the emitter electrode 11° and the injector electrode 12 on the back surface.

Next, the manufacturing method of the present invention will be explained step by step.

As shown in FIG. 2a, on a p-type InP substrate 1, a p-type pP with a concentration of 5×10"cys-3 is epitaxially grown to form an injector layer 2. Thereafter, a predetermined transistor forming region 2o is formed with a photoresistor 21. By protecting it and etching it for a predetermined period of time with an etching solution of Hq:H3P04=1=2, a convex portion in the region that will become the emitter of the injector transistor can be formed (FIG. 2b).

After removing the photoresist 24, an n layer having a larger forbidden band width than the base layer to be formed next is formed by liquid phase epitaxial growth.
InP of the form is grown at a concentration of 1 x 1018aN-3.

At this time, by selecting the degree of supersaturation of the liquid phase epitaxial layer and the height and width of the convex portion, as shown in FIG. Layers can be grown to form the current block 3. Similarly, by selecting the supersaturation degree of the liquid phase epitaxial layer, the emitter layer 4 can be made to block current 9.
It can be formed so as to bury the convex portions of the α layer 3 and the transistor configuration region 20. The emitter layer 4 is made of n-type InG, which has a smaller forbidden band width than the InP of the injector layer 22.
In aAs P, the concentration is 1x 10”) + 11-5,
The layer thickness on the transistor forming region 20 is 0.3 μm. Subsequently, the emitter layer 4 is formed using the liquid phase epitaxial method.
p-type InGa, which has a smaller forbidden band width than InGaAsP.
A base layer of AsP is formed with a concentration of 1×10"3" and a thickness of 0.4 PQ. On top of that, the concentration I X10'7
The collector layer 6 is made of n-type InGaAsP with a thickness of 0.
It will be formed into 6 units.

In FIG. 2d, the silicon nitride film 22 is formed to a thickness of 0.3 m.
After forming L/C, a photo process is used to leave the silicon nitride film 22 only on the upper part of the collector region 6 of the transistor and remove the other parts. Thereafter, Zn is diffused at 500° C. by sealed tube diffusion to form a pace diffusion region 7 so as to reach the base layer 5.

Thereafter, as shown in FIG.
The emitter layer 4 was etched using a 10 bene etching solution of So4:H2o2:H2o-1:1:5.
Or a current blocking layer 3 of the same conductivity type formed thereunder.
expose. After depositing Au/Zn/Au on the p-type layer, a base electrode 1o is formed using a lift-off method, and Au/Sn/Au is deposited on the n-type layer.
After depositing Au, a collector electrode 9 is formed using a lift-off method. An emitter electrode 11 is formed.

Furthermore, Au/Zn/Au is deposited on the entire surface of the back surface to form the injector electrode 12, thereby forming a semiconductor integrated circuit device as shown in FIG. 2(f).

The emitter layer is thinly formed only in the region that constitutes the transistor, which prevents a drop in the injection efficiency of the injector transistor, and at the same time, the forbidden band width of the material is approximately 0.
．． By using InGaAsP of 95 eV, the forbidden band width is smaller than that of InP (gap band width: 1.35 eV) of the injector layer, and the emitter injection efficiency can be made approximately 1 due to the effect of a so-called wide gap emitter.

Furthermore, since there is an InP current blocking layer having a side band width 11.\\ larger than the InGaAsP base layer of the injector transistor in a region other than the region constituting the transistor, leakage current can be reduced.

On top of that, the space layer of the driving transistor is made of InGaAs, which has an even smaller forbidden band width (the forbidden band width is about 0.75 eV).
), the current amplification factor of the transistor can be increased due to the wide gap emitter effect, and high-speed operation is possible. In this example, the current amplification factor of the injector transistor was hyHcy 5.5, and the current amplification factor of the drive transistor was hFE 80.

Effects of the Invention As described above, according to the present invention, the injection efficiency of the injector transistor can be increased, the leakage current is small, the reactive current is small, and the high-density integrated logic is capable of high-speed operation. A semiconductor integrated circuit device suitable for the circuit can be manufactured.

[Brief Description of the Drawings] Fig. 1 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, and Fig. 2 a/%/f is a process sectional view for explaining the manufacturing method of this embodiment. , Figure 3 shows the conventional IIL
A cross-sectional view of the circuit, and FIG. 4 is an equivalent circuit diagram of the IIL circuit. 1... InP substrate, 2... Injector layer, 3... Current blocking layer, 4... Emitter layer, 6... Paste layer. , 6... Collector layer. Name of agent: Patent attorney Toshio Nakao and 1 other person/2
/ P71F Tiger Base

Claims (1)

[Claims] forming a first layer of a first conductivity type on a substrate; and selectively reducing the thickness of the first layer while leaving a desired first region constituting a transistor in the first layer; a step of forming a second layer of a second conductivity type having a forbidden band width equal to or larger than that of the first layer only in the concave portion of the step; and further forming the convex portion thereon. forming a third layer of a second conductivity type having a forbidden band width smaller than that of the first layer so as to embed the second layer; and a third layer having a forbidden band width smaller than that of the third layer on the third layer. a step of forming a fourth layer of one conductivity type, a step of forming a fifth layer of a second conductivity type on the fourth layer, and a step of forming a second region of the fifth layer above the first region. forming a first conductivity type diffusion region from the surface of the fifth layer to at least the fourth layer so as to surround the fifth layer; and providing ohmic properties to the first layer, the second layer, the fifth layer and the diffusion region. A method for manufacturing a semiconductor device comprising a step of forming an electrode using a contact metal.