JPS62219397A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a refresh cycle by controlling the release period of the operation inhibition of a column address system which is inhibited from operating at the time of transition to the refresh mode based on an external control signal other than a column address strobe signal and a row address strobe signal. CONSTITUTION:An REF clock circuit 17' is constituted by adding NOR gates 17e and 17f and an inverter 17g to an REF clock circuit and the output of an AND gate 17c is applied as REF' to one input terminal of the NOR gate 17e. The NOR gate 17e cooperates with the NOR gate 17f to constitute a flip- flop, whose output is led out as REF through the inverter 17g. The NOR gate 17f is supplied with a signal WE together with the output of the NOR gate 17e. Consequently, the release period of the operation inhibition of the column address system is controlled by not only the column address strobe signal and row address strobe signal, but also other control signals.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a static access mode.

[Prior Art] In recent years, column address systems have been configured with static circuits, and a mode (referred to as static column mode) has been provided in which a column address decoder operates in accordance with changes in column addresses and outputs data. Dynamic MOS-
RAM is used.

FIG. 4 is a block diagram showing a conventional example of a dynamic RAM having a static column mode as described above.

In the figure, a memory cell array 10 has a plurality of memory cells regularly arranged along bit lines and word lines (not shown), and memory cells connected to the same bit line are connected to a sense amplifier/I10 gate 11. It is connected to input buffer 21 and output buffer 22 via.

The input buffer 21 temporarily stores the input data input from the input terminal 6, and the input buffer 21 temporarily stores the input data input from the input terminal 6.
give to The output buffer 22 temporarily stores data read from the memory cell and outputs it to the output terminal 7. The bit lines and word lines of the memory cell array 10 are selected by the column decoder 12 and row decoder 1, respectively.
It is done by 4. The column decoder 12 decodes the column address given from the column address buffer 13, and the row decoder 14 decodes the row address given from the row address buffer 15. The column address buffer 13 and the row address buffer 15 temporarily store a column address and a row address Add, which are input from the outside to the address input terminal 5 in a time-sharing manner. The row address buffer 15 also has a row address counter 16.
It also receives the row address generated by memory cell array 1.
In the 0 refresh mode, this internally generated row address is temporarily stored in place of the external row address.

R/W clock circuit 20. The CAS clock circuit 19 and the RAS clock circuit 18 have input terminals 2 and 18, respectively.
A read/write control signal WE (hereinafter simply referred to as WE), a column address strobe signal CAS (hereinafter simply referred to as CAS), and a row address strobe signal RAS (hereinafter simply referred to as R
The receiver (referred to as AS) generates a predetermined timing clock signal to control the operation of each circuit. R/W clock circuit 2
0 controls the operation of input buffer 21 and output buffer 22. The CAS clock circuit 19 is an input buffer 21
．． Output buffer 22 and column address buffer 13
control the behavior of In addition, the CAS clock circuit 19
AS is generated and applied to the REF clock circuit 17. R.A.
The S clock circuit 18 generates a sense amplifier activation signal (hereinafter simply referred to as I) to control the operation of the sense amplifier included in the sense amplifier/I10 gate 11.

Moreover, this maize is given to the 100 generation circuit 30.

Furthermore, the RAS clock circuit 18 generates RAS and RAS.
It is applied to the EF clock circuit 17 and the τ1 generation circuit 30. The REF clock circuit 17 generates a refresh clock REF (hereinafter simply referred to as REF) for switching the semiconductor memory device 1 to a refresh mode. As will be described later, this REF is output when RAS falls after CAS falls. Therefore, the refresh mode at this time is referred to as the CAS before πWI refresh mode. REF output from the REF clock circuit 17 is sent to the row address buffer 15. Provided to address counter 16 and CE generation circuit 30. The row address buffer 15 is configured to switch and store the address from the address input terminal 5 and the address from the row address counter 16 in response to this REF. The CE generation circuit 30 generates a column address system enable signal CE (hereinafter simply referred to as 100) for controlling whether or not the column address system (column decoder 12, column address buffer 13, etc.) is enabled or disabled. be.

This CE is applied to column decoder 12 and column address buffer 13.

FIG. 5 is a circuit diagram showing details of the REF clock circuit 17 shown in FIG. 4. In the figure, CAS and RAS are applied to one input terminal of NOR gates 17a and ITb, respectively. The output terminals and input terminals of these NOR gates 17a and 17b are connected across each other to form a so-called flip-flop. The output of this flip-flop is applied to one input terminal of AND gate 17C. IAS inverted by an inverter 17d is applied to the other input terminal of the AND gate 17c. REF is output from the output terminal of the AND gate 17c.

FIG. 6 is a circuit diagram showing details of the 100 generation circuit 30 shown in FIG. 4. In the figure, RAS and REF are respectively inverted by inverters 31a and 31b and then applied to one input terminal and the other input terminal of NA and ND gate 31c. The output of this NAND gate 31C is inverted and applied to one input terminal of an AND gate 31d. An inverted signal is applied to the other input terminal of the AND gate 31d. The output of the AND gate 31d is inverted by the inverter 31e and becomes 100.

Next, the operation of the circuit shown in FIG. 4 during a read cycle will be described with reference to the timing chart shown in FIG.

When RAS falls, the row address buffer 15 latches the row address (RA) input from the address input terminal 5. This latched row address is decoded by the row decoder 14 and the memory cell array 10
One of the word lines is selected and its potential rises. Accordingly, data in memory cells connected to the selected word line is read onto each bit line. Next, the RAS clock circuit 18 falls 100 after a predetermined delay time from the fall of RAS, and activates the sense amplifier 11 connected to each bit line. A sensing operation is thereby performed.

In addition, with the fall of the clock, Cτ goes to "L" level, and from then on, the column address system (column decoder 12.
Column address buffer 13, etc.) is address input terminal 5
It operates by following the external address input from. moreover,
When the CA signal falls to the "L" level, the data output system operates and data output appears on the output buffer 22.

Next, with reference to the timing chart shown in FIG.
The operation of the circuit shown in the figure will be explained.

When ττι falls before RAS, when RAS falls, REF becomes the "H0 level" and the memory cell array 10 enters the refresh mode.

When REF rises, the row address is not an external input, but the output of the internal row address counter 16 is latched into the row address buffer 151. In response, the potential of the word line corresponding to the second row address rises, and the information of the corresponding bit is sensed (refreshed). Note that in this CAS refresh mode, the column address system does not need to operate at all. Therefore, the circuit shown in FIG. 6 keeps GE at the "H" level in this refresh mode, and inhibits column address system operations such as the column decoder 12 and column address buffer 13.

[Problems to be Solved by the Invention 1] Next, the problems of the above conventional example will be explained with reference to the timing chart shown in FIG.

As shown in FIG. 9, in the above conventional example, CA
After entering the S-before RAS refresh mode, when CAS is set to "H" at time t2, REF returns to the "L" level and the CAS-before-IAS refresh mode ends.Furthermore, in response to the fall of REF, C.E.
also falls, and the inhibition of column address system operation is released. Therefore, from now on, the column address system operates following changes in the external address signal, and unnecessary power supply current flows through the column address system. Therefore, the conventional semiconductor memory device has a problem in that power consumption increases unnecessarily.

Note that CAS is started up prior to RAS to end the refresh mode, for example, when switching to counter check mode (a mode for checking whether the address counter 16 is operating normally) is performed afterwards. This is to allow normal access (read/write) to be performed from time to time. That is, as shown by B in the figure, when CAS falls again before RAS rises, the row address latched at time t1 (the address generated by the row address counter 16) and the column address latched at time t3 A normal access is made to the memory cell specified by (column address from the outside), and a counter is checked based on the access.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that can prevent unnecessary increases in power consumption in the column address system. do.

[Means for Solving the Problems] A semiconductor memory device according to the present invention is capable of arbitrarily setting the timing for lifting inhibition of column address system operation based on an external control signal other than a column address strobe signal and a row address strobe signal. A control means is provided.

[Function] In the present invention, the timing to release the prohibition of column address system operation is controlled not only by the column address strobe signal and row address strobe signal but also by other control signals, thereby eliminating the need for the column address system to operate. be prevented from becoming operational at times,
As a result, unnecessary power consumption in the column address system is reduced.

[Embodiment] FIG. 1 is a circuit diagram showing an example of the configuration of a REF clock circuit used in a semiconductor memory device according to an embodiment of the present invention. This embodiment differs from the conventional device shown in FIG. 4 only in the configuration of the REF clock circuit, and the other configurations may be the same as that shown in FIG. 4. The REF clock circuit 17- shown in FIG. 1 has the same configuration as the REF clock circuit 17 shown in FIG.

R gates 17e and 17f and an inverter 17g are newly added. The output of AND gate 17C is R
EF'' to one input terminal of the NOR gate 17e. The NOR gate 17e cooperates with the NOR gate 17f to form a flip-flop, and its output is derived as REF via the inverter 17g.
WE is applied to the NOR gate 17f together with the output of the NOR gate 17e.

Next, the operation of the circuit shown in FIG. 1 will be briefly described with reference to the timing chart shown in FIG.

As shown in the figure, in the CAS before RAS refresh mode, REF- has exactly the same waveform as REF shown in FIG. However, the fall timing of REF- is controlled by WE by newly added NOR gates 17e and 17f and inverter 17g. That is, when WE is at “L” level, REF-
Even if REF falls, REF does not fall. Then, when WE rises, REF falls. In this way, R.E.
The falling timing of F, that is, the end timing of the refresh mode is controlled by WE.

Furthermore, the operation of one embodiment of the present invention will be explained in detail with reference to the timing chart shown in FIG. As mentioned above, the above embodiment is different from the conventional example shown in FIGS. 4 to 6 in terms of REF control conditions. That is, the third
In the figure, the CAS before RAS refresh mode is entered at time t1, and after REF becomes H” level, W
When E (read/write control signal) is set to "L" level (write state), even if CAS becomes "H" level at time t3, REF remains at "H" level.
This state continues until WE goes to "H" level at time t4. In such an operation, the column address system does not operate due to the transition of the external address signal between times t3 and t4, and the current that is unnecessarily consumed by these operations can be cut. Furthermore, when in the counter check mode, normal read/write operations are possible by setting WE to the "H" level immediately before the counter check mode.

In the above embodiment, the case where WE is used to control the fall timing of REF is shown, but this may be done by other control signals (for example, an output enable signal that controls output data, or a dedicated signal for REF control). control signals, etc.).

Further, in the above embodiment, an example was shown in which switching between enabling and disabling the column address system is performed in synchronization with REF during the CAS before RAS refresh mode.
This does not necessarily have to be REF, and other dedicated power-down signals or the like may be used.

Furthermore, in the above embodiment, the static column mode was taken as an example, but this is a page mode.

If you have a problem in nibble mode or the like and it includes a static operation, it can be done in the same way.

[Effects of the Invention] As described above, according to the present invention, the timing for releasing the prohibition of column address system operation, which is prohibited upon transition to the refresh mode, is determined by using signals other than the column address strobe signal and the row address strobe signal. Since it is configured to be controlled based on an external control signal, unnecessary current consumption in the column address system can be cut, and power consumption in refresh cycles can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing details of a REF clock circuit used in a semiconductor memory device according to an embodiment of the present invention. FIGS. 2 and 3 are timing charts for explaining the operation of the embodiment shown in FIG. 1. FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device. FIG. 5 is a circuit diagram showing details of the REF clock circuit shown in FIG. 4. FIG. 6 is a circuit diagram showing details of the generator circuit shown in FIG. 4. FIG. 7 is a timing chart showing the operation of the embodiment shown in FIG. 4 during a read cycle. FIG. 8 shows the same before π of the embodiment shown in FIG.
3 is a timing chart showing the operation in the 3-refresh mode. FIG. 9 shows the CAS before R in the embodiment shown in FIG.
3 is a timing chart for explaining problems that occur during AS refresh mode. In the figure, 1 is a semiconductor memory device, 2 to 4 are input terminals,
5 is an address input terminal, 10 is a memory cell array, 11
is a sense amplifier/I10 gate, 12 is a column decoder, 13 is a column address buffer, 14 is a row decoder, 15 is a row address buffer, 16 is a row address counter, 17' is a REF clock circuit, 17a, 17b
, 17e, 17f are NOR gates, 17c is an AND gate, 17d and 17g are inverters, 18 is a RAS clock circuit, 19 is a CAS clock circuit, 20 is an R/
W clock circuit, 30 shows a CE generation circuit.

Claims (2)

[Claims] (1) A memory cell array including a plurality of memory cells, a column address system that specifies a column address of the memory cell array following address data from the outside, and address data from the outside or address data generated internally. a row address system that specifies the row address of the memory cell array according to the memory cell array; and a control means for operating the row address system in accordance with the internally generated address data, wherein the semiconductor memory device is configured to prohibit external control other than the column address strobe signal and the row address strobe signal. It is characterized in that means is added to the control means for arbitrarily controlling the release timing of prohibition of the operation of the column address system based on the signal,
Semiconductor storage device. (2) The semiconductor memory device according to claim 1, wherein the external control signal is a read/write control signal.