JP2787674B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a static access mode. 2. Description of the Related Art In recent years, a mode in which a column address system is constituted by a static circuit and a column address decoder system operates following a change in a column address to input / output data (referred to as a static column mode). Is used. FIG. 4 is a block diagram showing a conventional example of a dynamic RAM having a static column mode as described above. In the figure, a memory cell array 10 is formed by regularly arranging a plurality of memory cells along bit lines and word lines (not shown). Memory cells connected to the same bit line are sense amplifiers / I / Os. Input buffer 21 and output buffer 22 via gate 11
Connected to. An input buffer 21 temporarily stores input data input from an input terminal 6 and has a sense amplifier I / I /
It is given to the O gate 11. Output buffer 22 temporarily stores the data read from the memory cell and outputs the data to output terminal 7. [0005] Selection of a bit line and a word line of the memory cell array 10 is performed by a column decoder 12 and a row decoder 14, respectively. Column decoder 1
2 decodes a column address given from a column address buffer 13 and a row decoder 14
Is for decoding a row address given from the row address buffer 15. The column address buffer 13 and the row address buffer 15 temporarily store a column address and a row address Add externally input to the address input terminal 5 in a time-division manner. The row address buffer 15 also receives a row address generated by the row address counter 16 and temporarily stores the internally generated row address instead of an external row address when the memory cell array 10 is in the refresh mode. I do. An R / W clock circuit 20, a / CAS clock circuit 19 and a / RAS clock circuit 18 are provided with read / write control signals / WE (hereinafter simply referred to as / WE and / WE) input from input terminals 2, 3 and 4, respectively. ), Column address strobe signal / CAS (hereinafter, referred to as
/ CAS) and a row address strobe signal / RAS (hereinafter simply referred to as / RAS) to generate a predetermined timing clock signal to control the operation of each circuit. The R / W clock signal 20 is supplied to the input buffer 2
1 and the operation of the output buffer 22. / CAS
The clock circuit 19 includes an input buffer 21 and an output buffer 2
2 and the operation of the column address buffer 13 are controlled. The / CAS clock circuit 19 generates / CAS and supplies it to the REF clock circuit 17. A / RAS clock circuit 18 generates a sense amplifier activation signal / S (hereinafter simply referred to as / S),
The operation of the sense amplifier included in the sense amplifier / I / O gate 11 is controlled. This / S is applied to / CE generation circuit 30. Further, the / RAS clock circuit 18
Generates / RAS, and REF clock circuit 17 and /
It is given to the CE generation circuit 30. The REF clock circuit 17 generates a refresh clock REF (hereinafter simply referred to as REF) for switching the semiconductor memory device 1 to a refresh mode. As described below, this REF is
Output when / RAS falls after CAS falls. Therefore, the refresh mode at this time is referred to as / CAS before / RAS refresh mode. The R output from the REF clock circuit 17
EF is a row address buffer 15 and an address counter 1
6 and / CE generation circuit 30. The row address buffer 15 is configured to switch and store the address from the address input terminal 5 and the address from the row address counter 16 in response to the REF. The / CE generation circuit 30 has a column address system (column decoder 12, column address buffer 13).
) To generate a column address enable signal / CE (hereinafter simply referred to as / CE) in order to control the operability / prohibition of the operation. / CE is applied to column decoder 12 and column address buffer 13. FIG. 5 shows the REF clock circuit 17 shown in FIG.
FIG. 3 is a circuit diagram showing details of the embodiment. In the figure, / CAS and / RAS are NOR gates 17a and 1 respectively.
7b is provided to one input terminal. These NOR gates 17a and 17b have their output terminals and input terminals cross-connected to form a so-called flip-flop. The output of this flip-flop is AND gate 17
c is applied to one input terminal. The other input terminal of the AND gate 17c has a signal inverted by the inverter 17d /
RAS is provided. REF is output from the output terminal of the AND gate 17c. FIG. 6 is a circuit diagram showing details of the / CE generation circuit 30 shown in FIG. In the figure, / RAS and REF are applied to one input terminal and the other input terminal of NAND gate 31c after being inverted by inverters 31a and 31b, respectively. This NAND gate 3
The output of 1c is inverted and applied to one input terminal of an AND gate 31d. / S is inverted and applied to the other input terminal of AND gate 31d. The output of AND gate 31d is inverted by inverter 31e to become / CE. Next, the operation in the read cycle of the circuit of FIG. 4 will be described with reference to the timing chart of FIG. When / RAS falls, row address buffer 15 latches a row address (RA) input from address input terminal 5. The latched row address is decoded by the row decoder 14, one word line in the memory cell array 10 is selected, and its potential rises. Accordingly, data of a memory cell connected to the selected word line is read out to each bit line. Next, the / RAS clock circuit 18 outputs the / RAS
After a predetermined delay time from the fall of S, / S falls, and the sense amplifier 11 connected to each bit line is activated. Thus, a sensing operation is performed. Also, with the fall of / S, / CE goes to "L" level. Thereafter, the column address system (column decoder 13, column address buffer 13, etc.) follows the external address input from the address input terminal 5. Works. Further, when / CAS falls to "L" level, the data output system operates and output buffer 22
Data output appears at Next, the operation of the circuit of FIG. 4 in the / CAS before / RAS refresh mode will be described with reference to the timing chart shown in FIG. When / CAS falls before / RAS,
At the time of fall of / RAS, REF goes to "H" level, and the memory cell array 10 enters the refresh mode. Since REF rises, the row address is not an external input but a row address counter 1 provided internally.
6 is latched in the row address buffer 15.
In response, the potential of the word line corresponding to the row address rises, and the information of the corresponding bit is sensed (refreshed). In the / CAS before / RAS refresh mode, the column address system does not need to operate at all. Therefore, the circuit of FIG. 6 keeps / CE at "H" level in this refresh mode, and inhibits the operation of the column address system such as the column decoder 12 and the column address buffer 13. Next, with reference to a timing chart shown in FIG. 9, problems of the above conventional example will be described. As shown in FIG. 9, in the above-described conventional example, after the / CAS before / RAS refresh mode is entered at time t1, when / CAS is set to "H" at time t2, R
EF returns to “L” level, and / CAS before / RAS
The refresh mode ends. Further, in response to the fall of REF, / CE also falls, and the operation inhibition of the column address system is released. Therefore, thereafter, the column address system operates following changes in the external address signal, and unnecessary power supply current flows through the column address system. Therefore, the conventional semiconductor memory device has a problem that power consumption is unnecessarily increased. The rise of / CAS prior to / RAS and the end of the refresh mode are performed, for example, in the counter check mode (mode for checking whether or not the address counter 16 is operating normally) performed thereafter. ) Is switched to normal access (read /
Write). That is, as shown by B in the figure, / CAS
Is dropped again before the rise of / RAS,
Normal access is performed to the memory cell specified by the row address (generated address of the row address counter 16) latched at time t1 and the column address (external column address) latched at time t3. A counter check is performed based on this. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a semiconductor memory device capable of preventing an unnecessary increase in power consumption of a column address system. With the goal. In the semiconductor memory device according to the present invention, the timing of releasing the operation prohibition of the column address system is determined based on an external control signal other than the column address strobe signal and the row address strobe signal. Arbitrary control means is provided. According to the present invention, the release timing of the operation prohibition of the column address system is controlled by not only the column address strobe signal and the row address strobe signal but also other control signals, so that the column address system does not need to operate. Sometimes, an operable state is prevented, and as a result, unnecessary power consumption in the column address system is reduced. FIG. 1 is a circuit diagram showing an example of a configuration of a REF clock circuit used in a semiconductor memory device according to an embodiment of the present invention. This embodiment differs from the conventional device shown in FIG. 4 only in the configuration of the REF clock circuit, and other configurations may be the same as those shown in FIG. The REF clock circuit 17 'shown in FIG.
In addition to the configuration of the REF clock circuit 17 shown in FIG.
R gates 17e and 17f and an inverter 17g are newly added. The output of the AND gate 17c is R
EF 'is supplied to one input terminal of the NOR gate 17e. The NOR gate 17e forms a flip-flop in cooperation with the NOR gate 17f, and its output is derived as REF via an inverter 17g. In addition,
NOR gate 17f is supplied with / WE together with the output of NOR gate 17e. Next, the operation of the circuit shown in FIG. 1 will be briefly described with reference to the timing chart shown in FIG. As shown, / CAS before / RAS
In the refresh mode, REF 'has exactly the same waveform as REF shown in FIG. However, this R
EF 'is the newly added NOR gates 17e and 17f.
And the inverter 17g makes the fall time
Controlled by WE. That is, when / WE is at "L" level,
Even if REF 'falls, REF does not fall. Then, when / WE rises, REF falls. As described above, the fall time of REF, that is, the end time of the refresh mode is controlled by / WE. Further, the operation of the embodiment of the present invention will be described in detail with reference to a timing chart shown in FIG. As described above, the above embodiment differs from the conventional example shown in FIGS. 4 to 6 in the REF control conditions. That is, at time t1 in FIG.
Enter S before / RAS refresh mode and REF
When / WE (read / write control signal) is set to the "L" level (write state) after the level of "/" is set to the "H" level, even if / CAS goes to the "H" level at time t3, R
EF remains at the "H" level, and this state changes at time t4.
And continues until / WE becomes "H" level. In such an operation, the column address system does not operate in accordance with the transition of the external address signal during the period from time t3 to time t4, so that unnecessary current consumption can be cut off. . In addition, in the counter check mode, if / WE is set to the “H” level immediately before that, a normal read / write operation can be performed. In the above-described embodiment, the case where / WE is used for controlling the fall timing of REF has been described. However, this is not the case with other control signals (for example, an output enable signal for controlling output data, a REF control signal). For example, a dedicated control signal). Further, in the above-described embodiment, the example in which the operation of the column address system is enabled and disabled in synchronization with REF in the / CAS before / RAS refresh mode has been described, but this is not necessarily REF. There is no need to use another power-down internal signal or the like. Further, in the above-described embodiment, the static column mode has been described as an example. However, the same can be applied to a case including a static operation in a page mode, a nibble mode, or the like. As described above, according to the present invention, a column address strobe signal and a row address strobe are used to release the operation prohibition of the column address system whose operation is prohibited in accordance with the transition to the refresh mode. Since the control can be performed based on an external control signal other than the signal, unnecessary current consumption to the column address system can be cut, and power consumption in a refresh cycle can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing details of a REF clock circuit used in a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of the embodiment shown in FIG. 1; FIG. 3 is a timing chart for explaining the operation of the embodiment shown in FIG. 1; FIG. 4 is a block diagram illustrating an example of a conventional semiconductor memory device. FIG. 5 is a circuit diagram showing details of a REF clock circuit shown in FIG. 4; FIG. 6 is a circuit diagram showing details of a / CE generation circuit shown in FIG. 4; FIG. 7 is a timing chart showing an operation in a read cycle of the conventional example shown in FIG. FIG. 8 shows a conventional / CAS before / RA shown in FIG.
FIG. 4 is a timing chart showing an operation in an S refresh mode. FIG. 9 is a timing chart for explaining a problem that occurs in the / CAS before / RAS refresh mode in the embodiment shown in FIG. 4; [Description of Signs] 1 semiconductor memory device, 2, 3, 4 input terminal, 5 address input terminal, 10 memory cell array, 11 sense amplifier / I / O gate, 12 column decoder, 13 column address buffer, 14 row decoder, 15 Row address buffer, 16 row address counter, 1
7 'REF clock circuit, 17a, 17b, 17e,
17f NOR gate, 17c AND gate, 17
d, 17g Inverter, 18 / RAS clock circuit, 19 / CAS clock circuit, 20 R / W clock circuit, 30 / CE generation circuit.

Claims (1)

(57) [Claims] A memory cell array (1) having a plurality of memory cells
0), a column address system (12, 13) for designating a column address of the memory cell array following the external column address data, and an external row address data or an internally generated row address data. A row address system (14, 1) for designating a row address of the memory cell array follows.
5, 16), a source (4) of a row address strobe signal (/ RAS), and a source (3) of a column address strobe signal (/ CAS). A semiconductor memory device having a refresh mode for operating the row address system following the refresh mode, wherein (t2) after the start of the refresh mode, the deactivation of the column address strobe signal (t3), and the refresh mode. Means (2) for supplying an external control signal (/ WE) inputted until the end or the second activation (B) of the column address strobe signal
Receiving the row address strobe signal and the column address strobe signal, activating the row address strobe signal in response to activation, and deactivating in response to the column address strobe signal inactivation. A first logic circuit means (17a-17d) for generating one internal control signal (REF '); receiving the first internal control signal and the external control signal, and activating the first internal control signal A second internal control signal (e.g., a second internal control signal activated in accordance with the activation of the column address strobe signal and deactivated between the end of the refresh mode or the second activation of the column address strobe signal). REF), a second logic circuit means (17e-17g) for generating the second internal control signal and the row address straw. Receiving a signal, generating a third internal control signal (/ CE) that is activated in response to the inactivation of the second internal control signal and inactivated in response to the inactivation of the row address strobe signal. Third logic circuit means (31a-3
1e), wherein the column address system receives the third internal control signal and becomes operable only during a period in which the third internal control signal is activated.