JPS62213480A - Picture signal binarizing circuit - Google Patents

Abstract

PURPOSE:To reduce the size of circuit scale by means of both hardware and software and to simplify the work of signal adjusting by varying the frequency of a pulse wave generated in accordance with a controlling signal, and using the resulting pulse for the driving clock of an image sensor. CONSTITUTION:A frequency-variable type driving clock generating circuit 10 varies the frequency of its output clock signal in accordance with a frequency control signal supplied to a control terminal 11. The image sensor 1 outputs the optical information incident to itself as a pulse signal corresponding to the clock from the circuit 10, and supplies the pulse to an amplifier circuit 3. Accordingly, the frequency of the signal outputted from the image sensor 1 varies in accordance with the frequency control signal supplied to the terminal 11. The circuit 3 has its gain characteristic correspondent to the frequency of its own input signal. Consequently, the level of a picture signal inputted to a comparator 4 varies in accordance with the above-said control signal. Therefore, the level of binarization also varies so that an effect similar to that to be obtained by varying a reference voltage is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a binarization circuit that converts an image signal output from an image sensor into a binarized signal.

[Conventional technology]

FIG. 2 is a block diagram showing an image sensor device according to the prior art. In the figure, 1 is an image sensor that converts optical information into an electrical signal, for example, a -dimensional image sensor, and 2 is each photoelectric sensor on this image sensor 1. This is a drive clock generation circuit (fixed frequency) for driving the switch of the element.

The image sensor 1 uses this drive clock generation port j12i2
The image signal is output in synchronization with the clock from. 3 is an amplifier circuit for amplifying this image signal, and 5 is a base s1! for generating a reference voltage for determining the level of black and white. In the voltage generating circuit, the 6 semi-fixed resistors adjust and determine this reference voltage. The comparison circuit 4 compares this reference voltage with the input image signal and binarizes it. This circuit has the effect of emphasizing the shading of the original image by using a binary signal, and conventional circuits, such as the circuit described in Japanese Patent Laid-Open No. 158769/1982, emphasize the shading of the original image. Adjustment of the reference voltage for binarization was performed using a semi-fixed resistor 6. Also, the frequency f of the clock that drives the image sensor 1
is always constant and does not change.

[Problem that the invention seeks to solve]

In the above conventional circuit, the semi-fixed resistor 6 for adjusting the reference voltage is
Therefore, it was necessary to consider ways to arrange the circuit in a position where it could be easily adjusted, and to find a way to make the adjustment easy, which placed constraints on the miniaturization and simplification of the circuit.

The purpose of the present invention is to eliminate the semi-fixed resistor 6 for adjusting the reference voltage and to provide a reference voltage adjusting means to replace it, thereby making the circuit smaller and simpler, and simplifying the signal adjustment for binarization. the hardware.

This is achieved through both software.

[Means for solving problems]

In order to achieve the above object, the present invention provides a variable frequency clock generation circuit that changes the frequency of the pulse wave generated according to a control signal, and supplies the clock signal generated by this clock generation circuit as the image sensor lζ driving clock. I configured it to do this.

[Effect]

A variable frequency clock generation circuit changes the frequency of a clock signal according to a control signal. When the variable range of this clock signal is set within a range that includes a frequency higher than the cutoff frequency of the circuit provided between the image sensor and the comparison circuit, the circuit between the image sensor and the comparison circuit adjusts the gain according to the control signal. Therefore, the input signal of the comparator circuit changes its level in accordance with the control signal. Therefore, the binarization level of the comparator circuit changes according to the control signal.

〔Example〕

FIG. 1 shows a first embodiment of the present invention. The image signal readout circuit of this embodiment includes an image sensor 1, an amplifier circuit 3 that amplifies the output signal of the image sensor 1, a comparison circuit 4, and a comparison circuit 4. Basic single voltage generation circuit WIJ5. It consists of a variable frequency drive clock generation circuit 10. Image sensor 1. Amplification circuit 3. Comparison circuit 4. The reference voltage generating circuit 5 is similar to the circuit shown in FIG.

The output voltage of the reference voltage generating means 5 is directly applied to the comparison circuit 4. Drive clock generation port w510 is control terminal 1
The frequency of the output clock signal is changed according to the frequency control signal applied to the output clock signal. A specific circuit of the drive clock generation circuit 10 will be described later. The image sensor 1 outputs incident optical information as a pulse signal in response to a clock from a drive clock generation circuit, and supplies the pulse signal to an amplifier circuit 3. The frequency of the signal output from the image sensor 1 is determined by the control terminal 11.
varies depending on the frequency control signal applied to the

Since the amplifier circuit 3 has a gain characteristic that depends on the frequency of the input signal, even when a signal of the same field of view is input, the signal level of the output signal changes depending on the frequency. Therefore, even if the output voltage of the reference voltage generation circuit 5 is constant, the level of the image signal 7 input to the comparison circuit 4 changes according to the frequency control signal input to the control terminal 11. The binarization level also changes, and the same effect as when changing the reference voltage can be obtained.

FIG. 3 shows a graph of the frequency-gain characteristics of the amplifier circuit 3. In the amplifier circuit 3, the frequency of the input signal is the cutoff frequency f.
, the gain gradually decreases. At a frequency f1 below the cutoff frequency f, the gain is 'wl', but at a frequency ft exceeding the cutoff frequency f, the gain decreases to A,t.

The present invention utilizes a region (region from frequency f to frequency fh) in which the gain changes at a predetermined rate depending on the frequency of the input signal. Control terminal 111 of drive clock generation circuit 10
By changing the frequency control signal applied to the image sensor 1,
The frequency of the image signal output from is varied in the range from f to fj. Then, the gain of the amplifier circuit 3 changes in the range from Awa to 'ek, and the voltage level of the output of the amplifier circuit 3 changes. When the output voltage level of the amplifier circuit 3 changes, the binarization level of the comparison circuit [4 changes even if the reference voltage generated by the reference voltage generation circuit 5 is constant.

5 and 6 show the relationship between the output voltage of the amplifier circuit 3 and the reference voltage and the relationship between the output signal of the comparator circuit 4 when the frequencies of the input signals of the amplifier circuit 3 are ft and h, respectively. Fifth
In FIG. 6, graph 7 shows the amplification circuit jf! Graph 8 shows the output signal of reference voltage generation circuit 5, and graph 9 shows the output signal of comparison circuit 4.

When the frequency of the input signal to the amplifier circuit 3 is ft, the gain of the amplifier circuit 3 is as high as 41, so up to the fourth pulse exceeds the reference voltage VrH, but the frequency is f.

When the gain of the amplifier circuit 3 increases to A,! The number of pulses exceeding the reference voltage VTI also decreases to 2 pulses. Therefore, at frequency f1, a binary signal of (001111) is output from the comparator circuit 4, but at frequency 1, an output of (000011) is obtained. This is compatible when the reference voltage is 'Tlh' shown by the broken line in FIG.

In the output of the comparator circuit 4, level 1 represents "black",
Assuming that level O represents "white", when the frequency is set to ft, the original signal becomes "more" than when the frequency is set to f.
The level close to "white" will be output as a signal, and conversely, the frequency will be changed to f! If you do this, the level closer to the river will be output as white. therefore,
When reading an original image with little difference in density, such as a thinly written original image, the frequency of the reading clock of the image sensor 1 may be lowered by controlling the frequency control signal applied to the control terminal 11.

FIG. 4 shows specific circuits of the reference voltage generation circuit 5 and comparison circuit 4. In the present invention, the reference voltage VTH may be fixed, so the power supply Vex is divided by resistors R, 4 to obtain the reference voltage VTH.
It is said that Comparison circuit 4 is released from comparator 41,
A reference voltage divided by a resistor R8°R1 is supplied to the reference voltage input terminal.

As described above, according to this embodiment, even when the base voltage 8 ('rH) is kept constant, by changing the generated clock frequency f of the drive clock generation circuit 11 that is input to the image sensor 1, the image of the intermediate color original can be changed. The relative level of the reference voltage VrH when binarizing the signal 7 can be changed.

The frequency range (f, ~fj) used in this example is as follows:
The cutoff frequency f is determined by the design of the amplifier circuit 3.

You can set it freely by changing . Therefore, the frequency range can be set according to the reaction speed of the image sensor 1 and the processing speed of the device connected to the output terminal 9.

The missing numbers show a second embodiment of the present invention. In the first embodiment, the cutoff frequency of the amplifier circuit 3 is 1. Although a clock with a frequency above is generated, in this embodiment, a frequency band below the cutoff frequency f is used. Therefore, the voltage level of the image signal input to the comparator circuit 4 is constant regardless of the frequency of the drive clock. In this embodiment, instead, the reference voltage supplied to the comparator circuit 4 is changed according to the frequency of the drive clock, so that the two
The digitization level is changed.

FIG. 7 is a block diagram showing this embodiment. The difference from FIG. 1 is that the reference voltage generating circuit 12 generates the reference signal 8 based on the output voltage of the amplifier circuit 3. Image sensor 1. Amplification circuit 3. The comparison circuit 49 and variable frequency drive clock generation circuit 10 are the same as those in the first embodiment. However, the cutoff frequency f of the amplifier circuit 3,
is a frequency variable drive clock generation circuit 1o as described later.
It is set higher than the upper limit of the frequency change range of the drive clock generated in

The reference voltage generation circuit 12 of this embodiment includes a comparator 13
．． Diode 14. It consists of a peak hold circuit consisting of a capacitor 15 and a voltage dividing circuit consisting of resistors 16 and 17. The peak hold circuit holds the peak value of the output voltage of the amplifier circuit 3 in the capacitor 15. The voltage Tg held in the capacitor 15 is divided by resistors 16 and 17 and supplied to the comparator circuit 4 as the base voltage Tg. The retention period of the peak value, that is, the response characteristic is determined according to the time constant determined by the impedance (16, 17, etc.).In non-embodiments, this time constant is set sufficiently large.

FIG. 8 shows the frequency characteristics of the output voltage 7 of the amplifier circuit 3 and the output voltage 8 of the reference voltage generation circuit 12 in this embodiment. Graph α shows the frequency characteristics of the output signal of the amplifier circuit 3, graph b shows the frequency characteristics of the output signal of the peak hold circuit, and graph C shows the frequency characteristics of the basic signal input to the comparison circuit 4. As shown in graph b, the cutoff frequency fat of the peak hold circuit is equal to the amplification port ji! i
The cutoff frequency fe2 is set lower than the cutoff frequency fe2 of No. 3.

The cutoff frequency fe+ of the peak hold circuit is determined by the output impedance of the comparator 13, the internal resistance of the diode 14, the capacitance value of the capacitor 15, and the dividing resistor 16.
．． It can be set by changing the resistance value of 17.

In this embodiment, the reference voltage VTH is set to VTH by changing the frequency of the drive clock within the range of fi to 11.
The binarization level in the comparator circuit 4 is changed by changing it within the range from l to 'TH*.

In other words, even if a signal with the same black peak level is input from the amplifier circuit 3 to the peak hold circuit, by changing the frequency of the drive clock in the range from ft to f, the black peak level will be in the range from VTK□ to VTlh. Therefore, the binarization level in the comparison circuit 4 changes depending on the frequency of the driving clock even if the image signal has the same black peak.

FIG. 9 shows input and output signals of the comparison circuit 4 when the reference voltage VTH changes from VTHl to 'TH2. The same figure (11
When the image signal 7 whose voltage decreases stepwise as shown in FIG. , the reference voltage 8 is also 'Tit' for the same black peak (WJ1 pulse 20).
Since the signal is lowered to 100%, more signals are output as black. Therefore, when reading a document with a low density, the frequency of the drive clock may be increased.

According to this embodiment, the binarization level of the comparator circuit can be changed by changing the frequency of the drive clock.

In this embodiment, the image signal of the portion closest to black (the black point value) of the original information read by the image sensor 1 is held in the peak hold circuit, and the reference voltage is determined based on this voltage. , the optimal reference voltage is automatically determined according to the image being read.

In this embodiment, capacitor 15. If the time constant determined by resistor 16 and 17 is set relatively short, if a black peak exists in the middle when reading one image, the reference voltage will automatically change before and after it, so the binarization in comparator circuit 4 will be possible. It is possible to binarize image signals with uniform sensitivity even when the level changes and there are parts with different densities within a single document.

Furthermore, in this embodiment, the group 's1! Since the power supply of the pressure generation circuit is the output voltage of the amplifier circuit 3, by setting the resistance 16 to a small value or setting the resistance value to zero, the maximum value of the dynamic range of the output of the amplifier circuit 3 and the maximum value of the base:a@pressure can be adjusted. If the values match and the voltage is divided by the resistor 16, which does not use an unnecessarily high voltage as a reference voltage source, the image signal 7 may also be voltage-divided by the resistor.

Furthermore, in this embodiment, the positive terminal of the comparator of the reference voltage generation circuit 12 is connected to the output terminal of the amplifier circuit 3, but it is connected to the output terminal of the variable frequency drive clock generation circuit 10, so that the reference voltage can be directly derived from the drive clock signal. may be generated. However, in this case, either set the voltage of the output clock signal of the drive clock generation circuit 10 to be higher than the maximum value of the output of the amplifier circuit 3, or reduce the level of the output of the amplifier circuit 3 by resistor division, etc. 4 must be supplied.

Next, the first. FIG. 10 shows a specific configuration of the variable frequency drive pulse generation circuit 10 used in the second embodiment. The variable frequency drive pulse generation circuit 10 includes an oscillator 21. Start pulse generation circuit 22. Frequency division 823° AND circuit 24
．． It consists of an OR circuit 5. The frequency dividing circuit % divides the frequency of the original clock pulse generated by the oscillator 21 and outputs the result. A frequency control signal is applied to the decoder circuit U via a bus 26;
The decoder circuit 24 decodes this frequency control signal and outputs it as a 2'' binary code for each bit to the AND circuit 24.The other input terminal of the AND circuit ji2i 24 receives the output of the frequency dividing circuit for each bit. The output of the AND circuit 24 is input to an OR circuit 25, which outputs logic 1 if even one of the AND circuits 24 is square root 1.

Thus, for example, when the decoder outputs a binary 2, the output of the frequency divider circuit is divided by 2, and when the decoder outputs a binary 4, the output is divided by 4.

The start pulse generation circuit 22 is a signal indicating the start of reading from the image sensor.

〔Effect of the invention〕

According to the present invention, in place of the conventional clock with a constant frequency f given to the image sensor 1, a drive clock generation circuit 2' with a variable clock frequency f using hardware or software is installed, thereby generating an output. Output base progressive pressure VT of the reference voltage generation circuit 5 of the circuit of the data 9 generation part
The semi-fixed resistor 6 for II adjustment has been abolished, making the circuit less adjustable and more compact.

Also, by hardware or software, the clock frequency f
By changing and setting , it becomes possible to easily adjust the relative level difference between the image signal 7 input to the comparator circuit 4 and the reference voltage 8 (J'ry).

Adjustment of binarized output data has become easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a block diagram showing an image sensor device according to the prior art, FIG. 3 is a graph showing the frequency vs. gain characteristic of the amplifier circuit 3, and FIG. FIG. 4 is a circuit diagram showing an embodiment of a binarization circuit with a constant base voltage 'TH, and FIG. FIG. 6 is a waveform diagram showing the relationship between the reference voltage VTH8 and the image signal 7 and the binarized output data 9, FIG. 7 is a block diagram showing the second embodiment of the present invention, and FIG. is a graph showing the output versus frequency characteristics of the amplifier circuit 3 and the reference voltage generation circuit 5 shown in FIG. 7, and FIG. 9 is a waveform diagram showing the relationship between the reference voltage and the image signal and the relationship between the binarized output data. , 1st
0 is a block circuit diagram of the driving clock generation circuit 2, and FIG. 11 is a waveform diagram showing an example of a clock pulse having a different frequency from the start pulse sent to the image sensor 1. 1... Image sensor 2... Drive clock generation circuit 3... Amplification circuit 4... Comparison circuit 5...
Reference voltage generation circuit 10... Frequency variable drive clock generation circuit 11...
・Control terminal 12... base single voltage generation circuit 11
Kuto12 Kuchi

Claims (6)

[Claims] (1) Convert the input optical image signal to an electrical image signal,
An image sensor that outputs the electric image signal in synchronization with a clock signal, and an output signal of the image sensor and a reference signal are supplied, and the image signal is binarized by comparing the electric image signal and the reference signal. A variable frequency clock signal that changes the frequency of the clock signal generated in accordance with a control signal in an image signal binarization circuit that includes a comparison circuit that outputs and a reference voltage generation circuit that generates a reference signal and supplies it to the comparison circuit. An image signal binarization circuit comprising a generation circuit and supplying a clock signal generated by the variable frequency clock signal generation circuit to the image sensor. (2) In claim 1, the frequency change range of the variable frequency clock signal generation circuit is set to include at least a region exceeding the cutoff frequency of the circuit between the image sensor and the comparison circuit. An image signal binarization circuit characterized by: (3) In claim 2, an amplifier circuit for amplifying the output signal of the image sensor is provided, and the cutoff frequency of the amplifier circuit is set at least to the maximum frequency in the frequency variable range of the variable frequency clock signal generation circuit. An image signal binarization circuit characterized by the following settings. (4) In claim 1, an amplifier circuit is provided which amplifies the output signal of the image sensor and supplies the amplified output to the comparison circuit, and is connected to the output terminal of the amplifier circuit and outputs the output signal of the amplifier circuit. An image signal binarization circuit characterized in that a reference voltage generating means for generating the reference signal is provided. (5) The image signal binarization circuit according to claim 4, wherein the reference voltage generation means includes a peak hold circuit that detects a peak value of the output signal of the amplifier circuit. (6) An image signal binarization circuit according to any one of claims 4 to 5, characterized in that the cutoff frequency of the reference voltage generating means is set to be equal to or lower than at least the maximum frequency of the variable range of the clock signal. .