JP2570122B2 - Video signal white level setting circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a white level setting circuit for A / D converting an analog video signal into a digital signal.

[0002]

2. Description of the Related Art Conventionally, for example, in computer processing of a bank passbook or the like, pages or lines of
Processing is performed by A / D converting a video (video) signal obtained by reading with a D area sensor or the like. When a video signal is converted into a digital signal in this manner, it is impossible to faithfully convert the video signal as it is because the number of bits of the digital signal is limited. Therefore, in A / D conversion of a video signal, a white level voltage which is a maximum level and a black level voltage which is a minimum level are set for the video signal, and the video signal is compared with the white level voltage and the black level voltage. Thus, the analog video signal is converted into a digital signal at a predetermined resolution.

FIG. 3 shows a conventional white level voltage setting method. Here, as shown in FIG. 3A, the peak of the video signal is fixedly set as the white level voltage. Further, for example, in the video signal processing circuit disclosed in Japanese Patent Application Laid-Open No. H3-143082, as shown in FIG. 4, the peak level (white level) of the video signal output from the variable gain adjustment circuit 41 that varies the amplitude of the video signal. Level) and the blank level (black level) are held in the peak blank holding circuit 43. The control means 43 adjusts the gain of the variable gain adjustment circuit 41 so that the difference between the peak level and the blank level falls within the range of a preset contrast setting value, and adjusts the white level and the black level of the video signal to A / A. The configuration is such that the resolution of the A / D converter is maximized by making it approximately equal to the input voltage range of the D converter.

[0004]

As shown in FIG. 3A, among the above-mentioned conventional methods for setting a white level voltage, a method for fixedly setting the first peak value of a video signal as a white level voltage. In this case, since the white level voltage does not follow the video signal, the peak value of the actual video signal read due to, for example, contamination of the page or line portion of the bankbook is ΔV smaller than the white level voltage as shown in FIG. If it is low, efficient digital conversion cannot be performed. In the method of making the white level and the black level of the video signal substantially equal to the input voltage range of the A / D converter by the preset contrast setting value shown in FIG. There is a problem that it is greatly different from the above.

The present invention has been made to solve such a conventional problem, and it is possible to set a white level signal that follows a video signal and does not decrease even if the video signal temporarily drops. It is an object to provide a white level setting circuit for a video signal.

[0006]

In order to achieve the above object, a video signal white level setting circuit according to the present invention comprises a first white level generation circuit for generating a white level hold signal following a white peak level of a video signal. A second white level generation circuit for generating a white level long hold signal obtained by holding the white level hold signal for a long time; and a white level hold signal or a white level long hold signal having a large value among white level hold signals. It is composed of a circuit that outputs a signal. In a preferred aspect, the first
A first level charging circuit for charging the video signal;
And a first discharge resistor for discharging a charged signal and outputting a white level signal following the video signal, wherein the second white level generation circuit includes the white level hold signal. , A second capacitor having a larger capacity than the first capacitor for charging the divided signal, and discharging the charged signal to output a white level long hold signal. And a second discharge resistor.

[0007]

According to the present invention, in a normal state, the first white level generation circuit outputs a white level signal that follows the white peak level of the video signal. If the video signal drops significantly, the white level long hold signal long-held by the second white level generation circuit is output as a white level signal. This prevents a decrease in the white level signal.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a white level setting circuit according to one embodiment of the present invention. In FIG. 1, the white level setting circuit includes a white level hold circuit 30.
And the white level long hold circuit 40 and the output circuit 50
It is composed of

The white level hold circuit 30 includes the amplifier 3, the diode 8, and the white level hold capacitor 1.
2. A white level hold signal 18 which is composed of a discharge resistor 13 and an amplifier 4 and follows a video signal is generated. Further, the white level long hold circuit 40 includes the voltage dividing resistor 1.
4 and 15, an amplifier 5, a diode 10, a white level long hold capacitor 16, a discharge resistor 17 and an amplifier 6, and generates a white level long hold signal 19 which is held longer than the white level hold signal 18. The output circuit 50 includes the diodes 9 and 11 and the amplifier 7.
And outputs the larger one of the white level hold signal 18 and the white level long hold signal 19 as the white level signal 20.

In this embodiment, as an example, the capacitance of the white level holding capacitor 12 is 0.01 μF, and the capacitance of the white level long holding capacitor 16 is 7 μF.
And the resistance values of the discharge resistors 13 and 17 are set substantially equal.

The voltage dividing resistors 14 and 15 set a voltage level at which a long hold is applied to the white level hold signal 18. For example, when the resistance values of the voltage dividing resistors 14 and 15 are set to be 1: 9, a white level long hold signal 19 which is reduced by 10% of the white level hold signal 18 is generated. . Therefore, the value of the white level long hold signal 19 with respect to the white level hold signal 18 can be changed by changing the value of the voltage dividing resistors 14 and 15 using a variable resistor.

Next, the operation of the white level setting circuit according to the present embodiment configured as described above will be described. When a video signal 21 as shown in FIG. 2 is input from the input terminal 1, the video signal 21 is current-amplified by the amplifier 3, and the diode 8 passes only its positive output. Diode 8
Is passed through the white level holding capacitor 12.
, And the charged signal is discharged by the discharging resistor 13.

The discharged signal is current-amplified by the amplifier 4, and is output from the amplifier 4 as a white level hold signal 18 following the video signal 21.

The white level hold signal 18 is further divided by the voltage dividing resistors 14 and 15, and after current amplification by the amplifier 5, passes through the diode 10 and is charged into the white level long hold capacitor 16. .

The signal charged in the white level long hold capacitor 16 is discharged by the discharge resistor 17, further amplified by the amplifier 6, and output as a white level long hold signal 19. Here, since the capacity of the white level long hold capacitor 16 is set sufficiently larger than the white level hold capacitor 12, the white level hold signal 1 following the video signal 18 is set.
A white level long hold signal 19 that is held for a time longer than 8 is generated.

Of the white level hold signal 18 or white level long hold signal 19, the one with the larger voltage is selected by the diode 9 or 11, the current is amplified by the amplifier 7, and is output from the output terminal 2 as the white level signal 20. , And A / D converters (not shown).

As described above, since the operation is performed, as shown in FIG. 2, when the peak level of the video signal 21 is high, the white level hold signal 1 following the video signal 21 is output.
8 is generated, and when the peak of the video signal 21 falls near the black level 22,
White level long hold signal 19 is white level setting signal 2
It is generated as 0. Therefore, for example, when a page or line of a bank passbook is read by a CCD area sensor or the like, a white level signal that follows the video signal is obtained in a normal state. Further, when the video signal temporarily drops due to dirt on the page or line of the passbook or the like, a signal obtained by long-holding the white level signal is output as the white level signal, so that the white level signal is prevented from lowering. Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0018]

As described above, according to the white level setting circuit of the present invention, a white level signal following a video signal can be obtained in a normal state. Further, when the video signal temporarily drops, a signal obtained by long-holding the white level signal is output as the white level signal, so that the white level signal is prevented from lowering. This makes it possible to set a white level signal that follows the video signal as a whole, and realizes efficient digital conversion.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a white level setting circuit according to one embodiment of the present invention.

FIG. 2 is a waveform diagram showing a state of a white level signal generated by a white level setting circuit of the embodiment.

FIG. 3 is a waveform diagram showing a conventional method of setting a white level signal.

FIG. 4 is a circuit diagram showing an example of a conventional video processing circuit for adjusting a white level.

[Explanation of symbols]

 3, 4, 5, 6, 7 Amplifier 8, 9, 10, 11 Diode 12 White level holding capacitor 13, 17 Discharge resistor 14, 15 Voltage dividing resistor 16 White level long hold capacitor 18 White level hold signal 19 White Level long hold signal 20 White level signal 21 Video signal 30 White level hold circuit 40 White level long hold circuit 50 Output circuit

Claims (1)

(57) [Claims] 1. A first white level generation circuit for generating a white level hold signal following a white peak level of a video signal, and a second white level generation circuit for generating a white level long hold signal by holding the white level hold signal for a long time. A white level generation circuit, and an output circuit that outputs a signal having a large value among the white level hold signal or the white level long hold signal as a white level signal, wherein the first white level generation circuit includes the video signal Charge the
A first capacitor that discharges the charged signal and
Outputs a white level hold signal that follows the video signal.
The second white level generation circuit is configured to include
A voltage dividing resistor for dividing a signal at a predetermined ratio;
Larger capacity than the first capacitor for charging the signal
The second capacitor and discharge the charged signal to
A second discharge resistor that outputs a bell long hold signal is provided.
White level setting circuit Ete video signal, characterized in that constructed.