JPS62213153A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To control currents between electrodes having a wide facing area, and to prevent the interference of signals between memory cells such as solid capacitor cells by specifying the shape of a groove or stipulating the relationship of substrate concentration, a distance between adjacent grooves, etc., in a memory cell using the side wall section of the groove in an Si substrate as an electrode surface for a capacitor. CONSTITUTION:When the conditions of L>W/2 are satisfied in an interval L with a capacitor oppositely faced to a capacitor 1 in (w) width and (d) depth to the capacitor 1, currents between these two capacitors can be controlled by substrate voltage VBB, and currents can be inhibited at an extremely small value by setting VBB within a proper range. Currents between the capacitors can also be reduced exceedingly by the impurity concentration NB of a layer wrapping a groove shaping the capacitor 1 and by setting the interval under predetermined conditions between the capacitor and the adjacent capacitor. Accordingly, informations between the adjacent capacitors do not interfare, thus normally operating a memory cell.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, particularly a structure in which electrodes face each other over a wide area, for example, to realize a large capacity without increasing the planar area. It relates to semiconductor integrated circuit memory.

[Conventional technology]

As semiconductor integrated circuits become more highly integrated, a structure in which electrodes face each other over a wide area is created. A concrete example of this is the trench capacitor cell of dynamic MOS memory.
Since AM was released, it has quadrupled in scale in three years. However, in conventional planar capacitors, as the scale increases, the signal charge also decreases proportionally, and the S/N
Deterioration of the ratio becomes a major problem. This led to a movement to utilize silicon substrates in three-dimensional form. That is, by using a trench capacitor that uses the side wall portion of a trench dug into a silicon substrate as a capacitor, it has become possible to simultaneously increase the scale of L and maintain the amount of signal charge.

[Problem that the invention seeks to solve]

In such a three-dimensional capacitor, since adjacent cells face each other over a large area, a current called an inter-cell leakage current that is difficult to control flows. Controlling this type of current is a major challenge in realizing three-dimensional capacitor cells.

Note that related devices of this type include, for example, Japanese Patent Application Laid-Open No. 51-130178.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for controlling current between electrodes having a large opposing area and preventing signal interference between, for example, three-dimensional capacitor cells.

[Means for solving problems]

The present invention provides a memory cell in which the side wall of a trench dug into a Si substrate is used as the electrode surface of a capacitor, and the shape of the trench is defined or the relationship between the substrate concentration, the distance between adjacent trenches, etc. is defined. In particular, this is to prevent signals between adjacent capacitors from interfering with each other. As a result, it is possible to increase the electrode area without increasing the side surface area, obtain a desired capacitance, and obtain a highly reliable memory cell that does not malfunction. Note that there was previously an invention, JP-A-59-106146, which defined the relationship between the substrate concentration and the groove distance, but this was a linear approximation of a part of the relationship expressed by a curve. Since the present invention has almost strictly formulated the boundary lines, it can be applied over a wide range of areas, and also includes other conditions such as the shape of the grooves and the voltage between the grooves.
Can be widely applied.

[Effect]

That is, for a capacitor of width W and depth d, when the condition L>- is satisfied in the distance between it and the capacitor facing it, the current between the two capacitors is equal to the substrate voltage VB.
By setting VBB in a suitable range, the current L can be suppressed to an extremely small value.

Also, the impurity concentration N of the layer surrounding the trench forming the capacitor is
The current between the capacitors can also be made extremely small by setting the distance between B and the adjacent capacitors under predetermined conditions.

[Embodiments of the invention]

Hereinafter, a case where the present invention is applied to a trench capacitor in a dynamic RAM will be described.

FIG. 1 shows a block diagram of a trench capacitor.

Common memory cells in dynamic RAM are Si
It is composed of a capacitor formed by sandwiching an insulating film between a substrate and an electrode, and a switching MOS transistor.

Storage is performed depending on whether the charge accumulated in the capacitor is greater or less than a certain value. In the trench capacitor,
A Si substrate is dug and a capacitor 1 is formed on its side wall. The drain of the switching MOS transistor 2 is connected to the bit line 3, and the gate thereof is connected to the word line 4.

A method for manufacturing a groove capacitor will be explained using FIG. 2. First, as shown in FIG. 2(a), a field oxide film 6 is selectively formed on a Si substrate 5 by the LOCO3 method. Thereafter, as shown in FIG. 2(b), L and grooves 7 are formed by parallel plate plasma etching using CF41SF8 as a main component. By controlling etching conditions such as time,
, can dig trenches of any depth. As a mask, 15iOt*5iaN+, CVD5 on a Si substrate.
CVD5iO in the part where a film is formed in the order of iOz and grooves are dug.
z, 5iaNn.

Use etched SL Ox.

Next, as shown in FIG. 2(Q), a capacitor insulating film 8 and a plate 9 are formed. The method for forming these is the same as that for planar capacitors. Polycrystalline Si is used for the plate. Thereafter, a memory cell using a trench capacitor as shown in FIG. 1 is formed in the same manner as a planar capacitor.

The trench capacitor described above utilizes an inversion layer formed on a silicon substrate. Alternatively,
FIG. 3(a) shows an example in which an n-conducting layer is provided along a groove-shaped capacitor and a capacitor is formed between the n-conducting layer and the plate. To form n+Jl on the sidewall, selective diffusion may be performed using a photoetching method or the like. Alternatively, a directional ion implantation method may be used.

If P+ such as B is diffused along the trench before forming the n-conducting layer, H
iC structure can be realized. In other words, the n-conducting layer is surrounded by the p-conducting layer.

The method for manufacturing a trench capacitor has been briefly explained above.

Next, an embodiment in which the present invention is applied to a DRAM cell using a trench capacitor will be described. DR using trench capacitor
In cell A, two trench capacitors face each other and are located close to each other. At this time, depending on one condition, the signals stored in each capacitor may cause interference. The conditions are that the potential of the trench capacitor, the substrate voltage, the shape of the capacitor, the distance between the capacitors, and the concentration profile between the capacitors can be kept below the level necessary for normal operation. Hereinafter, a case where Si as a P substrate is used will be explained. The present invention is also applicable to the case where Si is used as an n-substrate.

[Embodiment 1] A first embodiment of the present invention is shown in FIGS. 4 and 5. Fourth
The length of the channel capacitor shown in the figure is 1 width W, for example 2°μ
m, depth d, for example, is a rectangular parallelepiped of 4 μm, L, and the distance between opposing capacitors is larger than w/2, for example, 1.5
It is μm. At this time, the opposing surfaces of the capacitor are rectangular wXd as shown in FIG. This is S
When folded with respect to the i surface, L becomes a rectangle of wX2d, and the radius r of the largest inscribed circle is w/2. The current can thus be controlled by the substrate voltage VBB. L 1 on the solid line in Figure 6
, 5 p m , w 2 μm , d 4 p
m, capacitor voltage 6V, substrate concentration], 5
101! Icxn-" (1) shows the inter-capacitor current characteristics. By setting the substrate voltage to -4.5 V or less, the inter-capacitor current can be suppressed to the required level of 10"" δA or less.

On the other hand, when L≦−, w=3 μm (broken line in FIG. 6).

As shown by w=4 μm (dotted line in FIG. 6), the current between the capacitors cannot be controlled by the substrate voltage.

In the above embodiments, the relationship between the capacitor width and the distance between the capacitors is defined, but even in a structure where L is larger than the cell depth d as shown in FIGS. 7 and 8, the relationship between the capacitor width and the distance between the capacitors is Can control current. For example, L
In the structure of l, 5μm, w4μm, ・81μm, the current between the capacitors is 10-1'A when the substrate voltage is -465V or less.
I was able to obtain the following.

[Example 2] A second example will be described using FIGS. 9 and 10. In a structure in which the distance between opposing capacitors is L and the substrate concentration is uniform as shown in FIG. L and N where the current is 10-”A
There was a relationship as shown by the solid line in Figure 10.

In other words, g-L=const In the area to the upper right of this solid line, for example, when L=2.0 μm, if a substrate concentration of 2×10”am””8 or more is used, the current between the capacitors can be reduced to 10-”A or less. .

[Example 3] FIG. 11 shows a third example related to the previous example, with a substrate concentration of 1.
Under the condition of substrate voltage -4V, the current between the capacitors is 1
There was a relationship as shown by the solid line in Figure 11 between the capacitor-to-capacitor voltage Vo, which is 0-"aA, and the capacitor spacing. That is, Vo+IVBBl+$ * L=const (φ=0
．． 813V) In the upper left area of this solid line, for example, when door E〒IVei+φ is 2.4, Ll is 6 μm.
By using the above, the current between the capacitors can be reduced to IQ-18A or less.

If the above two embodiments are combined, the current between the capacitors will be 1
It is possible to define a wide range of regions where the temperature is O-18A or less. That is, provided that NAO=1.5
X 10"am-", Lo=2.2um r V n
o = 6 V + V aso = 4 V + φ=O
L, N^y Vo, V to satisfy -813V v
By determining BB, the current between the capacitors can be kept below the level required for normal operation of the memory cell in any case.

[Example 4] A fourth embodiment is shown in FIGS. 12 and 13.

An n-conducting layer is formed along the groove L shown in FIG.

Furthermore, a P conductive layer having a higher concentration than the substrate is formed so as to surround this. This formation of the P conductive layer brings about the same change in the current between the capacitors as if the distance between the capacitors was increased by an amount proportional to the thickness d. The situation is shown in FIG. 13. The slope of the straight line is a function L of the substrate concentration N^ and P÷ layer concentration NB. Combining this result with the above example, we get
In the structure shown in FIG. 12, the inter-capacitor leaf current is set to 10-18 A or less, which is a condition for normal operation of the memory. Namely.

However, NAQ=1, 5×101Bam-”,
Lo=2.2um, Voo=6V, Vano=-4V
, $=0.813VsTo satisfy the above equation, capacitor spacing L, substrate concentration NA, capacitor-to-capacitor voltage o, substrate voltage V a P + 10 layer degree and thickness Na along Bt groove
By setting L and dti, it is possible to obtain a dynamic memory that does not cause signal interference between L and capacitors.

〔Effect of the invention〕

According to the structure of the trench capacitor of the present invention shown above,
Memory cells can operate normally without interference of information between adjacent capacitors.

[Brief explanation of drawings]

Figure 1, Figure 2 (a) (b) (c), Figure 3 @ (a
)(b) is a cross-sectional view showing a groove-shaped shibashita cell, FIG. FIG. 7 is a diagram showing opposing memory cells, FIG. FIG. 8 shows the shapes of opposing surfaces of memory cells; FIG. FIGS. 10, 11, and 13 are diagrams showing characteristics of memory cells, and FIGS. 9 and 12 are sectional views showing adjacent trench capacitors. 1... Capacitor, 2... MOS transistor for switch, 3... Bit line, 4... Word line, 5...
・Silicon, con board, 6...LOCO3, 7...groove,
8...Field oxide film, 9...Plate polycrystalline silicon. Atsushi 1 Figure 'Hz Figure 2 Figure 2 °Schiff interval; Fi,, 7-L (Δ] Figure 7 10 Mouth LolWt)

Claims (1)

[Claims] 1. It has two or more memory cells each having a storage capacitance section and a switching element section provided in a region including the sidewall of a trench dug into a silicon substrate, and the following two conditions are met. For at least one of the grooves adjacent to 1, the radius r of the maximum circle inscribed in the figure obtained by folding the opposing surface against the silicon surface is equal to or less than the interval L between the adjacent grooves; 2. The shape of the groove is arbitrary, and the groove is covered with a layer of the same conductivity type as the substrate and the same or high concentration, and the concentration of the high concentration layer is N_B.
, thickness d, interval L between adjacent grooves, substrate concentration N_A, voltage between grooves V_D, and substrate voltage V_B_B are expressed by the following formula ▲ There are mathematical formulas, chemical formulas, tables, etc. ▼ However, V_D_O = 6V, V_B_B_O = -4V ,
φ=0.813V, L_O=2.2μm, N_A_O=
A semiconductor memory characterized by satisfying at least one of the following conditions: 1.5×10^1^5 cm^-^δ.