JPS62211915A - Method for deposition of conductive thin film - Google Patents
Method for deposition of conductive thin filmInfo
- Publication number
- JPS62211915A JPS62211915A JP5567586A JP5567586A JPS62211915A JP S62211915 A JPS62211915 A JP S62211915A JP 5567586 A JP5567586 A JP 5567586A JP 5567586 A JP5567586 A JP 5567586A JP S62211915 A JPS62211915 A JP S62211915A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electron beam
- deposited
- conductive film
- deposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 8
- 238000000034 method Methods 0.000 title abstract description 5
- 230000008021 deposition Effects 0.000 title abstract description 4
- 238000010894 electron beam technology Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 238000000137 annealing Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005243 fluidization Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、導電薄膜の堆積方法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a method for depositing conductive thin films.
（従来の技術）
従来、半導体装置等の配線用の導電薄膜の堆積法として
は、真空蒸着法やスパッタ法が用いられてきた。(Prior Art) Conventionally, vacuum evaporation and sputtering have been used as methods for depositing conductive thin films for wiring in semiconductor devices and the like.
（発明が解決しようとする問題点）
しかし、これら従来の方法で段差部を有する基板上に堆
積された膜は、段差部において、膜厚が薄くなる、マイ
クロクラックが発生する、オーバーハング構造が発生す
る等、被覆特性が悪く、半導体装置の配線に応用した場
合、歩留りや信頼性の低下の原因になるという問題があ
った。(Problems to be Solved by the Invention) However, films deposited on substrates having stepped portions using these conventional methods have thin film thickness, microcracks, and overhang structures at the stepped portions. When applied to wiring of semiconductor devices, there has been a problem that the coating properties are poor, such as occurrence of oxidation, and that it causes a decrease in yield and reliability when applied to wiring of semiconductor devices.
本発明の目的は、この問題点を解決し、被覆特性の優れ
た導電薄膜の堆積法を提供することにある。An object of the present invention is to solve this problem and provide a method for depositing a conductive thin film with excellent coating properties.
（問題点を解決するための手段）
本発明の要旨とするところは、段差を有する基板上に導
電膜を堆積する途中に堆積された導電膜に電子ビーム照
射加熱を行ない少くとも下地段差部に堆積された導電薄
膜を流動化させるものである。(Means for Solving the Problems) The gist of the present invention is to apply electron beam irradiation heating to the conductive film deposited during the deposition of the conductive film on a substrate having a step, so that at least the underlying step portion is heated. This fluidizes the deposited conductive thin film.
電子ビーム照射加熱は、導電膜の堆積をそのま＼続けな
がら行っても、あるいは堆積な一担中断して行ってもよ
い。また流動化は、導電膜を溶解させて行っても、ある
いは溶解させずに固相での軟化を利用してもかまわない
。The electron beam irradiation heating may be performed while the conductive film is being deposited as it is, or may be performed after the deposition is interrupted. Further, fluidization may be performed by dissolving the conductive film, or by utilizing softening in the solid phase without dissolving it.
（作用）
電子ビーム照射加熱により導電膜が軟化あるいは溶解し
て流動化されるため、段差部における堆積膜の傾斜角が
ゆるやかになる、被覆率が改善される、マイクロクラッ
クが消滅する、といった被覆特性が改善される。(Function) The conductive film is softened or melted and fluidized by electron beam irradiation and heating, so the inclination angle of the deposited film at the step part becomes gentler, the coverage is improved, and microcracks disappear. Characteristics are improved.
（実施例） 以下、図面を用いて本発明の詳細な説明する。(Example) Hereinafter, the present invention will be explained in detail using the drawings.
第１図ｆａｌ〜ｔｅｌは本発明の一実施例を説明する為
の工程順に示した半導体チップの断面図である。FIGS. 1 to 1 are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
第１図１ａ）は、 ＭＯ８型集積回路装置におけるＭＯ
Ｓ ）ランジスタ部の配線形成前の断面図である。第
１図（ａ）においてｌはシリコン基板、２は不純物拡散
層、３はモリブデンシリサイド層、４はゲート電極、５
は層間絶縁膜、６は関ロ≠♀国＝白−Ｅルである。Figure 1 1a) shows the MO in the MO8 type integrated circuit device.
S) A cross-sectional view of the transistor section before wiring is formed. In FIG. 1(a), l is a silicon substrate, 2 is an impurity diffusion layer, 3 is a molybdenum silicide layer, 4 is a gate electrode, and 5 is a molybdenum silicide layer.
is an interlayer insulating film, and 6 is Kanro≠♀country=white-Eru.
次に第１図（ｂ）に示すように、通常のスパッタ法によ
シ、シリコンを１−程度含有したアルミニウム膜７ａを
約０．５μｍの厚さに堆積する。この様に堆積されたシ
リコン含有アルミニウム膜７ａには、開口を久≠傘＝±
６やゲート電極４端上の段差部において、側面被覆率が
悪くかつマイクロクラックやオーバハングが生じている
。Next, as shown in FIG. 1(b), an aluminum film 7a containing approximately 1-1 silicon is deposited to a thickness of about 0.5 .mu.m by a conventional sputtering method. The silicon-containing aluminum film 7a deposited in this manner has an opening for a long time≠umbrella=±
6 and the stepped portions on the ends of the gate electrode 4, the side surface coverage is poor and microcracks and overhangs occur.
次に第１図（Ｃ）に示すように、試料を電子ビームアニ
ール装置内に移して、シリコン含有アルミニウムｌｉ
７ ａに電子ビームを照射して加熱し、１マイクロ秒以
下程度の極めて短時間溶解することにより、オーバハン
グやマイクロクラックが無くなりかつゆるやかな傾斜を
持ったシリコン含有アルミニウム膜７ｂに変形する。Next, as shown in FIG. 1(C), the sample was transferred to an electron beam annealing device and silicon-containing aluminum was heated.
By irradiating and heating the film 7a with an electron beam and melting it in a very short time of about 1 microsecond or less, the silicon-containing aluminum film 7b is transformed into a silicon-containing aluminum film 7b that has no overhangs or microcracks and has a gentle slope.
次に第１図（ｄＪに示すように、再びスパッタ法により
シリコン含有アルミニウムをさらに約０．５μｍ堆積し
、シリコン含有アルミニウムｇ７ｃを形成する。Next, as shown in FIG. 1 (dJ), approximately 0.5 μm of silicon-containing aluminum is deposited again by sputtering to form silicon-containing aluminum g7c.
最後に第１図ｆｉｌに示すように、通常の方法によりこ
のシリコン含有アルミニウム膜７ｃをエツチングするこ
とによりアルミニウム配線７ｄが形成される。Finally, as shown in FIG. 1fil, aluminum wiring 7d is formed by etching silicon-containing aluminum film 7c using a conventional method.
（発明の効果）
以上説明したように本発明は、堆積工程の途中で導電膜
に電子ビーム加熱を行ない導電膜を流動化させるため、
堆積した導電薄膜は、従来の方法による膜に比べて段差
部での被覆特性が著しく改善される。(Effects of the Invention) As explained above, the present invention performs electron beam heating on the conductive film during the deposition process to fluidize the conductive film.
The deposited conductive thin film has significantly improved step coverage properties compared to films produced by conventional methods.
第１図（ａｌ〜ｔｅ＋は本発明の一実施例を説明する為
の工程順に示した半導体チップの断面図である。
１・・・・・・シリコン基板、２・・・・・・拡散層、
３・・・・・・モリブデンシリサイド、５・・・・・・
層間絶縁膜、６・・・・・・開口、７ａ、７ｂ、７ｃ・
・・・・・シリコン含有アルミニウム膜、７ｄ・・・・
・・アルミニウム配線。
・′：″−“）
・゛”ザ）
代理人 弁理士 内 原 晋 ＣＬ；’、ｉＹ１
回FIG. 1 (al to te+ are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention. 1...Silicon substrate, 2...Diffusion layer ,
3...Molybdenum silicide, 5...
Interlayer insulating film, 6...Opening, 7a, 7b, 7c.
...Silicon-containing aluminum film, 7d...
...Aluminum wiring.・′:″−“) ・゛”The) Agent Patent Attorney Susumu Uchihara CL;', iY1
times
Claims (1)
積された導電膜に電子ビーム照射加熱を行ない少くとも
前記段差部に堆積された前記導電膜を流動化させること
を特徴とする導電薄膜の堆積方法。A conductive thin film characterized in that during the course of depositing the conductive film on a substrate having a stepped portion, the deposited conductive film is heated by electron beam irradiation to fluidize at least the conductive film deposited on the stepped portion. Deposition method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5567586A JPS62211915A (en) | 1986-03-12 | 1986-03-12 | Method for deposition of conductive thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5567586A JPS62211915A (en) | 1986-03-12 | 1986-03-12 | Method for deposition of conductive thin film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62211915A true JPS62211915A (en) | 1987-09-17 |
Family
ID=13005455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5567586A Pending JPS62211915A (en) | 1986-03-12 | 1986-03-12 | Method for deposition of conductive thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62211915A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266521A (en) * | 1991-03-20 | 1993-11-30 | Samsung Electronics Co., Ltd. | Method for forming a planarized composite metal layer in a semiconductor device |
| US5534463A (en) * | 1992-01-23 | 1996-07-09 | Samsung Electronics Co., Ltd. | Method for forming a wiring layer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS566434A (en) * | 1979-06-28 | 1981-01-23 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| JPS5797647A (en) * | 1980-12-10 | 1982-06-17 | Toshiba Corp | Forming of electrode wiring in semiconductor device |
-
1986
- 1986-03-12 JP JP5567586A patent/JPS62211915A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS566434A (en) * | 1979-06-28 | 1981-01-23 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| JPS5797647A (en) * | 1980-12-10 | 1982-06-17 | Toshiba Corp | Forming of electrode wiring in semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869902A (en) * | 1990-09-19 | 1999-02-09 | Samsung Electronics Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US5266521A (en) * | 1991-03-20 | 1993-11-30 | Samsung Electronics Co., Ltd. | Method for forming a planarized composite metal layer in a semiconductor device |
| US5534463A (en) * | 1992-01-23 | 1996-07-09 | Samsung Electronics Co., Ltd. | Method for forming a wiring layer |
| US5589713A (en) * | 1992-01-23 | 1996-12-31 | Samsung Electronics Co., Ltd. | Semiconductor device having an improved wiring layer |
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