JPS62208711A - Dual timer circuit - Google Patents

Abstract

PURPOSE:To realize two timer functions by a few hardwares by providing two timer registers holding independently timer information respectively and using a circuit means such as +1 addition in time division between two timers in common. CONSTITUTION:The 1st timer register 11 and the 2nd timer register 12 are registers holding two counts required to realize the 1st and 2nd two independent timer functions and connected in a loop via a processing circuit 13. Each timer information is transferred cyclicly from the 1st timer register 11 to the 2nd timer register 12 and vice versa via a processing circuit 13 at a period T/2 being a half of the clock period T in the loop. In this case, the information is subject to +1 addition or no addition by the processing circuit 13. Thus, the processing circuit 13 is operated in time division and the first half and the latter half period of each clock period are assigned to the 1st timer and the 2nd timer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] By sharing circuit means such as +1 addition between two timers in a time-sharing manner, two timer functions are realized with a small amount of hardware.

(Industrial Application Field) The present invention relates to a timer circuit, and particularly to a dual timer circuit having two independent timer functions.

[Conventional technology]

Generally, there are many devices, such as timing control circuits used in multi-systems, that require dual timers to be provided and operated independently using the same clock.

Conventionally, in such cases, each timer is usually configured as a completely independent circuit. FIG. 6 shows one example.

In FIG. 6, 60 and 60' are timer circuits having the same configuration. Due to duplication, the timer circuit 60.6
0' is represented by 60 to explain the circuit function, 61
is a timer register (represented by TM-1), 62 is a +1 adder that adds 1, and 63 is a parity check circuit (P, C
, 64 is a +1 control signal, 65 and 66 are A
ND circuit.

67 is an OR circuit, 68 is an NOT circuit, and t represents the value of timer information in timer register TM-1.

The basic operation of the timer circuit is based on the value L of timer register TM-1.
This is a counter operation in which 1 is read out, +1 is added by the +1 adder 62, and sequentially updated.

Since the value is counted up every clock, it can be used as any timer by monitoring the value.

The AND circuits 65 and 66, the OR circuit 67, and the NOT circuit 68 collectively constitute a selection circuit, and the output of the +1 adder 62 (tl
+1) and write to timer register TM-1, or select the output of timer register TM-1 and write +
1 adder 62 is bypassed, and the content tI of timer register TM-1 is rewritten as is.

The parity check circuit 63 includes a timer register TM-1.
Performs a parity check on the output value.

Prevents malfunction of the timer circuit.

By turning on the +1 control signal 64, the timer circuit 60 performs a count amplification operation for each clock with one period T clock.

For each clock, the value of timer register TM-1 is 1. is checked by parity check circuits p and c, and also inputted to the +1 adder 62. +1 control signal 64 is ON
When the output of the AND circuit 65 is the value t, +l, AND
The output of the circuit 66 has a value of 0, and the output of the OR circuit 67 has a value of t1+1. As a result, timer register T after synchronization T
The value of M-1 is t,+1.

When the +1 control signal 64 is OFF, the output of the AND circuit 65 is 0, the output of the AND circuit 66 is t,
Then, the output of the OR circuit 67 becomes the value t1. The readout of timer register TM-1 after period T is t. This is the timer register TM-2 of the timer circuit 60'.
The same is true for.

[Problem that the invention seeks to solve]

Conventionally, when there are two timers with the same function,
In order to operate each independently, it is necessary to separately provide a +1 adder circuit and a parity check circuit, which causes an increase in the amount of hardware.

[Means for solving problems]

The present invention reduces the overall amount of hardware by converting two timer circuits into a single circuit and by sharing circuits with the same function used by the two timers as much as possible to the extent that independence can be maintained. It was planned.

FIG. 1 shows the basic configuration of the double timer circuit of the present invention.

In FIG. 1, 11 is a first timer register.

12 represents a second timer register, 13 represents a processing circuit, 14 represents a parity check circuit, and 15 represents a composite +1 control signal.

The first timer register 11 and the second timer register 12 are
These are registers that hold two pieces of timer information (specifically, count values) necessary to realize the functions of the first and second two independent timers, and are connected in a loop through the processing circuit 13. has been done. Each timer information is transferred from the first timer register 11 to the second timer register 12 via the processing circuit 13 in a loop with a cycle T/2, which is half the clock cycle T, and from the second timer register 12 to the first timer register 11. 19, the processing circuit 13 adds +1 or does not add +1. Therefore, the value of each timer register goes through the loop in one cycle T, and is updated by +1 (count amplifier) or not updated.

Therefore, the processing circuit 13 operates in a time-division manner.

The first and second timers are assigned the first and second half periods of each clock period.

The parity check circuit 14 includes a second timer register 12
Performs a parity check on the sequential timer information output from the .

The composite +1 control signal 15 adds +1 to each of the first and second timer information input to the processing circuit 13.

This is a signal that individually instructs non-addition.

[Effect]

In FIG. 1, the composite +1 control signal 15 that controls the processing circuit 13 is applied to each of the first and second timers at the time-division operation timing of the processing circuit 13, that is, during the first half and second half of the clock period T. This corresponds to the +1 control signal.

1 is added to the timer information input from the first timer register 11 to the processing circuit 13 during T/2x, 11 when the composite +1 control signal 15 is ON, and the result is written into the second timer register 12.

On the other hand, nothing is added to the timer information manually input to the processing circuit 13 during the T/2 period when the composite +1 control signal 15 is OFF, and the timer information is written into the second timer register 12 as is.

This control is performed for each clock period T(
..., TM-1, TN, TN-1, TN+□,
), the timer information is sequentially applied to the timer information of the first timer and the second timer that appear alternately in units of T/2.

In this way, within one timer circuit, the timer information of two timers is shared with the common processing circuit 13 at a unique timing.
The signal is inputted to , and is subjected to +1 addition or non-addition processing in a two-time division format.

〔Example〕

FIG. 3 shows the configuration of one embodiment of a double timer circuit according to the present invention.

In the figure, 11 is a first timer register, 12 is a second timer register, 13 is a processing circuit, 14 is a parity check circuit, and 15 is a composite +1 control signal.

16 is a +1 adder, 17.18 is a multiplexer.

19 is the first timer +1 control signal, 20 is the second timer +1
The control signal 21 is a clock pulse with a period T and a pulse duty of 50%.

Note that the elements indicated by 11 to 15 in FIG. 3 are the same as the elements with the same numbers in FIG. 1. Also tl+
tZ is the first. Indicates the value of timer information of the contents of the second timer register.

In the processing circuit 13, the value of the first timer register 11 is increased by +1 adder 16 and multiplexer 1 every T/2.
7.

The other input of the multiplexer 17 has a +1 adder 16
The outputs t, +l are given.

The multiplexer 17 operates as a selection circuit that selects either tl or j++1, and outputs the composite +1 control signal 15.
is ON, t, +1, and OFF, 1. controlled to select.

The output of the multiplexer 17 (ie, the output of the processing circuit 13, t, +1 or tl) is transferred to the second timer register 12 and written therein.

At this time, the value t2 that was previously in the second timer register 12 is simultaneously checked by the parity check circuit 14 and transferred to the first timer register 11 and written therein.

The multiplexer 18 alternately selects the first timer +1 control signal 19 and the second timer +1 control signal 20 every T/2 to generate the composite +1 control signal 15 .

The value of the first timer register 11 is 1. and the value t2 of the second timer register 12 after T time, respectively.

It takes a +1 updated value or a non-updated value, and its combinations result in four types of states (■ to ■) shown in the cubic table.

The multiplexer 18 outputs four types of composite +1 control signals shown by ■ to ■ in FIG. 4 according to the states ■ to ■ in the table above.

FIG. 5 shows the operation sequence of the double timer circuit controlled by the composite +1 control signals ■ to ■ shown in FIG.
0), (after T/2), and (after T). In the figure, 11 represents a first timer register, 12 represents a second timer register, and 13 represents a processing circuit. +0. shown in the processing circuit 13. +1 indicates the selected function. Also, j+ + is attached to each timer register.
2, "l+1+t2+1, etc., indicate the contents of the timer register at that point in time.

〔Effect of the invention〕

According to the present invention, two timers can be compactly configured in a single circuit with a smaller amount of hardware than two independent timer circuits, and the device can be downsized, reduced in cost, and improved in reliability. I can do it.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle configuration of the present invention, FIG. 2 is a timing diagram of timer information processing of the first and second timers, FIG. 3 is a diagram of the configuration of one embodiment of the present invention, and FIG. An explanatory diagram of the composite +1 control signal in the embodiment shown in the figure, FIG.
The operation sequence diagram of the embodiment shown in FIG. 6 is a block diagram of a conventional timer circuit. In Figure 1. 11: First timer register 12: Second timer register 13: Processing circuit 14: Parity check circuit 15: Composite +1 control signal

Claims (1)

[Claims] A first timer register (11) and a second timer register (12) each holding independent timer information, and a process of adding +1 or not adding to input data according to instructions from a control signal. The first timer register (11), the processing circuit (13) and the second timer register (12) are connected in a loop and are operated at a constant cycle by a clock. During the first half of the clock period, the first timer register (
The timer information in 11) is passed through the processing circuit (13) to the second
At the same time, the timer information in the second timer register (12) is transferred to the first timer register (11), and in the second half of each clock cycle, the first timer information is transferred to the timer register (12) in the same way as above. Each timer information is transferred between the timer register (11) and the second timer register (12), and the information is transferred from the first timer register (11) to the processing circuit (13) for each period of the first half and second half of the clock cycle. ) A double timer circuit is characterized in that a control signal is applied to individually instruct either +1 addition or non-addition processing for each piece of timer information input into the circuit.