JPS62208669A - Contact structure and formation thereof - Google Patents

Abstract

PURPOSE:To improve a contact by forming a wiring layer on a buried region which has a gentle slope recess-like step difference except only the side wall left by etching of a thin and laminated layer of polycrystalline silicon laminated on a buried layer W. CONSTITUTION:The first conductive material (tungsten layer) 4 selectively made of a refractory metal is partially buried in a contact hole by vapor growth using a silicon substrate 1 formed in the contact hole. Then, the second conductive material of polycrystalline silicon 5 is laminated on all the surface by vapor growth and a recess like side wall 8 is left in the contact hole by etching. Then, the contact hole is buried and a wiring layer is formed by forming the Al wiring layer 6 on the two layer conductive materials 4, 5. This enables obtaining a good contact in a high density integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] As the degree of integration of integrated circuits increases, conditions for height differences in contact holes formed on a substrate become increasingly strict. In order to maintain good contact, a method will be described in which refractory metal is partially buried in the contact hole, and a concave sidewall is formed using polycrystalline silicon to alleviate the step difference, and then a wiring layer is formed.

[Industrial application field]

The present invention relates to a contact structure for an integrated circuit and a method for forming the same.

In high-density integrated circuits, the relationship between the height and width of a contact hole opened on a substrate is extremely strict, and if a wiring layer is formed directly in the contact hole, step coverage will be poor.

Therefore, in order to alleviate the step difference, a method has been adopted in which a conductive material is buried in the contact hole to improve step coverage.

The present invention aims to solve the problems in the method of embedding a conductive material.

[Conventional technology]

A conventional method of filling contact holes in a high-density integrated circuit will be explained with reference to FIGS. 2fa) to 2Fdl.

FIG. 2(a) shows a state in which a tungsten layer (W layer) 4 is selectively embedded in a contact ball 3 formed in an insulating film 2 of a silicon substrate 1. As shown in FIG.

The growth of W is performed by a reduced pressure vapor phase growth method using a mixed gas of WF6, N2, and N2. Growth can be performed at a low temperature of about 300° C., and growth proceeds selectively only in exposed contact holes of silicon on the substrate.

However, the thickness of the selective growth of W mentioned above is limited to 5,000 layers, and if it is grown beyond that, there will be no selectivity. Therefore, in the case of an integrated circuit with an insulating film thickness of about 1 μm, large steps will still remain. It will be done.

FIG. 2 (bl) shows a state in which polycrystalline silicon 5 is grown in a vapor phase over the entire surface in order to flatten the stepped portion. Monosilane gas (SiH4) is used for growth at a temperature of approximately 700°C.

In order to completely fill and flatten the contact hole,
It is necessary to grow approximately 1 μm thick polycrystalline silicon.

FIG. 2 (C1 shows the state where planarization was performed by anisotropic etching (tE) using CCβ4+02 gas.

In addition, it is necessary to dope impurities to lower the resistance value of polycrystalline silicon, and there are methods such as introducing impurity gas when forming a polycrystalline silicon film, or ion implantation after forming a non-doped polycrystalline silicon film. A method of introducing impurities is applied.

Therefore, p for bipolar transistors.

Both n contacts require separate implantation of impurities, and it is necessary to selectively perform ion implantation in two steps.

After the contact hole filling and planarization step as described above, the Al wiring layer 6 shown in FIG. 2fdl is formed.

[Problem that the invention seeks to solve]

In the conventional method described above, it is necessary to form a thick stack of polycrystalline silicon, and furthermore, it is necessary to remove most of this thick polycrystalline silicon film by etching for planarization.

Furthermore, another problem is that when performing ion implantation, the impurity is W.
It is also conceivable that it penetrates through the layer and diffuses into the element formation region of the underlying silicon substrate, adversely affecting the characteristics.

[Means for solving problems]

The above problem is solved because the polycrystalline silicon to be laminated on the W buried layer is made into a thin layer and is etched to leave only the sidewalls and buried with a gentle concave step, and then the wiring layer is formed on top of this. This problem is solved by the contact structure and method for forming the same according to the present invention.

That is, in the structure, a first conductive material made of refractory metal is partially embedded in the contact hole,
A second conductive material of polycrystalline silicon forming a concave side wall portion is buried on the first conductive material, and a contact structure is formed in which a wiring layer is formed on the two layers of conductive material. .

Further, the method for forming the contact hole uses a silicon substrate in which a contact hole is formed, and selectively embeds a first conductive material made of refractory metal into the contact hole by vapor phase growth.

Next, a second conductive material of polycrystalline silicon is deposited over the entire surface by vapor phase growth, and a concave sidewall portion is left in the contact hole by etching. By forming a wiring layer on the two layers of conductive material, the contact hole is filled and the wiring layer is formed.

[Effect]

In the present invention, in order to simplify the process of embedding the second conductive material and etching, thin polycrystalline silicon is laminated and etched to form a shallow hole with a concave sidewall remaining.

As a result, although the contact hole is not planarized, the wiring layer laminated thereon has a sufficiently good stethoscope coverage.

The Aρ wiring layer partially contacts the W layer directly at the center of the contact hole. Furthermore, polycrystalline silicon can be turned into a silicide by heat treatment before forming a wiring layer, and the resistance can be lowered without particularly requiring implantation of impurities.

〔Example〕

An embodiment according to the present invention will be described in detail with reference to the drawings. Explanation of the same reference numerals as those used in the prior art section will be omitted.

FIGS. 1A to 1C are cross-sectional views showing the contact hole filling method of the present invention in the order of steps.

In FIG. 1(ta), the steps up to filling the contact hole 3 with the W layer 4 are the same as the method explained in the section of the prior art.

Next, about 20% of polycrystalline silicon 5 is grown using the same vapor phase growth method.
00 to 4,000 people in thickness. Since the polycrystalline silicon layer is thin, a depression 7 is formed on the top surface of the contact hole, and a relatively thick polycrystalline silicon layer is laminated on the sidewall 8 of the contact hole.

Next, as shown in FIG. 1(b), anisotropic etching is performed using CC24+Oz gas to remove the polycrystalline silicon layer on the insulating film 2, and at the same time, the W layer is partially exposed in the contact hole and the sidewalls are removed. In this case, polycrystalline silicon is left in a concave shape.

Next, heat treatment at 800° C. is performed to silicide the polycrystalline silicon layer.

FIG. 1C shows a state in which a 7B wiring layer 6 is formed after the double-layer contact hole filling process is performed.

In the above embodiments, an example was explained in which W was used as the first conductive material, but similar effects can be expected when Mo or other adhesive flux metals are used.

〔Effect of the invention〕

As explained above, the contact structure and the method for forming the same of the present invention can provide a good contact in a high-density integrated circuit, contributing to improved cheek confidence.

[Brief explanation of drawings]

1+8j to tc) are step-by-step cross-sectional views showing a contact forming method according to the present invention, and FIG. In the figure, (2) is a silicon substrate, 2 is an insulating film, 3 is a contact ball, 4 is a tungsten layer, 5 is polycrystalline silicon, 6 is an Aρ wiring layer, 7 is a recess, and 8 is a side wall portion.

Claims (2)

[Claims] (1) A first conductive material (4) made of refractory metal is partially embedded in the contact hole (3),
A second conductive material (5) of polycrystalline silicon forming a concave side wall portion (8) is buried on the first conductive material, and a wiring layer (6) is formed on the two layers of conductive material. ) is formed. (2) In the silicon substrate (1) in which the contact hole (3) is formed, a first conductive material (4) made of refractory metal is selectively buried in the contact hole by vapor phase growth. a step of laminating a second conductive material (5) of polycrystalline silicon on the entire surface by vapor phase growth, and leaving a concave side wall portion (8) in the contact hole by etching; A contact forming method comprising the step of forming a wiring layer (6) on the contact forming method.