JPS62208147A - Expansion address converter - Google Patents

Abstract

PURPOSE:To shorten an address conversion time by selecting an entry coinciding with the longest part of virtual addresses out of an entry group registered in a converting buffer device and outputting one table in a head converting table group or a real address. CONSTITUTION:An instruction part 101 read from a main memory device 400 is supplied from an instruction analysis control part 100 to an instruction execution part 200 and a virtual address 2 calculated by an address calculating part 210 is outputted to an address conversion part 230. The conversion table having hierarchical structure for converting the address 2 into a real address is stored in the device 400 and specified by a register 1 in a control register control part 240. The leading address group of the conversion table is stored in the conversion buffer 20 together with the pair of the virtual address and the real address and the entry coinciding with the longest part of the virtual address is selected from the entry group registered in the buffer 20 by a level determining/selecting circuit 30. One head conversion table out of the head conversion table group or the real address is outputted in accordance with the coincident length, so that the conversion time can be shortened.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a translation buffer device for performing address translation from a virtual address to a real address at high speed. The present invention relates to an address translation device suitable for speeding up translation processing when used.

[Background of the invention]

Traditionally, the hierarchical structure of address translation tables for translating virtual addresses to real addresses is described in the IBM manual; System 370 Principles.
of 0operation (G A 22-700
0-8) Dynamic Address Tra
Two stages have been used, as shown in the section on nslation.

However, when the virtual address is expanded from 31 bits to a wide range (for example, 64 bits), a two-level hierarchical structure is insufficient, and it is natural to use a multi-level hierarchical structure of about five levels. The reason for this is that if address expansion were to be carried out in two stages, the number of required entries for the translation table would be enormous, and a large contiguous memory area would need to be secured for the translation table. By doing so, it is possible to reduce the memory area that must be consecutively secured.

However, a disadvantage of using multiple stages is that processing performance deteriorates when the corresponding entry does not exist in the conversion buffer provided to speed up the conversion. 2
In the case of stages, two memory requests are issued, whereas in the case of five stages, five memory requests are required.

[Purpose of the invention]

An object of the present invention is to reduce the number of references to a multi-stage address translation table group that is performed when there is no entry matching a virtual address to be translated in a translation buffer device provided for speeding up address translation. An object of the present invention is to provide an address translation device that reduces the time required for translation.

[Summary of the invention]

Since only pairs of virtual addresses and real addresses are registered in conventional translation buffer devices, if translation fails, address translation must be started from the highest translation table. The address of the translation table at each stage is also recorded in each entry of the address translation buffer, and there is no need to access the translation table up to the portion where the virtual addresses match, thereby improving the translation speed. Moreover, the addresses of the conversion tables at each stage are read during the process of conversion, so they do not add any load.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

FIG. 1 shows the configuration of an information processing device to which the present invention is applied, which is composed of the following.

(1) Command analysis/control unit 100 Decodes command words and controls other parts of processing.

(2) Command Execution Unit 200 This is a unit in charge of executing command words, and is a unit to which the present invention is applied.

(3) Memory control unit 300 Controls data transfer with the main storage device (MS) 400.

The above configuration is a common one.

Next, the configuration inside the instruction execution unit 200 to which the present invention is applied will be described.

(1) Address calculation unit 210 This is the part that calculates the virtual address.

(2) General-purpose register control unit 220 This is a part that controls reading from and writing to a plurality of general-purpose registers 221.

(3) Address conversion unit 230 This is a unit that converts the virtual address created by the address calculation unit 210 into a real address.

(4) Control Register Control Unit 240 This is a unit that controls reading from and writing to a plurality of control registers 241. In this embodiment, number 1 of the control registers is used for address translation.

Since the above configuration is a general one, a detailed explanation will be omitted, but the flow of instruction word processing will be explained based on this figure, and the position of address conversion will be described.

The operation code (OP) in the instruction word 101 read from the MS 400 is decoded, the type of instruction is recognized, and each part in the instruction word is extracted. B in imperative word
2L+X2. Calculate the address of the operand based on the D2 part. Specifically, (a) the contents of part 82 in the instruction word are transmitted to the general-purpose register control unit 220, the general-purpose register specified by B2 is read out, and the Bz register data 2 is read.
Set to 11. (b) Similarly to Ca'l, a value is set in the x2 register data 212 corresponding to the X2 part.

(C) D in the command word! The contents of par 1- are set in the Dz data register 213. (d) Address adder 21 that receives three inputs: Bz register data 211, Xz register data 212, and D2 data register 213.
4, the addition is performed and the result is stored in the address register 21.
Set to 5. This content is called a virtual address, and the role of the address translation unit 230 is to translate this into an actual address (real address) on the MS.

The details will be described later, but as a result, the real address is set in the translation address register 232. The contents of the translation address register 232 are stored in the memory control unit 3.
MS address register 30] in M
Used for fetch or store operations for S400.

The flow of instruction word processing and the role of the address translation unit 230 therein have been described above.

FIG. 2 shows the structure of an address translation table that translates virtual addresses into corresponding real addresses.

The address translation table is stored within the MS 400. In this embodiment, the virtual address is 64 bits 1~, and the virtual address is divided into the following six sets.

(1) BL part (2) B2 part (3) B3 part (4) S part (5) P part (6) D part Control 1 no register 1 indicates the start address of the conversion table group formed by the PI groove structure on the 1st floor used for 8 of the contents of the 81st part of the virtual address is added to the contents of control register 1.
The value obtained by adding the multiplied value is the address of the entry corresponding to the B1 part, and this entry includes the start address of the conversion table for the B2 part. B2 in the virtual address is added to the start address of the conversion table for B2 part.
The value obtained by adding 8 times the value of the content of the part is the address of the entry corresponding to the B2 part, and the entry contains the following:
Contains the start address of the B3 part conversion table. Thereafter, in the same manner, the start address of the S-part conversion table and the start address of the P-part 1- conversion table are obtained. The entry corresponding to the contents of the P part in the P part conversion table includes a real page number (RP N).

The value obtained by concatenating the RPN and Dpar1- in the virtual address becomes the real address corresponding to the virtual address.

In addition, in the above process, there is an invalid bit in the lower part of each translation table entry, and when it is 1, it is assumed that the virtual address is not allocated to real memory, and an address translation exception is generated. A program interrupt occurs.

Next, the flow of address conversion processing will be explained using FIG.

(1) Find the longest part of the translation buffer that matches the virtual address, counting from the top. A circuit for this purpose is shown in FIG. In the figure, the conversion buffer has multiple sides. Each plane stores multiple entries. Some bits in the virtual address are compressed by compressor 4.
0, input to each side of the conversion buffer 20, and compressed contents 42 of the position specified by the bit 41.
is output on each side. The bit compressor 40 is preferably configured with a hash circuit (known in the art), for example. Also,
A readout control circuit that outputs a plurality of outputs in response to one input is well known, so its details will be omitted. Their outputs 10 become inputs to the selection circuit 30. The selection circuit 30 selects the longest matching virtual address from the top.

FIG. 5 shows a selection circuit constituting the main part of address translation processing by a translation buffer to which the present invention is directly applied. One entry 10 of the conversion buffer includes 10 types of primary information.

(a) 81 part of virtual address (b) 82 part of virtual address (c) B3 part of virtual address (d) S part of virtual address (e) P part of virtual address (f) Start address of B2T table (g ) 83T table start address (h) ST child table start address (i) PT child table start address (j) Real page number for virtual address RPN The comparison between the virtual address to be converted and the conversion buffer entry is as follows. will be implemented. That is, the virtual address and the corresponding five parts in the translation buffer entry are respectively
41C5x8, and if they match, ON is output, and if they do not match, OFF is output. The five output signal lines are input to a decoder DEC16. One of the outputs of the decoder DEC16 is used as selection information for the selector 5EL17. Another output of the decoder DEC16 is used as output level code information. The relationship between the values of the five input lines of the decoder DEC and the output information 18 is as shown in the pronation table.

All the output information 18 on each side of the conversion buffer is input to the minimum output level selection circuit 19, and as a result, the entry having the minimum output level is selected. FIG. 6 shows the configuration of the minimum output level selection circuit 19. In this figure, the output level 18a and constants '0' to 15' are compared.

Following the comparison result signal line 31, the contents of the output information 18 are transmitted to the input of the selector 33 via the selector 32. On the other hand, each output signal line 35 of the OR circuit 36 indicates whether there is an output level 0 to 5. This output signal line 35 is operated by a NOT circuit 36 and an AND circuit 37 to turn on at most one of the selection signal lines 38 of the selector 33 and turn off the others. At this time, if the one with a lower output level is turned on, the selection signal line 38 with a higher output level is turned off. In this way, one of the selectors 33 is selected and the output information 232 is outputted via the register 34.

(2) Whether the output level of the selected entry is 0 or not;
Check by 0 comparator 80. If it is 0, it means that the corresponding entry has been found, and the process ends as address translation is successful.

(3) If the output level is not 0, set the output level 31 and output address 32 to work register 1 (33), j(
34) respectively, and perform the following processes (4) to (8).
repeat.

(4) Part selection signal 92 obtains information on the corresponding part in the virtual address according to the value of register 1 (33), and sets it in work register k (35). For example, if the output level is 2, the contents of the S part in FIG. 5 are set in register k (35).

(5) The address calculation unit 81 reads 8B of data 302 from the memory using the sum of eight times the contents of register k (35) and the contents of register j as an address. Then, the contents are set in register j (34) and are input to the merge circuit 21 for setting the value in the write entry data register 22 to the conversion buffer 20.

The merge circuit 21 sets the address part of the corresponding part in the entry data register 22 according to the value of register 1 (33).

(6) Invalid bit in read data
Check whether is 1. If it is 1, control is passed to the program interrupt process and the process ends.

(7) If not 1, register i (output level) (3
Subtract 1 from 3).

(8) If register i (33) is not 0, process (4)
)go to.

(9) If register 1 (33) becomes 0, it means that the address conversion was successful. In that case, processing is performed to register it in the conversion buffer. That is, a conventionally known replacement algorithm 70 is used to determine the entry position to be registered.

(10) Then, the contents of the entry data register 22 are written to the determined end position, and the address conversion process is completed. The information written consists of the following:

CB>virtual address pi, B2. B3. S and P parts.

(b) B2T table, B3T table, ST child table PT child table each start address, these information are (
These are the information up to the valid level of the information 23 included in the entry selected in 1), and the information sequentially read out in (5).

One embodiment of the present invention has been described above. In this example, 64
Although we have described an example in which a bit virtual address is divided into six parts, it should be noted that the present invention can easily be applied to virtual addresses of other lengths or when the method of division is changed.

According to this embodiment, address translation can be processed at high speed when the virtual address to be translated is not found in the translation buffer device. In this example, 5 memory references can be reduced to 1 to 5 times.

〔Effect of the invention〕

According to the present invention, in each entry of the conversion buffer device,
The start address of each stage of the hierarchical translation table is included, and the entry closest to the virtual address to be translated can be obtained from the translation buffer, so the entry whose position address completely matches the translation buffer is If not found, the start address of the conversion table for each stage recorded in the entry closest to it can be used. As a result, there is an effect that the speed of address translation processing when there is no corresponding entry in the translation buffer can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing device to which the present invention is applied; FIG. 2 is a diagram showing the hierarchical structure of an extended virtual address to which the present invention is effectively applied and a conversion table for converting it to a real address; Figure 3 shows the flow of address conversion processing, Figure 4 shows the overall configuration of the conversion buffer, Figure 5 shows the configuration of the entries in the conversion buffer, and Figure 6 shows the entry with the longest matching address. FIG. 7 is an explanatory diagram of the operation of the decoder 16 shown in FIG. 5. 1... Control register for address conversion, 2...
Virtual address, 3-7... Conversion table, 8... Converted real address, 10... Conversion buffer entry, 11-], 5...-Number comparator, 16... Decoder , 17...Selector, 18...Conversion buffer output, 20...Conversion buffer, 30...Selection circuit, 40...42 Eye 3 Eye Qin 4 Mouth

Claims (1)

[Claims] Conversion from a virtual address to a real address is performed using a hierarchically structured address conversion table group, and a plurality of pairs of virtual addresses and real addresses corresponding to the virtual addresses are stored in order to speed up the address conversion. An information processing device having a conversion buffer device, comprising: a conversion buffer device for recording a start address group of a conversion table in each layer of the layered conversion table group together with the pair of virtual address and real address; Select the entry whose virtual address matches the longest part among the entries registered in the device, and select either one of the head translation table group or the real address recorded in the entry depending on the matching length. An extended address translation device characterized in that it is provided with a device for outputting an address.