JPS62208137A - Image processor - Google Patents

Abstract

PURPOSE:To detect visually and simply in which step an error is generated and to improve debugging by setting up break addresses in a sequential register at the debugging of various image processing, and writing data obtained on the way to arithmetic processing in an image memory and displaying the data. CONSTITUTION:When the debugging processing of an image is started, a microprogram 110 is traveled and an original image stored in a source memory 112 is affine-transformed on the basis of cubic convolution method and stored in a destination memory 113. If a break address is not set up in a register 108, the processing is continued as it is to obtain a final result. When the break address is set up, an equal condition signal is inputted from a comparator 109 to the program 110 and the program starts a debugging routine. When a break is generated in the final processing result, the break address is set up and the intermediate result (data) is written in an image memory.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image processing device, and in particular, to an image processing device that can perform complex image processing such as affine transformation and spatial filtering under firmware control, and can easily debug the firmware. The present invention relates to an image processing device.

[Conventional technology]

Conventionally, image processing devices using firmware control read data from one image memory, calculate coefficients and addresses, and perform two processes.
A series of processes in which data read from the image memory is processed and the final result is returned to the image memory are executed using a microprogram or a microphone o=y repeater.

[Problem that the invention seeks to solve]

In the case of the above-mentioned conventional firmware maj-controlled image processing device, when there is an error in the final result, the most important part of the processing is stored in the image memory, and the correctness or error is determined. Therefore, it is not possible to determine where in the program processing the error is occurring or whether the error is due to hardware malfunction. In order to make such a determination, it is necessary to sequentially check the progress of the process using a debugging tool such as an analyzer or tracer that can display numerical values of registers, addresses, etc. in the device. However, with this method, there is a huge amount of 2-image data, and even if the contents of internal registers and addresses are displayed numerically using a debugging tool, it is not possible to determine correctness or incorrectness at a glance from a list of numerical values. The drawback is that it takes a lot of time to check everything.

An object of the present invention is to provide an image processing device that eliminates the above-mentioned drawbacks.

[Failure to solve the problem]

The image processing device of the present invention includes a first register file that latches addresses necessary for accessing one image memory;
a second register file for latching image data values;
an arithmetic unit used for address calculations and data calculations, a multiplier used for data calculations, at least two latches for providing data to the arithmetic unit and the multiplier, and storing intermediate values and instructions/programmers. the microprogram controller, a register for latching a break address for debugging, and a comparator for comparing the contents of the register with the microprogram from the microprogram controller; The control unit is characterized by having a microprogram in which a debug routine for writing intermediate results of processing into the image memory is incorporated into the processing routine.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

The image processing device of the present invention allows debugging of general-purpose image processing such as affine transformation, spatial filtering, and inter-image operations using simple hardware and firmware.

As an example of the present invention, a complex affine transformation cubic con? The operation will be explained using fusion processing as an example.

FIG. 2 is a diagram showing the principle of affine transformation using the cubic congolution method. In the figure, 201 is the original image stored in the source memory that undergoes affine transformation;
02 is a destination memory area to be converted, and has a size of M in the X direction and N in the Y direction. 203
is an enlarged view of 201 and 202. In 203.

To find air using the cubic convolution method, equation (204) can be used.

Ixy=ADD/T However, FIG. 1 is a block diagram of an embodiment of the present invention. 101 is a first register file that latches addresses necessary for accessing the image memory; 102 is a second register file that latches image data; 1.03 is an arithmetic unit (ALU) used for address calculation and data calculation; 1.04
is a multiplier used for data operations.

105 is two latches that provide data to the ALU 103 and the multiplier 104, and 106 is a scratch memo IJ (RAM) that stores intermediate values, instruction parameters, etc.
), lQ 7 is a microprogram controller (microprogram sequencer), 108 is a register for setting a break address, 109 is a comparator that compares the program address specified in register 108 with the current program address, 110 is a comparator 109 This is a microprogram with an added debug routine that writes the intermediate results of the calculation to the image memory when the conditions are equal. 111 is a microprogram control section having a microprogram controller 107 and a microprogram 110; Further, 112 is a source memory, and 113 is a destination memory. When processing starts, program 11
0 runs and executes equation (204) according to the flow shown in FIG. If the break address is not set in the register 108, the process continues as it is and returns to step 401 in FIG.
The final processing result is obtained. If the break address is set, the equal condition signal from the comparator 109 is 11.
0, the program enters the debug routine.

In the present invention, here, a data distortion as shown in 402 in FIG. 4 occurs in the final processing result.

In the middle of the coefficient calculation of "DD", a break address is set and the intermediate result is written to the image memory.For example, in FIG. 3, suppose that an abnormality occurs at step (p+m+1).As the break address, (p+m) address is set, the coefficient (-L+2L-L)X(-L'-1-
The calculation result of 2L -L) will be a normal pattern with no scratches like 403 in Figure 4.91Next, if you set the break address to the address (p+m+1) where the next process ends, the coefficient (- L+2L2-L3)X
The calculation result of (1-2L'2-t-L") is 4 in Figure 4.
It becomes a scratched pattern like 04, and it can be seen at a glance that there is an error in this calculation step. In this way, by setting break addresses one after another and writing and displaying the data in the middle of processing to the image memory, you can easily find in which step an error has occurred at a glance, and use a special debugging tool. do not need.

This example is an example of debugging image processing using the Haffin transform cubic composition method.

Similarly, various image processing such as spatial filters and inter-image operations can be easily debugged.

〔Effect of the invention〕

As explained above, in the case of image processing, the present invention generally
Even complex coefficients become regular geometric patterns when displayed two-dimensionally, so when debugging various types of image processing, break addresses are set and data in the middle of processing is written to image memory.

indicate. As a result, abnormalities in load coefficients and other coefficients can be easily detected visually, resulting in a significant improvement in debugging efficiency compared to the method of checking numerical values using a normal debugging tool.

In addition, the written coefficients and intermediate results used in the calculation can depend on the image memory, so if you import them into the host computer, you can know the address of the image memory where the error occurred and the image data value as numerical values. /reactor.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image processing device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining affine transformation of key-big congolution, and FIG. 3 is a flowchart of fine transformation processing according to the present invention. FIG. 4 is a diagram showing an example of image data obtained by the image processing apparatus of the present invention. 101...First register file, 102...Second register file, 103... Arithmetic unit (ALU)
). 104... Multiplier, 105... Two sets of latches, 10
6... Scratch memory, 107... Microprogram controller, 108... Register, 109... Comparator. 110... Micro program, 111... Micro program control unit, 112... Source memory, 1
13...Destination memory. Figure 2 Figure 4

Claims (1)

[Claims] 1. A first register file that latches addresses necessary for accessing the image memory, a second register file that latches image data values, an arithmetic unit used for address calculations and data calculations, and an arithmetic unit used for data calculations. a multiplier, at least two latches for providing data to the arithmetic unit and the multiplier, a scratch memory for storing intermediate values and instruction parameters, a microprogram control unit, and latching break addresses for debugging. It has a register and a comparator that compares the contents of the register with the microprogram from the microprogram control unit, and the microprogram control unit executes a debug routine that writes intermediate results of processing to the image memory as a processing routine. An image processing device comprising a microprogram incorporated into the image processing device.