JPS62208006A - Optical integrated circuit - Google Patents
Optical integrated circuitInfo
- Publication number
- JPS62208006A JPS62208006A JP5036986A JP5036986A JPS62208006A JP S62208006 A JPS62208006 A JP S62208006A JP 5036986 A JP5036986 A JP 5036986A JP 5036986 A JP5036986 A JP 5036986A JP S62208006 A JPS62208006 A JP S62208006A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- optical
- waveguide layer
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 title claims description 48
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000005253 cladding Methods 0.000 claims description 4
- 239000013078 crystal Substances 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000001947 vapour-phase growth Methods 0.000 abstract description 3
- 239000000470 constituent Substances 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000013307 optical fiber Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
- G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
- G02B6/122—Basic optical elements, e.g. light-guiding paths
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Optical Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体基板上に、半導体発光素子、受光素子、
導波路などを結晶成長により形成した光集積回路の構造
に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a semiconductor light-emitting device, a light-receiving device,
This field relates to the structure of optical integrated circuits in which waveguides and the like are formed by crystal growth.
光フアイバ通信の普及に伴ない、半導体基板上に、半導
体発光素子、受光素子、光スィッチ、光変調素子などの
光機能素子や、光分岐素子、光合分波素子、導波路など
の受動素子を一体化形成するいわゆる光集積回路の研究
が検討されるようになってきた。この光集積回路の重要
な課題は、できる限り簡易な構成で、−貫プロセスによ
り量産できるようにすることである。上記課題に対する
一つの解決法として、第1図に示す方法が提案されてい
る(特開昭59−90981号公報)、これは同図(a
)に示すように、光の伝搬方向に垂直な方向に延びる段
差を形成した半導体基板1上に、(b)に示すように活
性導波路3と受動導波路5を段差の両側で前記活性導波
路及び前記受動導波路の光軸が一致するように中間層を
介して連続して形成し、ついで、(C)に示すように、
前記各導波路および中間層のうち、前記半導体基板の段
差の上方の部分を除去して前記活性導波路及び受動導波
路に互いに略平行に対向した溝面を形成するようにした
ものである。連続的な結晶成長により実現できるという
特徴があり、経済化を期待できる。ところが実際に試作
して見ると次のような問題点があることがわかった。(
a)の半導体基板は面8の部分をエツチング技術でけず
りとって作らなければならないが、面8の部分は面9の
部分に比し、数倍以上も広いため1面8を平担に高寸法
精度で作ることは極めて困難であることがわかった。こ
の面8の部分の寸法精度が悪くなると、面8上に形成す
る光導波路、光変調器、光スィッチなどの性能に悪影響
を及ぼし、十分な特性のものが得られないことがわかっ
た。すなわち1面9上に形成する光デバイスの数に比し
1面8上に形成する光デバイスの数が数倍以上も多いの
で、面8上の寸法精度を面9上のそれよりもはるかに高
精度にしなければならず、第1図(a)のような基板構
造では光デバイスの高性能化がむずかしいことがわかっ
た。さらに、エツチングでけずりとる側の端面側33の
端部がきれいに形成できないために、この端部に光ファ
イバを接続して光信号を伝送させる場合に、光結合効率
が大幅に低下することがわかった。With the spread of optical fiber communication, optical functional elements such as semiconductor light emitting elements, light receiving elements, optical switches, and optical modulation elements, as well as passive elements such as optical branching elements, optical multiplexing/demultiplexing elements, and waveguides, are being mounted on semiconductor substrates. Research into so-called integrated optical integrated circuits has begun to be considered. An important challenge for this optical integrated circuit is to make it as simple as possible and mass-produce it using a through-process. As one solution to the above problem, the method shown in Figure 1 has been proposed (Japanese Unexamined Patent Publication No. 59-90981).
), an active waveguide 3 and a passive waveguide 5 are placed on the semiconductor substrate 1 on which a step extending in a direction perpendicular to the light propagation direction is formed, and an active waveguide 3 and a passive waveguide 5 are placed on both sides of the step, as shown in FIG. The waveguide and the passive waveguide are formed continuously through an intermediate layer so that their optical axes coincide, and then, as shown in (C),
Among the waveguides and the intermediate layer, portions above the step of the semiconductor substrate are removed to form groove surfaces substantially parallel to each other and facing each other in the active waveguide and passive waveguide. It has the characteristic that it can be realized by continuous crystal growth, and is expected to be economical. However, when we actually produced a prototype, we found the following problems. (
The semiconductor substrate in a) must be made by etching the surface 8 part, but since the surface 8 part is several times wider than the surface 9 part, one surface 8 is made flat and high. It turned out to be extremely difficult to manufacture with dimensional accuracy. It has been found that if the dimensional accuracy of this surface 8 portion deteriorates, it will adversely affect the performance of optical waveguides, optical modulators, optical switches, etc. formed on surface 8, making it impossible to obtain sufficient characteristics. In other words, since the number of optical devices formed on one surface 8 is several times greater than the number of optical devices formed on one surface 9, the dimensional accuracy on surface 8 is much higher than that on surface 9. High precision is required, and it has been found that it is difficult to improve the performance of optical devices with the substrate structure shown in FIG. 1(a). Furthermore, it has been found that because the end of the end face side 33 on the side to be etched cannot be formed neatly, when an optical fiber is connected to this end to transmit an optical signal, the optical coupling efficiency is significantly reduced. Ta.
本発明の目的は前記従来の問題点を解決させることので
きる光集積回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an optical integrated circuit that can solve the above-mentioned conventional problems.
すなわち、高精度、高性能の半導体発光素子、受光素子
、受動導波路を連続的な結晶成長により製造できる光集
積回路の構造にあり、また低コスト化も期待できる。In other words, the structure of the optical integrated circuit is such that high-precision, high-performance semiconductor light-emitting devices, light-receiving devices, and passive waveguides can be manufactured by continuous crystal growth, and cost reduction can also be expected.
本発明は、半導体、強誘電体、磁性体などの基板上に、
半導体発光素子、受光素子、光合分波素子、光変調素子
、光スイツチ素子などを形成して光集積回路を構成する
に際して、半導体発光素子。The present invention provides for a substrate such as a semiconductor, a ferroelectric material, a magnetic material, etc.
Semiconductor light emitting devices are used when constructing optical integrated circuits by forming semiconductor light emitting devices, light receiving devices, optical multiplexing/demultiplexing devices, optical modulation devices, optical switch devices, etc.
受光素子を形成する部分の基板部をエツチングによりけ
ずって段差部を設け、該基板上にバッファ層、受動導波
路層、中間層、活性導波路層、クラッド層を活性導波路
層と受動導波路層とが段差の両側で対向するように順次
連続的な結晶成長゛させた後1段差部近辺を基板の垂直
方向にエツチングして溝部を形成させ、あらかじめ基板
をけずった部分を半導体発光素子、受光素子として、残
りの部分を光合分波素子、光変調素子、光スイツチ素子
などを含む受動導波路として作用させるものである。The part of the substrate where the light receiving element will be formed is etched to form a stepped part, and the buffer layer, passive waveguide layer, intermediate layer, active waveguide layer, and cladding layer are formed on the substrate to form the active waveguide layer and the passive waveguide. After continuous crystal growth is performed in order so that the layers face each other on both sides of the step, a groove is formed by etching in the vertical direction of the substrate in the vicinity of the first step, and a semiconductor light emitting device is formed using the previously scratched portion of the substrate. As a light receiving element, the remaining portion acts as a passive waveguide including an optical multiplexing/demultiplexing element, an optical modulation element, an optical switch element, etc.
第2図(a)、(b)、(Q)に本発明の光集積回路に
用いる基板の実施例を示す、10は基板であり、たとえ
ば、半導体基板(InP、GaAgなど)を用いる。1
1,12.13は上記基板1oに設けた段差部であり、
エツチング(たとえば、ウェットエツチング、ドライエ
ツチング)により形成する。16は基板10の水平面、
15は上記水平面16に対して垂直の面からなる垂直面
、14も16と略垂直な面である。11は水平面16と
平行な面を有する段差部である。12は水平面16に対
して角度θlだけ傾いた面を有する段差部である。この
OLは14側よりも15側の方が低くなるように形成し
た角度である。13は水平面16に対して角度θ2だけ
傾いた面を有する段差部であるが、この02は15側が
14側よりも高くなるように形成した角度である。段差
部11゜12.13の面上には半導体発光素子、あるい
は半導体発光素子と受光素子が形成される。これに対し
て水平面16上には受動導波路以外に、光変調素子、光
スイツチ素子、光合分波素子などが形成され、11,1
2.13の部分の面積よりも数倍以上も広い面積を有し
ている。また水平面16は平担で表面あらさも小さいも
のが要求されるが、第2図のような構造であると、第1
図に比して非常に良好な特性が得られるという利点があ
る。すなわち、水平面16はあらかじめ精度の良い基板
を用いればよく、しかも、端部33側もあらがじめ垂直
端面が得られているので、光ファイバとの結合も容易で
ある。θ1.θ2.なる傾斜角をもたせた理由は第1図
(Q)において、半導体レーザの活性導波路層3からの
出射光7が受動導波路層5の入力部で反射して半導体レ
ーザの活性層導波路3へもどってこないようにするため
である。2(a), (b), and (Q) show examples of substrates used in the optical integrated circuit of the present invention. Reference numeral 10 denotes a substrate, and for example, a semiconductor substrate (InP, GaAg, etc.) is used. 1
1, 12, and 13 are stepped portions provided on the substrate 1o,
It is formed by etching (eg, wet etching, dry etching). 16 is a horizontal surface of the substrate 10;
15 is a vertical surface perpendicular to the horizontal surface 16, and 14 is also a surface substantially perpendicular to 16. Reference numeral 11 denotes a stepped portion having a surface parallel to the horizontal surface 16. Reference numeral 12 denotes a stepped portion having a surface inclined at an angle θl with respect to the horizontal surface 16. This OL is an angle formed such that the 15 side is lower than the 14 side. 13 is a stepped portion having a surface inclined at an angle θ2 with respect to the horizontal plane 16, and 02 is an angle formed such that the 15 side is higher than the 14 side. A semiconductor light emitting device, or a semiconductor light emitting device and a light receiving device are formed on the surfaces of the step portions 11°12.13. On the other hand, on the horizontal plane 16, in addition to the passive waveguide, an optical modulation element, an optical switch element, an optical multiplexing/demultiplexing element, etc. are formed.
It has an area several times larger than the area of the part 2.13. In addition, the horizontal surface 16 is required to be flat and have a small surface roughness, but if the structure is as shown in FIG.
This has the advantage that very good characteristics can be obtained compared to the figure. That is, it is sufficient to use a highly accurate substrate for the horizontal surface 16 in advance, and since a vertical end surface is already obtained on the end portion 33 side, coupling with an optical fiber is also easy. θ1. θ2. The reason for having such an inclination angle is that in FIG. 1 (Q), the emitted light 7 from the active waveguide layer 3 of the semiconductor laser is reflected at the input part of the passive waveguide layer 5, and This is to prevent them from returning.
第3図(a)および(b)は本発明の光集積回路の製造
方法および構造の実施例を示したものである。まず同図
(a)から説明する。第2図(a)で示した基板(In
P)10上にInPバッファ層17を形成する。その上
にInGaAsP受動導波路層18を形成し、ついで、
InP中間層19を、その上にInGaAsP活性導波
路層20を、そして最後にInPクラッドJjfJ21
を形成する6層17から21までは連続した気相成長に
より形成できる。なお、InGaAsP活落導波路層2
0とInGaAsP受動導波路層18は対向するように
、段差部11の深さ、バッファ層17および中間層19
の厚みは、あらかじめ設定される。第3図(a)の段差
境界部をドライエツチングして、同図(b)のごとく溝
部22を形成させ、半導体レーザ23と受動導波路24
を得る6なお、端面15側もエツチングにより22のよ
うな溝部を形成して共振端面を構成してもよい。この溝
部22の形成により、半導体レーザ23の共振端面が得
られ、もう一方の端面15との間でレーザ発振した光信
号は矢印25のごとく出射し、受動導波路18内を伝搬
していく。FIGS. 3(a) and 3(b) show an embodiment of the method and structure for manufacturing an optical integrated circuit according to the present invention. First, explanation will be given from FIG. The substrate (In
P) Form an InP buffer layer 17 on the layer 10. An InGaAsP passive waveguide layer 18 is formed thereon, and then,
InP intermediate layer 19, InGaAsP active waveguide layer 20 thereon, and finally InP cladding JjfJ21.
The six layers 17 to 21 forming the above can be formed by continuous vapor phase growth. Note that the InGaAsP active waveguide layer 2
The depth of the stepped portion 11, the buffer layer 17 and the intermediate layer 19 are such that the InGaAsP passive waveguide layer 18 and the InGaAsP passive waveguide layer 18 face each other.
The thickness of is set in advance. The step boundary shown in FIG. 3(a) is dry-etched to form a groove 22 as shown in FIG. 3(b), and the semiconductor laser 23 and passive waveguide 24 are
Note that the end face 15 side may also be etched to form a groove like 22 to form a resonant end face. By forming this groove portion 22, a resonant end face of the semiconductor laser 23 is obtained, and an optical signal lased between it and the other end face 15 is emitted as shown by an arrow 25 and propagated within the passive waveguide 18.
受動導波路部24には、この図では示してないが。The passive waveguide section 24 is not shown in this figure.
実際には光合分波素子、光変調素子、光スイツチ素子な
どが構成され、半導体レーザ部23の面積よりも数倍以
上も広い面積を有する。In reality, it includes an optical multiplexing/demultiplexing element, an optical modulation element, an optical switching element, etc., and has an area several times larger than the area of the semiconductor laser section 23.
第4図(a)および(b)は本発明の光集積回路の別の
実施例を示したものである。同図(a)は溝部26の両
側端面27,28をそれぞれθ8゜0番なる角度だけ傾
斜させて変動導波路層18からの反射光を半導体レーザ
部23の活性導波路層19へもどさせないようにしたも
のである。反射雑音の低減に有効である。また半導体レ
ーザ23の共振条件を変える効果もあり、たとえば、分
布帰還型や分布反射型レーザの動的均一モード化に有効
である。同図(b)は活性導波路層19が受動導波路層
18のほぼ中間に位置するように対向させ、活性導波路
層19からの出射光29を効率よく受動導波路層18内
に結合させるようにしたものである。FIGS. 4(a) and 4(b) show another embodiment of the optical integrated circuit of the present invention. In the figure (a), both side end faces 27 and 28 of the groove portion 26 are inclined by an angle of θ8°0 to prevent the reflected light from the variable waveguide layer 18 from returning to the active waveguide layer 19 of the semiconductor laser portion 23. This is what I did. Effective in reducing reflected noise. It also has the effect of changing the resonance conditions of the semiconductor laser 23, and is effective, for example, in making a distributed feedback type or distributed reflection type laser into a dynamic uniform mode. In the figure (b), the active waveguide layer 19 is opposed to the passive waveguide layer 18 so that it is located approximately in the middle, and the emitted light 29 from the active waveguide layer 19 is efficiently coupled into the passive waveguide layer 18. This is how it was done.
第5図(a)および(b)は本発明の光集積回路の製造
方法およびその構成の実施例を示したものである。この
場合は第2図(a)の11の部分の面積を若干広くとっ
て、それぞれの層を連続的に気相成長させ、同図(b)
のように、2カ所の溝部22.31を形成させたもので
ある。そして23は半導体レーザ部、30は半導体レー
ザの出射光32をモニタするための受光素子部として作
用させる。FIGS. 5(a) and 5(b) show an embodiment of the method for manufacturing an optical integrated circuit according to the present invention and its structure. In this case, the area of part 11 in Fig. 2(a) is set slightly larger and each layer is grown in a continuous vapor phase, as shown in Fig. 2(b).
As shown in the figure, two grooves 22 and 31 are formed. The reference numeral 23 serves as a semiconductor laser section, and the reference numeral 30 serves as a light receiving element section for monitoring the emitted light 32 of the semiconductor laser.
以上のように本実施例によれば、半導体レーザ部、受光
素子部、受動導波路部24を連続的に気相成長により形
成させることができる。そのため、低コスト化が可能で
あり、また受動導波路部を形成する基板上面16が平担
で表面あらさも小さくできるので、この部分に種々の機
能をもった高性能光デバイスを形成することが可能とな
る。As described above, according to this embodiment, the semiconductor laser section, the light receiving element section, and the passive waveguide section 24 can be continuously formed by vapor phase growth. Therefore, costs can be reduced, and the top surface 16 of the substrate that forms the passive waveguide section is flat and surface roughness can be reduced, making it possible to form high-performance optical devices with various functions in this area. It becomes possible.
本発明は上記実施例に限定されない。たとえば。The present invention is not limited to the above embodiments. for example.
半導体レーザ部は分布帰還型や分布反射型レーザを形成
させてもよい。The semiconductor laser section may be a distributed feedback type or distributed reflection type laser.
本発明によれば、高精度、高性能の半導体発光素子、受
光素子、受動導波路を連続的な結晶成長により製造する
ことができる。その結果、量産が可能であり、低コスト
化を達成させることができる。According to the present invention, highly accurate and high-performance semiconductor light emitting devices, light receiving devices, and passive waveguides can be manufactured by continuous crystal growth. As a result, mass production is possible and cost reduction can be achieved.
第1図は従来の光集積回路の製造方法の概略図。
第2図は本発明の光集積回路に用いる基板の実施例を示
す図、第3図および第5図は本発明の光集積回路の製造
方法およびその構造の実施例を示す図、第4図は本発明
の光集積回路の実施例を示す図である。
1.10・・・基板、2,17・・・バッファ層、3゜
20・・・活性導波路層、4,19・・・中間層、5゜
18・・・受動導波路層、6,21・・・クラッド層、
7゜25.29’、32・・・光の伝搬方向を示す矢印
、8゜11,12,13・・・段差部、9,16・・・
水平面部、14.15・・・垂直面、23・・・半導体
レーザ部、24・・・受動導波路部、22,26,31
・・・溝部、27.28・・・側端面e
、、 、−t、代理人 弁理士 小川勝
馬”・20.゛′−(−
第 3 図
(a−ジ
(b)
η
Y 4 図
(a−)
(b)
茗 5 図
(L)
(b)FIG. 1 is a schematic diagram of a conventional method for manufacturing an optical integrated circuit. FIG. 2 is a diagram showing an embodiment of the substrate used in the optical integrated circuit of the present invention, FIGS. 3 and 5 are diagrams showing an embodiment of the method of manufacturing the optical integrated circuit and its structure, and FIG. 1 is a diagram showing an embodiment of an optical integrated circuit according to the present invention. 1.10...Substrate, 2,17...Buffer layer, 3゜20...Active waveguide layer, 4,19...Intermediate layer, 5゜18...Passive waveguide layer, 6, 21... cladding layer,
7゜25.29', 32...Arrow indicating the direction of light propagation, 8゜11, 12, 13...Stepped portion, 9,16...
Horizontal surface part, 14.15... Vertical surface, 23... Semiconductor laser part, 24... Passive waveguide part, 22, 26, 31
...Groove, 27.28...Side end surface e
,, ,-t, Agent Patent Attorney Katsuma Ogawa"・20.゛'-(- Figure 3 (a-ji (b) η Y 4 Figure (a-) (b) Mayo 5 Figure (L) (b )
Claims (1)
つて段差部を設け、この基板上にバッファ層、受動導波
路層、中間層、活性導波路層及びクラッド層を、この活
性導波路層と受動導波路層とが段差部の両側で対向する
ことを特徴とする光集積回路。 2、特許請求の範囲第1項において、前記段差部の近辺
を上層部から基板に向かつて垂直方向にエッチングされ
た溝部を形成し、前記活性導波路層と受動導波路層とが
互いに略平行に対向した端面を形成していることを特徴
とする光集積回路。 3、特許請求の範囲第1項において、前記けずりとつた
基板上面に傾斜を有することを特徴とする光集積回路。 4、特許請求の範囲第2項において、前記基板をけずり
とつた部分に形成した層に、この層と垂直方向に少なく
とも1つの溝部を形成していることを特徴とする光集積
回路。[Claims] 1. The upper surface of the substrate where the semiconductor optical device is to be formed is cut to provide a stepped portion, and a buffer layer, a passive waveguide layer, an intermediate layer, an active waveguide layer, and a cladding layer are formed on this substrate. , an optical integrated circuit characterized in that the active waveguide layer and the passive waveguide layer face each other on both sides of a stepped portion. 2. In claim 1, a groove portion is formed in the vicinity of the step portion by vertical etching from the upper layer toward the substrate, and the active waveguide layer and the passive waveguide layer are substantially parallel to each other. An optical integrated circuit characterized by forming an end face facing the. 3. The optical integrated circuit according to claim 1, characterized in that the top surface of the chipped substrate has a slope. 4. The optical integrated circuit according to claim 2, wherein at least one groove is formed in the layer formed in the cut portion of the substrate in a direction perpendicular to the layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5036986A JPS62208006A (en) | 1986-03-10 | 1986-03-10 | Optical integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5036986A JPS62208006A (en) | 1986-03-10 | 1986-03-10 | Optical integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62208006A true JPS62208006A (en) | 1987-09-12 |
Family
ID=12856972
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5036986A Pending JPS62208006A (en) | 1986-03-10 | 1986-03-10 | Optical integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62208006A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01277204A (en) * | 1988-04-28 | 1989-11-07 | Shimadzu Corp | Optical waveguide element structure and photomask |
-
1986
- 1986-03-10 JP JP5036986A patent/JPS62208006A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01277204A (en) * | 1988-04-28 | 1989-11-07 | Shimadzu Corp | Optical waveguide element structure and photomask |
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