JPS62207074A - Video mixer-amplifier - Google Patents

Video mixer-amplifier

Info

Publication number
JPS62207074A
JPS62207074A JP4854786A JP4854786A JPS62207074A JP S62207074 A JPS62207074 A JP S62207074A JP 4854786 A JP4854786 A JP 4854786A JP 4854786 A JP4854786 A JP 4854786A JP S62207074 A JPS62207074 A JP S62207074A
Authority
JP
Japan
Prior art keywords
signal
circuit
border
input
wipe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4854786A
Other languages
Japanese (ja)
Other versions
JPH065918B2 (en
Inventor
Yuichi Koyama
小山 裕一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4854786A priority Critical patent/JPH065918B2/en
Publication of JPS62207074A publication Critical patent/JPS62207074A/en
Publication of JPH065918B2 publication Critical patent/JPH065918B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To provide two pieces of multiplier circuits and to enable an adder circuit to border-wipe with two-input addition by providing a switch circuit that receives and switches plural video signals, a key signal processing circuit, the first and the second multiplier circuits, and an adder circuit. CONSTITUTION:Under a border-wipe-ON control, the input video signal of the first multiplier circuit 3 is such a one that an input signal A and that B are switched at the boundary of a wipe-signal S1, while the input video signal to the second multiplier circuit 4 is an input signal BC. In the circuit 3, the video signal in which the input signals A and B are switched and a key signal that is generated by inversing a border signal, are multiplied. In the circuit 4, a border color signal (input signal BC) and a border signal S2 are multiplied. And the results of said two multiplications are added by the adder circuit 5, to obtain a picture by border-wiping the input signal A and that B.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はテレビジョン映像混合増幅器に係り、特にワイ
プおよびボーダーワイプを行や場合の映像混合増幅器に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television video mixing amplifier, and more particularly to a video mixing amplifier for use in wiping and border wiping.

〔従来の技術〕[Conventional technology]

従来のこの種の映像混合増幅器の一例を第4図に示し説
明すると、図において、A、B、BCは複数の映像信号
でらる入力信号、Slはワイプ信号、Ssはボーダー信
号、S4は出力映像信号である。
An example of a conventional video mixing amplifier of this type is shown in FIG. 4. In the figure, A, B, BC are input signals consisting of a plurality of video signals, Sl is a wipe signal, Ss is a border signal, and S4 is a border signal. This is the output video signal.

そして、11はワイプ信号Stおよびボーダー信号S愈
ヲ入力としキー信号の処理を行うキー信号処理回路、1
2,13.14は入力信号A、B、BCを入力とし乗算
を行う第1.第“2.第3の乗算回路で、上記キー信号
処理回路11で処理されたキー信号によって第1.第2
.第3の乗算回路12,13.14でキーイングし、加
算回路15でこれら第1〜第3の乗算回路12〜14の
3つの出力を金床することでワイプおよびボーダーワイ
プを行い、加算回路15の出力側に出力映像信号S4ヲ
得るように構成されている。
A key signal processing circuit 11 receives the wipe signal St and the border signal S and processes the key signal;
2, 13, and 14 are the first digits that receive input signals A, B, and BC and perform multiplication. The 2nd and 3rd multiplication circuits use the key signals processed by the key signal processing circuit 11 to
.. The third multiplier circuits 12, 13, and 14 perform keying, and the adder circuit 15 anvils the three outputs of the first to third multiplier circuits 12 to 14 to perform wipe and border wipe. It is configured to obtain an output video signal S4 on the output side of the .

このキー信号処理回路11の出力キー信号の波形および
入力ワイブ信号、入力ボーダー信号の波形を第5図、第
6図に示す。
The waveforms of the output key signal, input wide signal, and input border signal of this key signal processing circuit 11 are shown in FIGS. 5 and 6.

この第5図はボーダーワイプ時を示したものであり、第
6図はワイプ時を示したものである。
FIG. 5 shows the border wipe, and FIG. 6 shows the wipe.

そして、それぞれ@)は入カワイブ信号を示し、IP>
)は入力ボーダー信号、←)は第1の乗算回路12用キ
一信号、に)は第2の乗算回路13用キ一信号、色)は
第3の乗算回路14用キ一信号をそれぞれ示す。
And, respectively @) indicates an incoming active signal, and IP>
) indicates the input border signal, ←) indicates the key signal for the first multiplication circuit 12, 2) indicates the key signal for the second multiplication circuit 13, and color) indicates the key signal for the third multiplication circuit 14, respectively. .

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の映像混合増幅器では、ワイプ時には第3
の乗算回路は使用しているという問題点があり、また、
第1および第2の乗算回路用のキー信号を得る場合には
、キー信号処理回路でワイプ信号とボーダー信号の演算
が必要であるという問題点があった。
In the conventional video mixing amplifier described above, the third
There is a problem that the multiplication circuit of
In order to obtain the key signals for the first and second multiplier circuits, there is a problem in that the key signal processing circuit needs to calculate the wipe signal and the border signal.

〔問題点を解決するための手段〕[Means for solving problems]

本発明による映像混合増幅器は、複数の映像信号を入力
としてこれらの切替を行なう切替回路と、ワイプ信号と
ボーダー信号およびボーダーワイプ制御信号を入力とし
て上記切替回路の制御を行うと共にキー信号の処理を行
うキー信号処理回路と、上記切替回路およびキー信号処
理回路からの信号を受け乗算を行う第1の乗算回路およ
び第2の乗算回路と、この第1および第2の乗算回路の
出力?加算し出力映像信号を得る加算回路と全備えてな
るようにしたものである。
The video mixing amplifier according to the present invention includes a switching circuit that receives a plurality of video signals and performs switching between them, and a wipe signal, a border signal, and a border wipe control signal that are input to control the switching circuit and process key signals. A key signal processing circuit that performs multiplication, a first multiplication circuit and a second multiplication circuit that receive signals from the switching circuit and the key signal processing circuit, and outputs of the first and second multiplication circuits? It is designed to include an adder circuit that performs addition and obtains an output video signal.

〔作用〕[Effect]

本発明においては、ボーダーワイプ時にはワイプ境界は
ボーダー信号によってキーイングされて画面出現われな
いという点に着目し、ワイプ時には乗算回路を用いて2
つの画面の合成を行い、ボーダーワイプ時には切替回路
で2つの画面の合成をし、乗算回路でボーダ一部分の処
理を行う。
In the present invention, we focus on the fact that the wipe boundary is keyed by the border signal and does not appear on the screen when wiping a border, and when wiping, we use a multiplication circuit to
When wiping a border, a switching circuit combines the two screens, and a multiplication circuit processes a portion of the border.

〔実施例〕〔Example〕

以下、図面に基づき本発明の実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below based on the drawings.

第1図は本発明による映像混合増幅器の一実施例を示す
ブロック図である。
FIG. 1 is a block diagram showing an embodiment of a video mixing amplifier according to the present invention.

この第1図において第4図と同一符号のものは相当部分
を示し、1は複数の映像信号でおる入力信号A、B、B
Ci入力としてこれらの切替を行う切替回路、2はワイ
プ信号Slとボーダー信号Stおよびボーダーワイゲ制
御僅号Ssk入力として上記切替回路1の制御を行うと
共にキー信号の処理を行うキー信号処理回路、3および
4は上記切替回路1およびキー信号処理回路2からの信
号を受け乗算を行う第1の乗算回路および第2の乗算回
路、5はこの第1および第2の乗算回路3,4の出力を
加算し出力映像信号S4f:得る加算回路である。
In FIG. 1, the same reference numerals as in FIG.
2 is a key signal processing circuit that controls the switching circuit 1 and processes the key signal as an input of a wipe signal Sl, a border signal St, and a border weige control signal Ssk; 3; 4 is a first multiplier circuit and a second multiplier circuit that receive signals from the switching circuit 1 and the key signal processing circuit 2 and perform multiplication, and 5 adds the outputs of the first and second multiplier circuits 3 and 4. This is an adder circuit that obtains the output video signal S4f.

つぎにこの第1図に示す実施例の動作を第2図。Next, FIG. 2 shows the operation of the embodiment shown in FIG. 1.

第3図を参照して説明する。This will be explained with reference to FIG.

この第2図、第3図は第1図の動作説明に供する各部の
信号波形を示した図である。第2図はワイプ時を示した
ものでおり、第3図はボーダーワイプ時を示したもので
ある。そして、第2図において&)は入カワイブ信号を
示し、←)は入力ボーダー信号、(ハ)は第1の乗算回
路3用キ一信号、に)は第2の乗算回路4用キ一信号を
示し、第3図において0)は人カワイブ信号、(ロ)は
入力ボーダー信号、(ハ)は第1の乗算回路3に入力す
る映像信号を切替えるための切替信号、に)は第1の乗
算回路3用キ一信号、←)は第2の乗算回路4用キ一信
号をそれぞれ示す。
FIGS. 2 and 3 are diagrams showing signal waveforms of various parts to explain the operation of FIG. 1. FIG. 2 shows the state at the time of wiping, and FIG. 3 shows the state at the time of border wipe. In FIG. 2, &) indicates an input cute signal, ←) indicates an input border signal, (c) indicates a key signal for the first multiplier circuit 3, and (n) indicates a key signal for the second multiplier circuit 4. In Fig. 3, 0) is the human cute signal, (b) is the input border signal, (c) is the switching signal for switching the video signal input to the first multiplier circuit 3, and 2) is the first The key signal for the multiplier circuit 3 and ←) indicate the key signal for the second multiplier circuit 4, respectively.

まず、初めに、ワイプを行う場合の各部の動作を第2図
を参照して説明する。
First, the operation of each part when performing a wipe will be explained with reference to FIG.

ボーダーワイプ制御信号S3はボーダーワイプOFFと
いう制御をキー信号処理回路2にあたえ、このキー信号
処理回路2より切替回路1金制御して、第1の乗算回路
3に入力信号Aシよび第2の乗算回路4に入力信号81
fcそれぞれ出力するように制御を行う。また、キー信
号処理回路字ではワイプ信号Sxt入力として第1の乗
3!回路3にワイプ信号、第2の乗算口jl&4にその
ワイプ信号の反転を与える(第2図杓、←)参照)。そ
して、この第1および第2の乗算回路3,4では、これ
らキー信号によってキーイングを行い、加算回路5で加
算することにより、入力信号Aと入力信号Bのワイプが
行なえる(第2図参照)。
The border wipe control signal S3 gives border wipe OFF control to the key signal processing circuit 2, and the key signal processing circuit 2 controls the switching circuit to send the input signal A to the first multiplier circuit 3 and the second Input signal 81 to multiplier circuit 4
Control is performed to output each fc. In addition, in the key signal processing circuit, the first power 3! is used as the wipe signal Sxt input. A wipe signal is applied to the circuit 3, and the inverse of the wipe signal is applied to the second multiplication port jl&4 (see Figure 2, ←). The first and second multiplier circuits 3 and 4 perform keying using these key signals, and the addition circuit 5 adds the input signals to wipe the input signal A and input signal B (see Figure 2). ).

つぎに、ボーダーワイプ時の動作を第3図を参照して説
明する。
Next, the operation during border wipe will be explained with reference to FIG.

まず、ボーダーワイプONという制御によりキー信号処
理回路2でワイプ信号Sl’に用いて乗算回路に入力さ
れる映像信号の切替を行う切替信号t発生する。すなわ
ち、第1の乗算回路3の入力映像信号は、ワイプ信号S
1の境界で入力信号Aと入力信号Bが切替えられた信号
となり、第2の乗算回路4の入力映像信号は、入力信号
BC(ボーダーカラー信号)となる。
First, by controlling border wipe ON, the key signal processing circuit 2 generates a switching signal t that is used as the wipe signal Sl' to switch the video signal input to the multiplication circuit. That is, the input video signal of the first multiplication circuit 3 is the wipe signal S.
The input signal A and the input signal B are switched at the boundary of 1, and the input video signal of the second multiplication circuit 4 becomes the input signal BC (border color signal).

つぎに、第1の乗算回路3では、上記入力信号Aと入力
信号Bが切替えられた映像信号とボーダー信号を反転し
たキー信号が乗算される。そして、第2の乗算回路4で
はボーダーカラー信号(入力信号BC)とボーダー信号
S3が乗算される。そして、これら2つの結果を加算回
路5で加算することによって、入力信号Aと入力信号B
iボーダーワイプした画面が得られる。
Next, in the first multiplication circuit 3, the video signal obtained by switching the input signal A and the input signal B is multiplied by a key signal obtained by inverting the border signal. Then, in the second multiplication circuit 4, the border color signal (input signal BC) is multiplied by the border signal S3. Then, by adding these two results in the adder circuit 5, the input signal A and the input signal B are
You can get a screen with i-border wiped.

なお、上記実施例においては、入力信号Aと入力信号B
の2人力の切替を行う場合を例にとって説明したが、本
発明はこれに限定されるものではなく、切替を行うため
のワイプ信号をキー信号処理回路2に追加すると共に、
切替回路1に入力信号を追加することによって、複数の
映像信号である入力信号を切替えて、これにボーダーを
付けることもできる。
Note that in the above embodiment, input signal A and input signal B
Although the description has been given by taking as an example the case where two-manpower switching is performed, the present invention is not limited to this, and a wipe signal for performing switching is added to the key signal processing circuit 2.
By adding an input signal to the switching circuit 1, it is also possible to switch the input signals, which are a plurality of video signals, and add a border to the input signals.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれは、ワイプ時には乗
算回路を用いて2つの画面の行うため、ソフトワイプも
可能であり、また、ボーダーワイプ時には切替回路で2
つの画面の合成をし、乗算回路でボーダ一部分の処理を
行うことにより、乗算回路が2回路で、かつ加算回路も
2人力加算でボーダーワイプができるので、実用上の効
果は極めて大である。
As explained above, according to the present invention, a multiplier circuit is used to perform two screens when wiping, so a soft wipe is also possible, and a switching circuit is used to perform two screens during a border wipe.
By compositing two screens and processing a portion of the border using a multiplier circuit, border wipe can be performed using two multiplier circuits and two adder circuits, so the practical effect is extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による映像混合増幅器の一実施例を示す
ブロック図、第2図、第3図は第1図の動作説明に供す
る各部信号の波形を示す波形図、第4図は従来の映像混
合増幅器の一例を示すブロック図、第5図、第6図は第
4図の動作説明に供する各部信号の波形を示す波形図で
ある。 1・・・・切替回路、2e−−・キー信号処理回路、3
,4・・・・乗算回路、5・・・・加算回路。 ″  へ   ? τ ? )口
FIG. 1 is a block diagram showing an embodiment of the video mixing amplifier according to the present invention, FIGS. 2 and 3 are waveform diagrams showing waveforms of various signals used to explain the operation of FIG. 1, and FIG. A block diagram showing an example of a video mixing amplifier, and FIGS. 5 and 6 are waveform diagrams showing waveforms of various signals for explaining the operation of FIG. 4. 1...Switching circuit, 2e--Key signal processing circuit, 3
, 4...Multiplication circuit, 5... Addition circuit. ″ to ? τ ? ) mouth

Claims (1)

【特許請求の範囲】[Claims] 複数の映像信号を入力としてこれらの切替を行う切替回
路と、ワイプ信号とボーダー信号およびボーダーワイプ
信号を入力として前記切替回路の制御を行うと共にキー
信号の処理を行うキー信号処理回路と、前記切替回路お
よびキー信号処理回路からの信号を受け乗算を行う第1
の乗算回路および第2の乗算回路と、この第1および第
2の乗算回路の各出力を加算し出力映像信号を得る加算
回路とを備えてなることを特徴とする映像混合増幅器。
a switching circuit that inputs a plurality of video signals and switches between them; a key signal processing circuit that receives a wipe signal, a border signal, and a border wipe signal and controls the switching circuit and processes the key signal; and the switching circuit. The first circuit receives signals from the circuit and the key signal processing circuit and performs multiplication.
A video mixing amplifier comprising: a multiplier circuit, a second multiplier circuit, and an adder circuit that adds the respective outputs of the first and second multiplier circuits to obtain an output video signal.
JP4854786A 1986-03-07 1986-03-07 Video mixing amplifier Expired - Fee Related JPH065918B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4854786A JPH065918B2 (en) 1986-03-07 1986-03-07 Video mixing amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4854786A JPH065918B2 (en) 1986-03-07 1986-03-07 Video mixing amplifier

Publications (2)

Publication Number Publication Date
JPS62207074A true JPS62207074A (en) 1987-09-11
JPH065918B2 JPH065918B2 (en) 1994-01-19

Family

ID=12806394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4854786A Expired - Fee Related JPH065918B2 (en) 1986-03-07 1986-03-07 Video mixing amplifier

Country Status (1)

Country Link
JP (1) JPH065918B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0662314A (en) * 1991-03-29 1994-03-04 Grass Valley Group Inc:The Image synthesizing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0662314A (en) * 1991-03-29 1994-03-04 Grass Valley Group Inc:The Image synthesizing device

Also Published As

Publication number Publication date
JPH065918B2 (en) 1994-01-19

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