JPS6220702B2 - - Google Patents

Info

Publication number
JPS6220702B2
JPS6220702B2 JP8636285A JP8636285A JPS6220702B2 JP S6220702 B2 JPS6220702 B2 JP S6220702B2 JP 8636285 A JP8636285 A JP 8636285A JP 8636285 A JP8636285 A JP 8636285A JP S6220702 B2 JPS6220702 B2 JP S6220702B2
Authority
JP
Japan
Prior art keywords
semiconductor element
package
wiring board
lid portion
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8636285A
Other languages
Japanese (ja)
Other versions
JPS60258932A (en
Inventor
Kanji Ootsuka
Masao Sekihashi
Tamotsu Usami
Michiaki Furukawa
Fumyuki Kobayashi
Masakatsu Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8636285A priority Critical patent/JPS60258932A/en
Publication of JPS60258932A publication Critical patent/JPS60258932A/en
Publication of JPS6220702B2 publication Critical patent/JPS6220702B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
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    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は、半導体装置及びその実装回路装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a circuit device mounted thereon.

従来、高密度実装回路基板の新しいアプローチ
として、リードレスパツケージ（チツプキヤリ
ア）がある。このパツケージはリードがないた
め、小形化が可能になり、外部接続端子ピツチも
1.25mm、1.0mmと小さく、従来のデユアルインラ
インパツケージの２〜４倍の実装密度の向上が計
れる。しかしリードがないためパツケージの外部
接続端子と配線基板の接続端子を対向させ直接半
田付等の方法で実装しなければならず、配線基板
とパツケージの熱膨張係数が異ると、それらの膨
張収縮差が直接半田に応力として加わり、半田の
クリープ現象により、破壊するため、前記両者の
熱膨張係数を近似させる必要がある。 Conventionally, leadless packages (chip carriers) are a new approach for high-density packaging circuit boards. Since this package has no leads, it can be made smaller and the external connection terminal pitch can be reduced.
They are small at 1.25mm and 1.0mm, and can improve mounting density by 2 to 4 times compared to conventional dual inline packages. However, since there are no leads, the external connection terminals of the package and the connection terminals of the wiring board must face each other and must be directly mounted using methods such as soldering. Since the difference is directly applied as stress to the solder and it breaks due to the solder creep phenomenon, it is necessary to approximate the coefficients of thermal expansion of the two.

一方大消費電力を有する高密度回路装置は配線
基板がヒートシンクとなり得ず個々の半導体装置
に取付けられた放熱フインにより熱を逃してい
る。この時の半導体装置のパツケージング構造は
チツプ取付け面側を放熱フイン側にし、チツプア
クテイブ面を配線基板側にしたパツケージを使用
し、リードの成形により、配線基板に取付けるよ
うにしている。この点に関し、チツプキヤリアは
チツプのアクテイブ面のキヤツプが突出している
ことから、配線基板にキヤツプ側をダイレクトに
接続できない。従つて、一般的方法であるパツケ
ージのチツプ取付面側を配線基板面にして接続
し、配線基板より放熱させる努力をしている。一
例としてチツプキヤリア、配線基板の相互接続面
上で電気接続端子以外に放熱用に対向したメタラ
イゼーシヨンを行い、前記接続端子と同様に半田
等により同じに接続する方法が取られている。然
しこの方法はチツプキヤリアベースと配線基板を
介しての放熱であり、放熱効果的に制限のある構
造となる。 On the other hand, in high-density circuit devices that consume a large amount of power, the wiring board cannot serve as a heat sink, and heat is dissipated by heat dissipation fins attached to individual semiconductor devices. The packaging structure of the semiconductor device at this time uses a package with the chip mounting surface facing the heat dissipation fin side and the chip active surface facing the wiring board, and is attached to the wiring board by molding the leads. In this regard, since the chip carrier has a protruding cap on the active side of the chip, the cap side cannot be directly connected to the wiring board. Therefore, a common method is to connect the package with the chip mounting surface facing the wiring board in an effort to dissipate heat from the wiring board. For example, a method is used in which opposing metallization is performed on the interconnection surface of the chip carrier or wiring board in addition to the electrical connection terminals for heat radiation, and the same connection is made by soldering or the like in the same manner as the connection terminals. However, in this method, heat is radiated through the chip carrier base and the wiring board, resulting in a structure that has a limited heat radiation effect.

本発明はリードレスチツプキヤリアの前記２つ
の欠点、即ち、放熱制限、熱膨張係数のミスマツ
チによる歪を解消する構造を提案するものであ
る。 The present invention proposes a structure that eliminates the two drawbacks of leadless chip carriers, namely, heat dissipation limitations and distortion due to mismatch in thermal expansion coefficients.

又、本発明の他の目的として放熱性を強化する
構造を提供するものである。 Another object of the present invention is to provide a structure that enhances heat dissipation.

このような目的に適うために本発明は下記する
(1)ないし(2)の基本的構成を有するものとするもの
である。 In order to meet this purpose, the present invention is as follows.
It shall have the basic structure of (1) and (2).

なお、チツプキヤリアベースと配線基板を介し
て放熱する構造のものは、特開昭54−128277号公
報に開示されている。 Note that a structure in which heat is radiated via a chip carrier base and a wiring board is disclosed in Japanese Patent Laid-Open No. 128277/1983.

(1) 複数のセラミツクを積層して成りかつほぼ中
央に貫通孔を有するリードレスパツケージと、
一主面にワイヤボンデイング面を有する半導体
素子と、前記半導体素子のワイヤボンデイング
面とは反対の面に接合される放熱体と、前記放
熱体及び半導体素子を前記パツケージの貫通孔
部において前記パツケージに結合する熱伝導度
の良い材料からなる補助板と、前記半導体素子
のワイヤボンデイング面よりも上方に配置され
る蓋部と、前記蓋部の周囲でこの蓋部よりも高
い位置に設けられる外部接続用導電体端部とを
有することを特徴とする半導体装置。(1) A leadless package made of a plurality of laminated ceramics and having a through hole approximately in the center;
a semiconductor element having a wire bonding surface on one principal surface; a heat sink bonded to a surface opposite to the wire bonding surface of the semiconductor element; and a heat sink and semiconductor element bonded to the package in a through-hole portion of the package. An auxiliary plate made of a material with good thermal conductivity to be bonded, a lid portion disposed above the wire bonding surface of the semiconductor element, and an external connection provided around the lid portion at a higher position than the lid portion. What is claimed is: 1. A semiconductor device comprising: a conductor end portion for use in the semiconductor device;

(2) 複数のセラミツクを積層して成りかつほぼ中
央に貫通孔を有するリードレスパツケージと、
一主面にワイヤボンデイング面を有する半導体
素子と、前記半導体素子のワイヤボンデイング
面とは反対の面に接合される放熱体と、前記放
熱体及び半導体素子を前記パツケージの貫通孔
部において前記パツケージに結合する熱伝導度
の良い材料からなる補助板と、前記半導体素子
のワイヤボンデイング面よりも上方に配置され
る蓋部と、前記蓋部の周囲でこの蓋部よりも高
い位置に設けられる外部接続用導電体端子とを
有する半導体装置の前記外部接続用導電体端子
が配線基板の配線に接続されてなることを特徴
とする回路装置。(2) A leadless package made of a plurality of laminated ceramics and having a through hole approximately in the center;
a semiconductor element having a wire bonding surface on one principal surface; a heat sink bonded to a surface opposite to the wire bonding surface of the semiconductor element; and a heat sink and semiconductor element bonded to the package in a through-hole portion of the package. An auxiliary plate made of a material with good thermal conductivity to be bonded, a lid portion disposed above the wire bonding surface of the semiconductor element, and an external connection provided around the lid portion at a higher position than the lid portion. 1. A circuit device, characterized in that said conductor terminal for external connection of a semiconductor device having a conductor terminal for external connection is connected to wiring of a wiring board.

以下、本発明の好適な実施例を用いて本発明を
具体的に詳述する。 Hereinafter, the present invention will be specifically described in detail using preferred embodiments of the present invention.

第１図ａ〜ｂは本発明者が別途考えた放熱を容
易にするためのチツプキヤリアの一例である。本
図はセラミツクグリーンシート法により作られた
多層メタライズ配線セラミツクチツプキヤリアで
あり、先ず、セラミツク粉末と有機バインダーに
より構成されたグリーンシートを４枚用意し
（１′，１″，１，１″″の母材）、それぞれ耐熱性
メタライズ印刷を５，６，７，８のパターンで行
う。後、１″，１，１″″は５′，６′，７′の穴を
それぞれうがち、それぞれのシートは位置決めさ
れた後重ねられ、加熱加圧され、グリーンシート
中のバインダーの融着により一体化さす。次いで
９′が８のメタライズパターンの外形切断される
であろう中心線上に円形状にあけられ、９のスル
ーホールメタライズが施される。これにより、そ
れぞれの６と８が接続されることになる。この
後、９の中心を通るカツターでもつて外形切断さ
れ、チツプキヤリア構造の生の外形が完成する。
次いで焼成により有機バインダーを飛散させ、セ
ラミツク粒子を焼結させ磁器状にさせる。この時
メタライズ金属粉末も同時に焼結し、セラミツク
と強固に接着すると共に電気伝導を有する配線パ
ターンとなる。次いで素子組立を容易にさせるた
め、露出したメタライズ上にニツケルメツキを下
地とした金メツキが施される（一例）ことによ
り、チツプキヤリアが完成する。 FIGS. 1a to 1b show an example of a chip carrier designed separately by the inventor to facilitate heat radiation. This figure shows a multilayer metallized wiring ceramic chip carrier made by the ceramic green sheet method. First, four green sheets made of ceramic powder and an organic binder were prepared (1', 1", 1, 1"). (base material), heat-resistant metallization printing is performed in patterns of 5, 6, 7, and 8. After that, holes of 5', 6', and 7' are made for 1'', 1, and 1'', respectively. After the sheets are positioned, they are stacked, heated and pressed, and are integrated by fusing the binder in the green sheets. Next, a circular hole 9' is drilled on the center line where the outline of the metallized pattern 8 will be cut, and through-hole metallized 9 is formed. As a result, each of 6 and 8 will be connected. Thereafter, the outer shape is cut using a cutter passing through the center of the chip carrier, and the raw outer shape of the chip carrier structure is completed.
Next, the organic binder is scattered by firing, and the ceramic particles are sintered into a porcelain shape. At this time, the metallized metal powder is also sintered at the same time, forming a wiring pattern that firmly adheres to the ceramic and has electrical conductivity. Next, in order to facilitate device assembly, gold plating with nickel plating as a base is applied to the exposed metallization (for example), thereby completing the chip carrier.

第２図ａ〜ｂは前記第１図のチツプキヤリアに
LSI素子が組立てられ封止された状態を示す図の
一例である。先ずLSI素子（チツプ）１０が金め
つきされたメタライズ上にAu−Si共晶合金で接
続され、金又はアルミニウム線１１でLSI配線上
のパツドとメタライズパターン６がボンデイング
される。次いで、セラミツクと熱膨張係数の近似
した材質の蓋１２が７のメタライズパターン上に
適切な方法により接続され封止される。例えば蓋
１２はコバール材で形成され、金めつきが施さ
れ、メタライズパターン７と近似した角リング状
の金−錫合金の箔を界して重ね加熱し金−錫合金
により融着封止する。この際、蓋１２の上面は電
極８の面より下側にある。以上によりチツプキヤ
リアに組立てられたLSIデバイスが完成すること
において配線基板への実装は外部導出電極８によ
り行われるため、電極８が配線基板上の接続電極
に対向する。この結果、LSI素子チツプ１０は配
線基板の反対面にセラミツクチツプキヤリアベー
ス層１′を界して位置することになり、上面から
放熱を行う場合の有効な構造となる。 Figures 2 a to b are based on the Chippukiyaria shown in Figure 1 above.
1 is an example of a diagram showing a state in which an LSI element is assembled and sealed. First, an LSI element (chip) 10 is connected to a gold-plated metallization using an Au-Si eutectic alloy, and a pad on the LSI wiring and the metallization pattern 6 are bonded with a gold or aluminum wire 11. Next, a lid 12 made of a material having a coefficient of thermal expansion similar to that of ceramic is connected and sealed over the metallized pattern 7 by an appropriate method. For example, the lid 12 is made of Kovar material, is gold plated, and is heated by stacking a gold-tin alloy foil in the shape of a corner ring similar to the metallized pattern 7 and fusion-sealing it with the gold-tin alloy. . At this time, the top surface of the lid 12 is below the surface of the electrode 8. When the LSI device assembled on the chip carrier is completed as described above, the mounting on the wiring board is performed using the external lead-out electrode 8, so that the electrode 8 faces the connection electrode on the wiring board. As a result, the LSI element chip 10 is located on the opposite side of the wiring board with the ceramic chip carrier base layer 1' interposed therebetween, resulting in an effective structure for dissipating heat from the top surface.

第３図は前記第２図を配線基板に実装した構造
の回路装置の一例である。配線基板１５に配置さ
れた電極１４に対向させチツプキヤリア上の電極
８を置き半田等のロウ材１３でもつて接合させ
る。さらに必要ならば放熱体である放熱フイン１
６をセラミツクチツプキヤリアの素子取付された
セラミツクベースの裏面側に半田付等の適切な方
法で取付け、さらに放熱効果を良くさせる。この
際放熱フインがセラミツクと熱膨張係数が異る場
合、フインを小分割することによる絶対歪量を低
減させることが可能である。第４図は配線基板
に、チツプキヤリアに組立てられたLSIデバイス
２３が複数個第３図の状態で接続された状態を示
す。最近の高速高集積デバイスは数ワツトのパワ
ーを有し、複数個接続された場合、その放熱密度
は配線基板面上で１〜5W／cm3となる。このよう
な高放熱密度では配線基板に熱伝導度のよいセラ
ミツクを使用しても配線基板がヒートシンクにな
り得ず、配線基板のデバイス取付け面上で強制空
冷する方法が最も効果的である。この際LSIデバ
イス２３が空冷流路に最も近いところの前記セラ
ミツクチツプキヤリアのベース面に位置しするこ
とは、熱抵抗の最も小さな構造となる。 FIG. 3 is an example of a circuit device having a structure in which the circuit shown in FIG. 2 is mounted on a wiring board. The electrode 8 on the chip carrier is placed opposite to the electrode 14 arranged on the wiring board 15, and the electrode 8 is bonded with a brazing material 13 such as solder. Furthermore, if necessary, a heat dissipation fin 1 as a heat dissipation body
6 is attached to the back side of the ceramic base on which the element of the ceramic chip carrier is attached by an appropriate method such as soldering to further improve the heat dissipation effect. At this time, if the heat dissipation fins have a different coefficient of thermal expansion from ceramic, it is possible to reduce the absolute strain amount by dividing the fins into smaller pieces. FIG. 4 shows a state in which a plurality of LSI devices 23 assembled on chip carriers are connected to a wiring board in the state shown in FIG. 3. Recent high-speed, highly integrated devices have a power of several watts, and when a plurality of devices are connected, their heat dissipation density on the wiring board surface is 1 to 5 W/cm 3 . With such a high heat dissipation density, the wiring board cannot function as a heat sink even if ceramic with good thermal conductivity is used for the wiring board, and the most effective method is to perform forced air cooling on the device mounting surface of the wiring board. In this case, positioning the LSI device 23 on the base surface of the ceramic chip carrier closest to the air cooling flow path results in a structure with the smallest thermal resistance.

第５図ａ〜ｂは本発明の実施例である放熱効果
を更に高めた構造のセラミツクチツプキヤリアの
一例である。（半導体素子（チツプ）１０は熱膨
張係数の近似しかつ熱伝導度の良い材料、例えば
モリブデン又はタングステン等のベース板１７に
金−シリコンのロウ材により取付けられている。
又この前の工程でベース板１７はさらに熱伝導度
の良い材料、例えば銅、アルミニウム等のスタツ
ド１９が反対面にロウ材例えば銅−銀共晶合金等
で取付けられる。このスタツド１９は熱膨張係数
はシリコンに適合せずともよく、熱伝導度のみを
最高に取れる材料であればよい。この立場に立て
ば前記銅、アルミニウム以外にヒートパイプ等も
適切な例である。前記ベース板１７とセラミツク
ベース１の取付けはこの両者の熱膨張の差を緩和
する補助板１８で橋渡をして接続させる。この補
助板１８はベース板１７とセラミツクベース１の
中間の熱膨張係数を持ち、且つ比較的弾性率及び
弾性限界強度の低い材料、例えば鉄−ニツケル−
コバルト合金体、42アロイ（鉄−ニツケル合金）
等が適切であり、１７，１８及び１は相互に適切
なロウ材、例えば銅−銀共晶ロウで接合される。
前記構造のチツプキヤリアに前記した如くチツプ
が取付けられ、次いでボンデイングワイヤ１１で
チツプキヤリア上の配線電極に接続され、蓋１２
で封止される。この構造は、第２図のセラミツク
ベースを界した熱放散に比べ1/2〜1/10の熱抵抗
を有することがわかつた。 FIGS. 5a to 5b show an example of a ceramic chip carrier having a structure that further enhances the heat dissipation effect, which is an embodiment of the present invention. (The semiconductor element (chip) 10 is attached to a base plate 17 made of a material having a similar coefficient of thermal expansion and good thermal conductivity, such as molybdenum or tungsten, using a gold-silicon brazing material.
In the previous step, studs 19 made of a material with good thermal conductivity, such as copper or aluminum, are attached to the opposite surface of the base plate 17 using a brazing material such as a copper-silver eutectic alloy. The stud 19 does not need to have a coefficient of thermal expansion that matches that of silicon, and may be made of any material that can maximize only the thermal conductivity. From this standpoint, in addition to the copper and aluminum mentioned above, heat pipes and the like are also suitable examples. The base plate 17 and the ceramic base 1 are attached to each other by bridging the connection with an auxiliary plate 18 that alleviates the difference in thermal expansion between the two. This auxiliary plate 18 has a coefficient of thermal expansion between that of the base plate 17 and the ceramic base 1, and is made of a material with a relatively low elastic modulus and elastic limit strength, such as iron-nickel.
Cobalt alloy body, 42 alloy (iron-nickel alloy)
etc., and 17, 18 and 1 are bonded to each other with a suitable brazing material, such as copper-silver eutectic brazing.
The chip is attached to the chip carrier of the above structure as described above, and then connected to the wiring electrode on the chip carrier with the bonding wire 11, and the lid 12 is connected to the wiring electrode on the chip carrier.
is sealed. It was found that this structure has a thermal resistance that is 1/2 to 1/10 that of the heat dissipation through the ceramic base shown in FIG.

本チツプキヤリアは第３図と同様にして配線基
板に取り付けられさらに必要ならばスタツド１９
に放熱フインをかしめることにより実用に供せら
れることが容易に類推可能なため詳細説明は省略
する。 This chip carrier is attached to the wiring board in the same manner as shown in Figure 3, and if necessary, it can be attached to the stud 19.
Since it can be easily inferred that it can be put to practical use by caulking the heat dissipation fins, a detailed explanation will be omitted.

第３図の説明ですでに言及されたように配線基
板はセラミツクチツプキヤリアと熱膨張係数が近
似している必要があつた。即ち熱膨張係数が異つ
た場合接合部１３は歪を受け接合材料のクリープ
現象が起り接合が破壊される。このことは配線基
板もセラミツクで作る必要が生じ、従来の一般的
にガラスエポキシプリント基板が使用できない欠
点があつた。然し本発明では以下の詳細で示すよ
うにこの歪を吸収する材料を界することによりセ
ラミツクチツプキヤリアと有機系配線基板の接続
が可能たらしめる方法を提供する。 As already mentioned in the explanation of FIG. 3, the wiring board had to have a coefficient of thermal expansion similar to that of the ceramic chip carrier. That is, if the coefficients of thermal expansion differ, the joint portion 13 will be strained, causing a creep phenomenon of the joining material and destroying the joint. This required the wiring board to be made of ceramic, which had the disadvantage that conventional glass epoxy printed circuit boards could not be used. However, the present invention provides a method for connecting a ceramic chip carrier and an organic wiring board by interposing a material that absorbs this strain, as will be shown in detail below.

第６図は金属板加工体である接続ピース２０の
種々の形状を示したものである材質として、適切
なバネ性がある導体であれば良く銅、ニツケル、
鉄−ニツケル−コバルト合金、42アロイ、ベリリ
ウム銅、真チユウ等が考えられる。 Fig. 6 shows various shapes of the connection piece 20, which is a metal plate processed body.As for the material, any conductor with appropriate spring properties may be used, such as copper, nickel, etc.
Possible materials include iron-nickel-cobalt alloy, 42 alloy, beryllium copper, and brass.

第７図は有機系配線基板１５′の電極１４とセ
ラミツクチツプキヤリアの電極８を対向させ、前
記接続ピース２０を界してロウ材により融接した
構造を示すものであり、２０はセラミツクチツプ
キヤリアと配線基板の熱膨張の差による歪を変形
でもつて吸収することができる。即ち、第７図に
示す実施例は円筒状のスリーブを横にしたもので
この接続ピースが容易に変形することが判明す
る。但し第６図ａとｅは変形の方向性が多少存在
するが同図ｂ，ｃ，ｄはその方向性もなくさらに
望ましい形状であることが判る。 FIG. 7 shows a structure in which the electrode 14 of the organic wiring board 15' and the electrode 8 of the ceramic chip carrier are faced to each other, and fusion-welded with a brazing material with the connection piece 20 separated. Strain due to the difference in thermal expansion between the wiring board and the wiring board can be absorbed through deformation. That is, the embodiment shown in FIG. 7 has a cylindrical sleeve lying on its side, and it has been found that this connecting piece is easily deformed. However, in Figures 6a and 6e, there is some directionality of deformation, but in Figures b, c, and d, there is no such directionality, and it can be seen that the shapes are even more desirable.

この接触時の繁雑さを防止するため、あらかじ
め電極８に高融点ロウ材２１で接続ピース２０を
取付けておき配線基板接続時は抵融点ロウ材、例
えば半田２２で行うことも可能である。 In order to prevent complications during this contact, it is also possible to attach the connection piece 20 to the electrode 8 in advance using a high melting point brazing material 21, and then connect the wiring board using a low melting point brazing material, such as solder 22.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ〜ｂは本発明者が別途考えたリードレ
スパツケージを示す図で、ａは平面図、ｂは断面
図、第２図ａ〜ｂは本発明者が別途考えた半導体
装置を示す図で、ａは平面図、ｂは断面図、第３
図は本発明者が別途考えた回路装置を示す断面
図、第４図は本発明に係る回路装置を示す側面
図、第５図ａ〜ｂは本発明に係る実施例である半
導体装置を示す図で、ａは平面図、ｂは断面図、
第６図ａ〜ｅは本発明に係る金属板加工体を示す
斜視図、第７図は本発明に係る回路装置を示す断
面図である。 １……パツケージの基材、９……スルーホール
メタライズ（外部接続用端子）、１０……半導体
素子チツプ、１２……蓋、１３……ロウ材、１６
……放熱フイン、１７……ベース板、１８……補
助板、１９……スタツド、２０……金属板加工体
である接続ピース、２１……高融点ロウ材、２２
……はんだ、２３……LSIデバイス。 1A to 1B are diagrams showing a leadless package separately conceived by the present inventor, in which a is a plan view, b is a sectional view, and FIGS. 2A to 2B are diagrams showing a semiconductor device separately conceived by the present inventor. In the figure, a is a plan view, b is a cross-sectional view, and the third
The figure is a cross-sectional view showing a circuit device separately conceived by the present inventor, FIG. 4 is a side view showing a circuit device according to the present invention, and FIGS. 5 a to b show a semiconductor device as an embodiment according to the present invention In the figure, a is a plan view, b is a sectional view,
6A to 6E are perspective views showing a metal plate processed body according to the present invention, and FIG. 7 is a sectional view showing a circuit device according to the present invention. DESCRIPTION OF SYMBOLS 1... Base material of package, 9... Through-hole metallization (terminal for external connection), 10... Semiconductor element chip, 12... Lid, 13... Brazing material, 16
... Heat dissipation fin, 17 ... Base plate, 18 ... Auxiliary plate, 19 ... Stud, 20 ... Connection piece which is a processed metal plate, 21 ... High melting point brazing material, 22
...Solder, 23...LSI device.

Claims (1)

【特許請求の範囲】 １ 複数のセラミツクを積層して成りかつほぼ中
央に貫通孔を有するリードレスパツケージと、一
主面にワイヤボンデイング面を有する半導体素子
と、前記半導体素子のワイヤボンデイング面とは
反対の面に接合される放熱体と、前記放熱体及び
半導体素子を前記パツケージの貫通孔部において
前記パツケージに結合する熱伝導度の良い材料か
らなる補助板と、前記半導体素子のワイヤボンデ
イング面よりも上方に配置される蓋部と、前記蓋
部の周囲でこの蓋部よりも高い位置に設けられる
外部接続用導電体端子とを有することを特徴とす
る半導体装置。 ２ 複数のセラミツクを積層して成りかつほぼ中
央に貫通孔を有するリードレスパツケージと、一
主面にワイヤボンデイング面を有する半導体素子
と、前記半導体素子のワイヤボンデイング面とは
反対の面に接合される放熱体と、前記放熱体及び
半導体素子を前記パツケージの貫通孔部において
前記パツケージに結合する熱伝導度の良い材料か
らなる補助板と、前記半導体素子のワイヤボンデ
イング面よりも上方に配置される蓋部と、前記蓋
部の周囲でこの蓋部よりも高い位置に設けられる
外部接続用導電体端子とを有する半導体装置の前
記外部接続用導電体端子が配線基板の配線に接続
されてなることを特徴とする回路装置。 ３ 配線基板と半導体装置の「外部接続用導電体
端子」との固着には、配線基板と半導体装置との
熱膨脹の差を吸収する金属板加工体を介してロウ
材を用いて接合されてなるものが使用されている
ことを特徴とする特許請求の範囲第２項記載の回
路装置。[Scope of Claims] 1. A leadless package made of a plurality of laminated ceramics and having a through hole approximately in the center, a semiconductor element having a wire bonding surface on one main surface, and a wire bonding surface of the semiconductor element. a heat sink bonded to the opposite surface; an auxiliary plate made of a material with good thermal conductivity that connects the heat sink and the semiconductor element to the package at the through hole portion of the package; and a wire bonding surface of the semiconductor element. 1. A semiconductor device comprising: a lid portion disposed above the lid portion; and an external connection conductor terminal provided around the lid portion at a higher position than the lid portion. 2. A leadless package formed by laminating a plurality of ceramics and having a through hole approximately in the center, a semiconductor element having a wire bonding surface on one main surface, and a leadless package bonded to the surface opposite to the wire bonding surface of the semiconductor element. an auxiliary plate made of a material with good thermal conductivity that connects the heat radiator and the semiconductor element to the package at a through-hole portion of the package; and an auxiliary plate disposed above the wire bonding surface of the semiconductor element. A semiconductor device having a lid portion and an external connection conductor terminal provided around the lid portion at a higher position than the lid portion, wherein the external connection conductor terminal is connected to wiring of a wiring board. A circuit device characterized by: 3. The wiring board and the "external connection conductor terminal" of the semiconductor device are bonded together using a brazing material via a metal plate processing body that absorbs the difference in thermal expansion between the wiring board and the semiconductor device. 3. The circuit device according to claim 2, wherein a circuit device is used.
JP8636285A 1985-04-24 1985-04-24 Semiconductor device and circuit device thereof Granted JPS60258932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8636285A JPS60258932A (en) 1985-04-24 1985-04-24 Semiconductor device and circuit device thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8636285A JPS60258932A (en) 1985-04-24 1985-04-24 Semiconductor device and circuit device thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP13163478A Division JPS5559746A (en) 1978-10-27 1978-10-27 Semiconductor device and its mounting circuit device

Publications (2)

Publication Number Publication Date
JPS60258932A JPS60258932A (en) 1985-12-20
JPS6220702B2 true JPS6220702B2 (en) 1987-05-08

Family

ID=13884770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8636285A Granted JPS60258932A (en) 1985-04-24 1985-04-24 Semiconductor device and circuit device thereof

Country Status (1)

Country Link
JP (1) JPS60258932A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223741A (en) * 1989-09-01 1993-06-29 Tactical Fabs, Inc. Package for an integrated circuit structure
JPH0536751A (en) * 1991-07-26 1993-02-12 Nec Corp Semiconductor assembling structure

Also Published As

Publication number Publication date
JPS60258932A (en) 1985-12-20

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