JPS62206904A - Full wave rectifier circuit - Google Patents

Abstract

PURPOSE:To obtain a full wave rectifier waveform without distortion by selecting the 1st output signal being the result of sampling an input signal when the input signal is positive and selecting the 2nd output signal being the result of sampling the input signal when the input signal is negative. CONSTITUTION:An output selection section 2 uses a control signal phic to select either an output signal v1 or v2 and output the result as an output signal vout. That is, with the control signal phic at L level, the output signal v2 is selected. As a result, the output signal vout subjected to full wave rectification as shown in figure (e) is obtained. Since the output signal v1 or v2 is selected by the control signal phic based on the polarity of the input signal vin in this way, the output signals vout are not unarranged near zero voltage. Since the output signal v1 or v2 is obtained by sampling by means of the clock signal phi, the distortion of the output signals v1, v2 due to the nonlinearity of the components is not caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a double-wave rectifier circuit that double-wave rectifies an input signal.

[Prior Art] Conventionally, there has been a technique in this field as shown in FIG. The configuration will be explained below.

FIG. 2 is a block diagram showing an example of the configuration of a conventional double-wave shaping circuit. This double-wave shaping circuit includes an operational amplifier A1 that inverts and amplifies only the positive half cycle of the input signal Win, and an operational amplifier A2 that adds and inverts and amplifies the input signal Vln and the output signal of the operational amplifier AI. Operational amplifier A1
The positive input terminal of is grounded, and the negative input terminal is connected to the input terminal IN via an input resistor R1. A diode D1 is inserted between the output terminal and the negative input terminal of the operational amplifier A1. A feedback resistor R3 and a diode D2 connected in series are inserted in parallel with the diode D1 between the output terminal and the negative input terminal. The positive input terminal of the operational amplifier A2 is grounded, and the negative input terminal is connected to the input terminal IN via the input resistor R2, and also to the connection point between the feedback resistor R3 and the diode D2 via the input resistor R4. There is. Operational amplifier A2
A feedback resistor R5 is inserted between the output terminal and the negative input terminal. The output terminal of the operational amplifier A2 is connected to the input terminal OUT.

The operation of this double-wave shaping circuit in the case where the resistors R1=R2=R3=R4=R and the resistor R4=R/2 will be explained. Figure 3 (a
) When the input signal Tin shown in ) is positive, the diode Di
is non-conductive, diode D2 is conductive, and operational amplifier AI inverts and amplifies the input signal Vin. The output of this operational amplifier AI is connected to the input signal W via the input resistor R4.
in is input to the operational amplifier A2 via the input resistor R2, and is inverted and amplified. Now, since the input resistance R2=R and the input resistance R4=R/2, the output of the operational amplifier A1 has a 2 times larger amplification factor than the input signal Tin.

That is, the output -Tin of operational amplifier A1 is
The input signal Win is multiplied by 11 by the operational amplifier A2, and as a result, the positive half cycle of the input signal vin is output from the operational amplifier A2 as shown in FIG. 3(C).

When the input signal Win is negative, the diode D1 becomes conductive, the diode D2 becomes non-conductive, and the output of the operational amplifier AI becomes zero. Therefore, the operational amplifier A2 inverts and amplifies only the human input signal Yin, and as a result, the negative half cycle of the input signal Min is inverted and the positive half cycle is output as shown in FIG. 3(C).

Therefore, this double-wave shaping circuit can double-wave rectify the input signal vIn as shown in FIG. 3(a) to obtain an output signal as shown in FIG. 3(c).

[Problems to be solved by the invention] However, in the conventional double wave shaping circuit, the resistors Rl and R2
, R3, R4, and R5 do not satisfy the above-mentioned relationship, that is, R1=R2=R3=2R4=R5, as shown in Figure 3(b), both waves are shaped near O port. There was a problem in that the waveform was distorted and the resistance value had to be adjusted.

Furthermore, if the linearity of the diodes DI and D2 is not good, there is a problem that the output signal vout is distorted.

The present invention provides a dual-wave shaping circuit which solves the problem of the above-mentioned prior art in that the waveform of the output signal is not uniform near zero volts and is distorted.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a dual-wave shaping circuit that performs dual-wave shaping on an input signal. A sample and hold section for outputting a second output signal is provided, and one of the first and second output signals is selected by an output selection control signal based on the sign of the input signal.

[Function] According to the present invention, since the double wave shaping circuit is configured as described above, when the input signal is positive, the first output signal obtained by sampling the input signal is selected, and when the input signal is negative, the first output signal is selected. A second output signal obtained by sampling an inverted signal of the input signal is selected and output, and the input signal is double-wave rectified. Therefore, the above-mentioned problem can be eliminated.

[Example] A double-wave rectifier circuit according to an embodiment of the present invention is shown in FIG.

The sample and hold section 1 samples the input signal Win using the clock signal φ and outputs the output signal Ml.

Further, the sample hold section 1 inverts the input signal Tin,
The inverted signal is sampled by the clock signal φ,
Outputs an output signal v2. The output selection unit 2 selects one of the output signals vl + V 2 from the sample and hold unit 1 using the control signal φC, and outputs the output signal V out
It is output from the output terminal OUT as Control signal generator 3
outputs this control signal φC based on the input signal Win.

Next, the operation will be explained using the time chart shown in FIG.

When an input signal Win as shown in FIG. 4(a) is input, the sample-hold section 1 performs sampling using the clock signal φ and outputs an output signal v1 as shown in FIG. 4(b). The output signal v1 is actually discontinuous because it is sampled by the clock signal φ, but since the clock signal φ generally has a higher frequency than the period of the output signal v1, it is continuous in FIG. 4(b). It is illustrated as if. Signals '/2. shown in FIGS. 4(c) and (e). Vo
The same applies to uL. Also, sample hold section 1
inverts the input signal Win, samples this inverted signal using the clock signal φ, and outputs an output signal v2 as shown in FIG. 4(C).

On the other hand, the control signal generating section 3 outputs a control signal φC depending on the positive or negative sign of the input signal Win. That is, as shown in FIG. 4(d), when the input signal Win is positive, it is at H level;
If it is negative, the control signal φC which becomes L level is outputted to the output selection section 2.

The output selection section 2 selects output signals V+,
/2 is selected and outputted as the output signal VouL. That is, when the control signal φC is at the H level, the output signal v1 is selected, and when the control signal φC is at the L level, the output signal v2 is selected. As a result, a double-wave rectified output signal V out as shown in FIG. 4(e) can be obtained.

As described above, according to this embodiment, the control signal φ is based on the positive or negative sign of the input signal Van. The output signal Ml.

Since the output signal V2 is selected, the output signal Vout does not become irregular near zero volts, and the output signal Vl+V2 is obtained by resampling it using the clock signal φ. The output signal '/l+v2 is not distorted due to non-linearity of the constituent elements as in the conventional case.

A double wave shaping circuit according to another embodiment of the invention is shown in FIG. This double-wave shaping circuit also includes a sample hold section 1, an output selection section 2, and a control signal generation section 3.

The sample hold unit 1 receives a clock signal φ1. The input signal Win is sampled by φ2, and an output signal Vl having the same phase as the input signal Tin and an output signal v2 having the opposite phase are output. Analog switches Sla and Slb connected in series are connected to an input terminal IN. analog switch S
la is opened and closed by the clock signal φ1, and the analog switch Slb is opened and closed by the clock signal φ2, which has a phase 180° different from that of the clock signal φ1. A grounded capacitor C1 is connected to the connection point between the analog switches Sea and Slb. A positive phase operational amplifier Ala and a negative phase operational amplifier Alb are connected to the analog switch Slb.

An output signal Vl is output from the positive phase operational amplifier Ala,
An output signal v2 is output from the anti-phase operational amplifier Alb.

The output selection unit 2 receives a control signal φ8. from a control signal generation unit 3 which will be described later. One of the output signals Vl and V2 is selected by φb. Analog switch S2a connected in series
and S2b are connected to the output end of the positive-phase operational amplifier AIa of the sample hold section 1. analog switch 3
2a is opened and closed by a clock signal φl, and analog switch S2b is opened and closed by a control signal φa. A grounded capacitor C2a is connected to the connection point between the analog switch S2a and the analog switch S2b. Analog switches S2c and 32d connected in series form the opposite-phase operational amplification 1! of the sample hold section 1! It is connected to the output end of Alb. Analog switch S2c is opened and closed by clock signal φl, and analog switch S2d is opened and closed by control signal φb. Analog switch S2c and S
A grounded capacitor C2b is connected to the connection point with 2d. The analog switches S2b and S2d are commonly connected and connected to the input terminal of the positive phase operational amplifier A2, and the output terminal of the positive phase operational amplifier A2 is connected to the output terminal OUT.

The control signal generator 3 generates control signals φa and φb to the output selector 2 based on the input signal Win. The analog switch S3a is the positive phase operational amplifier A of the sample hold section l.
It is connected to the output terminal of la. Analog switch S3
b has one end grounded and the other end connected to the analog switch S3a. Analog switch 33a is opened and closed by clock signal φ1, and analog switch S3b is opened and closed by clock signal φ2. An analog switch S3a is connected to the negative input terminal of the voltage comparator A3 via a capacitor C3.
A common connection point between and S3b is connected. Voltage comparator A
The positive input terminal of No. 3 is grounded. Further, an analog switch S3c is inserted between the output end and the positive input end, and is opened and closed by the clock signal φ2. The output terminal of the voltage comparator A3 is connected to the data input terminal of the latch circuit 3e, which is a 0 flip-flop, and also to the data input terminal of the latch circuit 3f, which is a 0 flip-flop.
is connected to the data input end of the inverter 3d. A clock signal φS is input to the clock input terminals S of the latch circuits 3e and 3f. The signal from the output terminal Q of the latch circuit 3e is outputted as a control signal φa via an AND gate 3g, and the signal from the output terminal Q of the latch circuit 3f is outputted as a control signal φb via an AND gate 3h. AND gates 3g and 3h are clock signals φ2
Gate M is controlled by.

Next, the operation will be explained using the time chart shown in FIG.

The clock signal φ1 and the clock signal φ2 have a 180° phase difference, and the clock signal φS has a narrower pulse width than the clock signal φ1, and its falling edge is synchronized with the falling edge of the clock signal φ1.

The input signal 'Win inputted to the input terminal IN is inputted to the analog switch Sla. This analog switch Sla
becomes conductive when the clock signal φ1 is at H level, and the capacitor C1 is charged. Clock signal φ2 is H
When the level is reached, the analog switch stb becomes conductive, and the charge charged in the capacitor C1 is injected into the positive-phase operational amplifier Ala and the negative-phase operational amplifier Alb, which output signals v1 of the in-phase and negative-phase components of the input signal Win, respectively. ．． v2
is obtained.

Next, the operation of the control signal generating section 3 that generates the control signals φ and φb will be explained. When clock signal φ2 is at H level, analog switches S3b and S3c become conductive. Then, the negative input terminal of the voltage comparator A2 becomes a virtual ground state, and the accumulated charge of the capacitor C3 becomes zero. When the clock signal φ1 becomes H level, the analog switch S3a becomes conductive, and the analog switches S3b and S3 become conductive.
c enters the cut-off state. Then, the output signal v1 of the positive-phase operational amplifier Ala charges the capacitor C3 via the analog switch S3a, and this capacitor 3 has Q =
A charge of Cv l is charged. Here, C is the capacitance of the capacitor C3. Since the gain of the voltage comparator A3 is considered to be infinite when the analog switch S3c is in the cutoff state, if the output voltage v1 is positive, the comparison WiA
The output of comparator A3 becomes L level, and if the output voltage v1 is negative, the output of comparator A3 becomes H level.

When the output of comparator A3 is at H level, latch circuit 3e
An H level is input to the data input end of the latch circuit 3f, and an L level is input to the data input end of the latch circuit 3f.

These data signals are latched in synchronization with clock signal φ, and an H level signal and an L level signal are output from data output terminals Q of latch circuits 3e and 3f, respectively. These output signals are controlled by control signals φ1 . φb is generated. Now, since the output of comparator A3 is at H level,
The control signal S becomes H level. Conversely, when the output of comparator A3 is at L level, control signal φa becomes H level.

That is, when the output signal v1 is positive, the clock signal φ2
The control signal φa becomes H level in synchronization with the output signal v
If I is negative, the clock signal φ? control signal φ in synchronization with
b becomes H level.

The output selection circuit 2 receives these control signals φ. Either output signal vI or v2 is selected by φb. clock signal φ
When l becomes H level, analog switches S2a and S2
c becomes conductive, and capacitors C2a and C2b are charged by the output signal VllV2. Next, clock φ2
When the control signal φa becomes H level in synchronization with , the analog switch S2b becomes conductive, and the electric charge charged in the capacitor C2a is input to the positive phase operational amplifier A2. Further, when the control signal φa becomes H level in synchronization with the clock φ2, the analog switch S2a becomes conductive, and the charge charged in the capacitor C2b is transferred to the positive-phase operational amplifier A2.
is input. Positive phase operational amplifier A2 is capacitor C2a
Or amplify the signal from C2b and output new signal V ou
It is output from the output terminal OUT as t.

Therefore, when the output signal Vl is positive, the control signal φa becomes H level, and the analog switch S2b becomes conductive.
An output signal v1 is output from the output terminal OUT. Conversely, when the output signal v1 is negative, the control signal φb becomes H level, the analog switch S2b becomes conductive, and the output signal v2 is output from the output terminal OUT. the result,
The output signal v out has a double-wave rectified waveform.

In this way, according to this embodiment, the output signal is obtained by sampling without using a resistor.
The waveform near zero volts will not become irregular or distorted. Further, the circuit of this embodiment can be easily integrated into a circuit, and the circuit can be miniaturized. Therefore, this waveform shaping circuit can be used as a timing extraction circuit, a detection circuit, etc.

The present invention is not limited to the embodiments described above, and various modifications can be made.

For example, the input signal Win may be directly input to the analog switch S3a of the control signal generator 3.

[Effects of the Invention] As explained in detail above, according to the present invention, the input signal and its inverted signal are sampled, and the sampled signal is selected by a control signal based on the positive/negative of the input signal, so that zero volt It is possible to obtain a double-wave rectified waveform without irregularities in the vicinity and without distortion.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a double wave rectifier circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional double wave rectifier circuit,
3 is a time chart showing the operation of FIG. 2, FIG. 4 is a time chart showing the operation of FIG. 1, FIG. 5 is a circuit diagram showing a double wave rectifier circuit according to another embodiment of the present invention, and FIG. FIG. 6 is a time chart showing the operation of FIG. l...sample hold section, 2...output selection section, 3...control signal generation section, Sla, Slb,
S2a. S2b, S2c, S2d, S3a, S3b, S3c・-
・A, analog switch, CI, C2a, C
2b, C3-capacitor, Ala, Alb, A
2, A3--Operation amplifier, 3d... Inverter, 3e, 3F... Latch circuit, 3g, 3h...
And gate. Applicant Agent Kyo Kaki Ki Acid Fig. 1 DI, D2: Diode Fig. 2 Time chart of Fig. 2 Fig. 3 (d) Kabuto F]-Lf] Fig. 4 Fig. 6

Claims (1)

[Scope of Claims] A sample hold unit that outputs first and second output signals obtained by sampling an input signal and an inverted signal of the input signal using a clock signal, and a control signal for output selection based on the positive or negative of the input signal. a control signal generating section that generates a control signal, and a selecting section that selects and outputs either the first or second output signal according to the control signal from the control signal generating section; A double-wave rectifier circuit characterized by wave rectification.