JPS6258879A - Rectifying circuit - Google Patents

Abstract

PURPOSE:To obtain the rectifying characteristics without dispersion by doing sampling of the input signal voltage and by outputting each sampled voltage thus obtained always of a specified polarity. CONSTITUTION:From the sample hold circuit 2A an output voltage b is obtained with a waveform as shown in the figure. It is supplied to a switch 27 with which the ON-OFF control is exercised by means of the switch signal d. The switch 27 is kept turning ON while the rectified signal voltage a is in negative polarity, when it draws out the positive polarity portion of the output signal b in the sample hold circuit 2A and on the other, the switch 28 is kept turning ON while the rectified signal voltage is in positive polarity drawing out the earth voltage. Consequently, the voltage of positive polarity inverted by the negative polarity portion of the rectified signal voltage a and the earth voltage are alternately selected, so that the output voltage f' is obtained in which the rectified signal voltage a is subjected to half-wave reftification of positive polarity at the output terminal 5. No dispersion is brought forth to the rectifying characteristics, since no diode is used in the above-mentioned rectifying circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a rectifier circuit suitable for integration into an IC or LSI.

[Background of the invention]

Conventional rectifier circuits include, for example, "Basic Room, Sub-Circuit J p-209" by Takanori Okoshi, published on February 25, 1980.
212, the diode is inserted. Although it is easy to implement such a rectifier circuit into a bipolar IC, it is possible to convert this into a bipolar type IC.
Oxide S semiconductor ) Yani C
However, due to large variations in the characteristics of diodes, it was not possible to incorporate diodes into ICs, and an external element had to be used.

For this reason, the conventional rectifier circuit implemented as an MO8 type IC becomes large in size and is also limited in terms of productivity.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art and to provide a rectifier circuit that can be implemented as an MO8 type IC by eliminating external components.

[Summary of the invention]

To achieve this objective, the present invention obtains a rectified output voltage of the input signal voltage by sampling the input signal voltage and always outputting each sample voltage obtained thereby with a constant polarity. The points are distinctive.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

Section 1 is a circuit diagram showing an embodiment of the rectifier circuit according to the present invention, in which 1 is an input terminal, 2A and 2B are sample and hold circuits, 21 to 28 are switches, 31 and 32 are capacitors, and 4 is a comparator. , 5 are output terminals.

In the figure, an input terminal 1 to which an input signal voltage to be rectified (signal voltage to be rectified) a is input is connected to sample and hold circuits 2A, 2B and a comparator 4.

The two sample and hold circuits have switches 21 and 22 connected in series between the input terminal 1 and the ground terminal, and a switch 23 connected in series between the ground terminal and the output terminal of the two sample and hold circuits.゜24 and switch 21,2
20 connection point and a capacitor 31 connected between the connection point of switches 23 and 24. Further, the sample and hold circuit 2B includes a switch 2 connected in series between the input terminal 1 and the output terminal of this sample and hold circuit 2B.
5.26 and a capacitor 32 connected by kv5 between the connection point of the switch 25.26 and the ground terminal. The output terminals of the two sample and hold circuits are connected through a switch 27,
Further, the output terminals of the sample and hold circuits 2B are commonly connected to the respective output terminals 5 via switches 28.

The switches 21, 23, and 25 are controlled on and off by a common clock φ1, and the switches 22, 24, and 26 are controlled by a clock φ having an opposite phase to this clock φ.

Controlled on and off at the same time.

Comparator 4 compares the rectified signal voltage a with a reference voltage,
Switch signals e and d having mutually opposite phases are generated. Here, to simplify the explanation, this reference voltage, zero (V)
(ground potential), and the comparator 4 determines the polarity of the rectified signal voltage a. The switch 27 receives the switch signal d
The switch 28 is controlled on and off by the switch signal eVC. As a result, the switches 27 and 28 are turned on alternately, and the output voltages S and C of the sample and hold circuits 2A and 2B are alternately selected and supplied to the output terminal 5.

Next, the operation of this embodiment will be explained using FIG. 22, which shows the waveforms of signals at each part in FIG. Note that each signal in FIG. 2 is given the same reference numeral as the corresponding signal in FIG. 1.

First, in the sample and hold circuit 2A, when the switch 21.23 is turned on by the clock φ, the switch 22.24 is turned off, so that a current corresponding to the instantaneous value of the rectified signal voltage a at that time flows through the switch 21.23. ．． Capacitor 31. Flows through switch 23 and capacitor 31
Charging or discharging takes place. As a result, a voltage corresponding to the instantaneous value of the rectified signal voltage a when the switch 21.23 is closed is held in the capacitor 31.

That is, the rectified signal voltage a is sampled and held in the capacitor 31.

Next, when the switches 22 and 24 are turned on by the clocks φ and VC, the switches 21 and 23 are turned off, so that the sample voltage held in the capacitor 31 is output from the two sample and hold circuits. The switches 21 to 24 and the capacitor 31 operate as described above, and constitute a Nutschit capacitor circuit. At this time, the terminal that takes out the sample voltage from the capacitor 31 is on the opposite side of the terminal that takes this sample voltage into the capacitor 31, so the sample voltage output by the two sample and hold circuits is the same as the one that takes the sample voltage into the capacitor 31. The polarity is opposite to that of the sample voltage. That is, although the output signals from the two sample and hold circuits are sampled and held every cycle of the clock φ, they are obtained by inverting the polarity of the rectified signal voltage a.

On the other hand, in the sample hold circuit 2B,
When the switch 25 is closed by the clock φ1, the switch 26 is opened and the sample voltage of the rectified signal voltage a is held in the capacitor 32. Next, the switch 26 is closed by the clock φ, the switch 25 is opened, and the sample voltage held in the capacitor 32 is output from the sample and hold circuit 2B. The switches 25, 26 and capacitor 32 operate as described above, and these also constitute a switched capacitor.

At this time, since the input terminal and output terminal of the sample voltage of the capacitor 32 are the same, the sample voltage output from the sample hold circuit 2B and this sample voltage taken into the capacitor 32 have the same polarity. . Therefore, the output voltage C of the sample hold circuit 2B has the same polarity as the rectified signal voltage a.

The switch 27 is controlled by the switch signal d from the comparator 4 so that it is turned on during the period when the rectified signal voltage a has negative polarity and is turned off during the period when the rectified signal voltage a is positive polarity. On the contrary, the switch 28 is controlled by the switch signal e from the comparator 4 so that it is turned on during the period when the rectified signal voltage a has positive polarity and is turned off during the period when the rectified signal voltage a has negative polarity. For this purpose, the switch 27 alternately extracts the positive polarity periods of the output voltages of the two sample and hold circuits, and the switch 28 alternately extracts the positive polarity periods of the output signal C of the sample and hold circuit 2B. 5, an output voltage f is obtained by full-wave rectification of the rectified signal voltage a to positive polarity.

In this way, the signal voltage a to be rectified can be full-wave rectified, but since no diode is used, there will be no variation in the rectification characteristics even if the entire device is made into an MO8 type IC.

Note that by controlling the switch 27 with the switch signal e and the switch 28 with the switch signal d, the rectified signal voltage a can also be full-wave rectified to negative polarity.

FIG. 3 is a circuit diagram showing another embodiment of the rectifier circuit according to the present invention, and parts corresponding to those in FIG. 1 are given the same reference numerals and redundant explanation will be omitted.

In the embodiment shown in FIG. 1, a sample and hold circuit 2B is provided on the input side of the switch 28 to perform full-wave rectification, but in this embodiment shown in FIG.
The input side of 8 is grounded, thereby performing half-wave rectification.

That is, in FIG. 3, an output voltage having the waveform shown in FIG. 2 is obtained from the two sample-and-hold circuits, and this is applied to the switch 2 which is controlled on and off by the switch signal d.
The ground voltage is supplied to the switch 28, which is controlled to be turned on and off by the switch signal e. This ground voltage is the reference voltage K of the comparator circuit 4.

The switch 27 is on while the rectified signal voltage a has negative polarity and extracts the positive polarity portion of the output signals from the two sample and hold circuits, and the switch 28 is on while the rectified signal voltage a is positive. , extract the ground voltage. Therefore, the positive polarity voltage obtained by inverting the negative polarity portion of the rectified signal voltage a and the ground voltage are alternately selected, and the output voltage f obtained by half-wave rectifying the rectified signal voltage a to positive polarity is output to the output terminal 5. ′ is obtained.

FIG. 4 is a circuit diagram showing still another embodiment of the rectifier circuit according to the present invention, 6 is an AND gate, and parts corresponding to those in FIG. .

In this embodiment, the input side of the switch 27 is grounded, and
The switch 26 of the sample and hold circuit 2B is turned on and off by the output clock φ of the AND gate 6 which receives the clock φ and the switch signal e of the comparator 4,
This embodiment differs from the embodiment shown in Fig. pJ1 in that the switch 28 in Fig. 1 is omitted, and the rectified signal voltage a is half-wave rectified by kneading.

In FIG. 4, the switch 27 is controlled on and off by the switch signal d from the comparator 4, and outputs a ground voltage equal to the reference voltage of the comparator 4 during the negative polarity period of the rectified signal voltage a.

On the other hand, the AND gate 6 uses the switch signal C from the comparator 4 to output the positive period clock φ of the rectified signal voltage a,
This is the clock φ.

As a result, the switch 26 of the sample hold circuit 2B is controlled to be turned on and off. From this K, sample hold circuit 2
From B, voltage C' of the positive polarity period of the rectified signal voltage a is outputted with positive polarity.

Therefore, at the output terminal 5, a voltage f'' is obtained by half-wave rectifying the rectified signal voltage a to positive polarity.

Since the embodiments shown in FIGS. 3 and 4 also do not use diodes, uniform rectification characteristics can be obtained even if the entire structure is made into an MO3 type IC'. In these embodiments as well, the switch 27 is controlled on and off by the switch signal e, the switch 28 is controlled by the switch signal d, and the switch 26 (FIG. 4) is controlled by the AND processing output of the switch signal d and the clock φ2. By performing on/off control with K, it is also possible to half-wave rectify the rectified signal voltage a to negative polarity.

Furthermore, in FIGS. 1 and 3, the switch 22°24.26 in the sample and hold circuits 2A and 2B
The clock for controlling the on/off of the switch 26 shown in FIG. side switch 27.
28 can be omitted.

The reference voltage set in the comparator 4 can be set to any value other than zero (Vl) as necessary. However, the voltage on the input side of the switch 28 in FIG. The voltages of k are each made to match this reference voltage.At this time, k is the rectified signal voltage a, which is full-wave or half-wave rectified to be less than or equal to this reference voltage.

〔Effect of the invention〕

As explained above, according to the present invention, all elements are
Even if it is incorporated into a MO8-type IC by incorporating it into a MO8 type IC, consistent rectification characteristics can be obtained, which promotes miniaturization of the rectifier circuit, makes the characteristics of the rectifier circuit uniform, and improves productivity. It can have excellent effects.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the rectifier circuit according to the present invention, FIG. 2 is a waveform diagram showing signals at each part of FIG. 1, and FIGS. It is a circuit diagram showing an example of. l...Input terminal, 2A, 2B...Sample hold circuit, 4...Comparator, 5...
...Output terminal, 6...And gate. Figure 1 Figure 2 Figure 3

Claims (3)

[Claims] (1) A first means for detecting a first period in which the rectified signal voltage is equal to or higher than a set reference voltage and a second period in which the rectified signal voltage is less than the reference voltage; a second means for outputting two signal voltages corresponding to the rectified signal voltage; and a second means for alternately selecting two signal voltages output from the second means for each of the first and second periods. 3. A rectifier circuit comprising the third means, and configured such that a signal voltage obtained by rectifying the rectified signal voltage can be obtained from the third means. (2) In claim (1), the second means samples and holds the rectified signal voltage using a switched capacitor and outputs a signal voltage having a phase opposite to the rectified signal voltage. and a second sample and hold circuit that samples and holds the rectified signal voltage using a switched capacitor and outputs a signal voltage that is in phase with the rectified signal voltage. A rectifier circuit characterized by full-wave rectification of a rectified signal voltage. (3) In claim (1), the second means samples and holds the rectified signal voltage using a switched capacitor to generate a signal voltage that is in phase with or in phase with the rectified signal voltage. and a means for outputting a constant signal voltage equal to the reference voltage set by the first means, the rectifier circuit comprising: a sample and hold circuit that outputs a signal voltage; and a means for outputting a constant signal voltage equal to a reference voltage set by the first means, the rectifier circuit performing half-wave rectification of the voltage to be rectified.