JPS62206882A - Nonvolatile semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To minimize additional capacitance except the capacitance of a thin gate oxide film section, and to increase working speed and reduce fluctuation while enabling stable writing and erasion by leaving a positioning-displacement margin in the periphery of the thin gate oxide film between a drain and a floating gate. CONSTITUTION:A drain region 8 extending under a field oxide film for insulating isolation is faced oppositely to a floating gate 12 through a thin second gate oxide film (a tunnel oxide film) in a section 11. The floating gate 12 is extended so as to coat the second gate oxide film 11 formed onto the drain region 8, which is shaped as an opening section formed by removing the field oxide film through etching and extends under the field oxide film, onto a first gate oxide film 10 on a semiconductor substrate 7 between a source and a drain. A control gate 14 is shaped through a third gate oxide film 13. Accordingly, a positioning-displacement margin is left around the second thin gate oxide film section, thus removing a section where the drain and the floating gate are faced oppositely through the first gate oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Application Field 1 The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same, and more particularly to a non-volatile semiconductor memory device and a method for manufacturing the same, and in particular, it consists of a MIS field effect I transistor having a floating gate.
Tunneling (Fowler NordbPii Tu
E2PROM (Rlect
,rical IErasable Programa
ble ROM) and its manufacturing method.

1 Prior Art] Figure 11 (a>, (b) shows the conventional Foster Nord
dhc i+* A schematic plan view of an n-channel E2PROM memory I-transistor using the electron injection/output method by Tunne Iing and its A-A' cross-sectional view 97
are the P-type semiconductor substrate, 16.15 are the source and drain, respectively, 10.13 are the first gate I-oxide film, and the third gate I-oxide film, respectively.
A gate oxide film, 4 is a control gate electrode, 12 is a floating gate, and electrons are injected and extracted through the second gate oxide film 11. Each electrode is capacitively coupled as shown in FIG. C3 is the capacitance between the floating gate and the control gate, C2 is the capacitance of the thin second gate I to the oxide film between the floating gate and the drain, C3 is the capacitance between the floating gate and the semiconductor substrate, and CFS and CPD are the floating gates 1 to -, respectively. This is the overlap capacitance between sources and between floating gate and drain.

The write operation is performed by grounding the control gate, source, and semiconductor substrate and applying a high positive voltage (approximately 20 V for PA) to the drain, thereby concentrating the electric field from the capacitive coupling described above to the thin second gate oxide film, and performing FOW. Nordheim T
This is done by extracting electrons from the floating gate to the drain due to unneling.

Extraction of electrons results in the accumulation of positive charges in the floating gate, and the threshold value of the memory transistor becomes low F, resulting in so-called depletion operation. The erase operation is performed by grounding the drain, source, and semiconductor substrate, and applying a high positive voltage (for example, about 20 V) to the control gate to remove the thin second electrode from capacitive coupling.
Concentrate the electric field on the gate oxide film. In this case, the direction of the electric field is opposite to that of the write operation, and electrons are injected from the drain to the floating gate. As a result, negative charges are accumulated in the floating gate, and the threshold value of the memory transistor becomes high. Reading of the written information is performed by appropriately selecting the control voltage at the time of reading and determining whether the -1 memory transistor is ON (ON> or OFF).

The manufacturing method will be described below with reference to the cross-sectional views of FIGS. 13(a) to 13(e). FIGS. 13(a) to 13(e) are cross-sectional views shown in order of steps to explain a conventional manufacturing method.

First, a field oxide 1 for insulation isolation 9 is selectively formed on the p-type semiconductor substrate 7. As shown in FIG.

Next, as shown in FIG. 13('b), the source 16° and drain 15 are selectively formed by, for example, As ion implantation. Next, as shown in FIG. 13(c), about 80
0 first game) - An oxide film 10 is formed by a thermal oxidation method. Next, as shown in FIG. 13 (d), a part of the first gate oxide [10] on the drain 16 is etched away by a PR process to expose the semiconductor surface of the drain, and a photoresist gate oxide film 11 is removed. It is formed by a thermal oxidation method.Next, a first polycrystalline silicon film doped with n-type is formed and buttered to form a floating gate 12.At this time, the floating gate is formed by a thin second gate oxide film 11. The gate oxide extends from the first gate oxide ridge between the source and drain so as to completely cover the floating gate.Next, as shown in FIG. A gate oxide film 13 is formed, and then a second n-type doped polycrystalline silicon film is formed and patterned to form a control gate 14.

[Problem that the invention seeks to solve]

The above-mentioned conventional E'' FROM memory transistor has a drawback in that there are large unstable factors in the characteristics described below.

As described above, the write/erase characteristics of the memory transistor can be achieved by efficiently and stably concentrating the electric field on the thin third gate oxide film, thereby achieving stable characteristics in which the charge moves quickly. In a write operation, electrons are extracted from a state in which the voltage RQF in the floating gate is negative, making Q a positive state, and in an erase operation, conversely, electrons are injected into the floating gate from a positive state, making Qp a negative state. . When Q, which is the transition state between the written state and the erased state, is near zero, the electric field applied to the thin second gate oxide film during writing is expressed by t2, where t2 is the thin second gate oxide film, and V
O is a positive high potential applied to the drain, and is represented by the electric field Ep applied to the thin second gate oxide film during erasing. Here, VCtl is a positive potential applied to the control gate. EV to increase writing and erasing speed
, by increasing EE, and stability of write/erase characteristics can be achieved by suppressing variations in EV and EE.

However, according to the prior art, due to the misalignment margin as described below around the second thin gate oxide film, Cp
o has to become large, and CFD due to eye misalignment.
This has the major disadvantage that the writing/erasing speed is slow and has large variations due to fluctuations in the data. The boundary between the isolation field oxide film and the active region is a white ribbon (
There are many factors such as nitride ribbons) and protrusions on the silicon surface that deteriorate the properties of the oxide film.
It is undesirable for the second thin gate oxide film of the E2 PROM to cover that area from the viewpoint of E2 PROM memory characteristics (mainly durability). Therefore, it is necessary to provide a misalignment margin so that the second thin gate oxide film does not overlap the boundary between the isolation field oxide film and the active region. In addition, the second thin gate oxide film exists between the drain and the floating gate, and fluctuations in its area result in fluctuations in C2, resulting in characteristic fluctuations. A misalignment margin is required for each of the floating gate edge and the floating gate edge.

As described above, the conventional technology has the disadvantage that the CFD is large and includes variations due to misalignment, resulting in slow write/erase speed and large variations.

・The purpose of the present invention is to reduce the additional capacitance other than the capacitance of the second thin gate oxide film between the drain and the floating gate, and to be able to manufacture it stably, resulting in high speed, stable write/erase characteristics with small fluctuations. An object of the present invention is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same.

1゛Means for Solving the Problems] A nonvolatile semiconductor memory device according to the first aspect of the present invention has a source and a drain of a conductivity type opposite to that of the semiconductor substrate, which are provided on one main surface of a semiconductor substrate of one conductivity type. and a first gate insulating film formed on the semiconductor substrate between the two regions, and facing the drain region through a thin second gate insulating film in at least a part of the drain region. In a nonvolatile semiconductor memory device having a floating gate formed as shown in FIG. A part of the drain region extending under the field insulating film for isolation and the floating gate are formed under the field insulating film for isolation.
The openings formed by soching removal are arranged to face each other with a thin second gate insulating film interposed therebetween.

Further, the method for manufacturing a nonvolatile semiconductor memory device according to the second aspect of the present invention includes the steps of forming a diffusion layer region of a conductivity type opposite to that of the semiconductor substrate on the main surface of a semiconductor substrate of one conductivity type; forming a field insulating film for isolation so that a part of the field insulating film extends to the active region; and forming a first gate insulating film on the diffusion layer region of the active region and on the semiconductor substrate: [Then, after etching and removing the field insulating film for insulation isolation in a part of the diffusion layer region E to expose the diffusion layer region, a second layer is etched in the diffusion layer region E.
forming a floating gate covering and concealing the second goo insulating film and extending from the first gate oxide ridge above the active region; The method includes a step of forming source and drain regions of opposite conductivity types to the active region so that the diffusion layer region and the drain region are connected to each other.

1. Embodiments] Next, five embodiments of the present invention will be described with reference to the drawings. FIG. 1(a) is a plan view of the first embodiment of the present invention, and FIG. 1(b) and FIG. 1(c) are the plan view of the first embodiment of the present invention.
FIG. 1 (a>, (h>).

(In (~), 15 is a drain region, 16 is a source region, 12 is a floating gate, and 14 is a control gate.8
is a drain extending under the field oxide film for insulation isolation.
(The second gate is thinner at the floating gates 12 and 11 in the area)
- Opposing each other via an oxide film (1-channel oxide film). 7 is a p-type semiconductor substrate, 15° and 16 are n-type drain and source regions, 8 is a field oxide film for insulation isolation (drain region extending below with a thickness of about 1.0 μm), and 2 is a floating gate. Approximately 500 mm of semiconductor substrate between source and drain
A drain region 8L extending under the field oxide film is an opening formed by etching and removing the field oxide film in the first gate I-oxide 1 pattern 10-F with a thickness of ~800 mm.
A second gate oxide film having a thickness of about 100 to 150 nm is formed on the second gate oxide film and extends like a scrap. , 14 is a control gate, and the third gate oxide film 1 is about 500 to 800 thick.
3. The most characteristic feature of the memory transistor structure according to the present invention shown in the above is that a misalignment margin is provided around the second thin gate oxide 1 pattern as seen in the prior art, so that the drain and floating gate are aligned with the first data. 1- The portions that were facing each other through the oxide film no longer exist. The field oxide film 9 between the drain region 8 and the floating data 1-12 is about 1.0 .mu.m thick, which is the misalignment margin between the drain region and the second gate oxide film, so that Coo is sufficiently small to be ignored.

FIGS. 2(a), (b) to FIG. 7(a>, (b) show elements A-A', B shown in order of steps to explain an embodiment of the second invention of the present invention. -B'' line. In this embodiment, a method for manufacturing a memory transistor will be explained.

First, as shown in FIGS. 2(a) and (1), an n-type diffusion layer region 8 is selectively formed near the surface of a p-type semiconductor substrate 7 by, for example, As ion implantation.

Next, as shown in FIGS. 3(a) and (b), Locos
Field oxidation g for insulation isolation with a thickness of approximately 1.0 μm
form 9. At this time, n-type diffusion layer region 8 extends from the activation region to below field oxide film 9.

Next, as shown in FIGS. 4(a) and (b), about 500~
800 people's 1st Gate Oxidation II! 10 is formed by a thermal oxidation method. Then, field oxidation y! The field oxide film on a part of the n-type diffusion layer region 8 extending below A9 is removed by etching by a photoresist process to expose the rl-type diffusion layer region.

Next, as shown in FIG.
1 is formed on the exposed n-type diffusion layer region, and then a floating gate 12 made of n-type doped polycrystalline silicon is formed.

Next, as shown in FIGS. 6(a) and 6(b), an n-type source region 16, a drain region 1
form 5. At this time, n-type diffusion region 8 extending below field oxide film 9 and drain region 15 are connected. In addition, since the distance between the source and drain, which is the channel length, is matched with the floating gate length, the floating goose 1--drain over 11 portion is only X due to the lateral diffusion of the drain impurity As, and the conventional technology There is no variation in the overlap area due to the misalignment margin between the drain and floating gate, and there is no variation in the overlap area due to the misalignment. Therefore, CPD can be kept small.

Next, as shown in FIGS. 7(a) and 7(b), a third gate oxide film 13 of approximately 500 to 800 layers is formed on the floating gate by thermal oxidation, and an n-type doped film is formed on the third gate oxide film 13 by thermal oxidation. A control gate 14 made of polycrystalline silicon is formed.

As a result of the above, the memory I/transistor structure of one embodiment of the present invention shown in FIGS. 1(a>, (b), and (c)) is obtained.

Also, FIGS. 8(a), (b) to 10(a)(b)
5(a>, (b) to FIG. 7(a) of the above embodiment).
This is another example of the process shown in >, (b).

That is, as shown in FIGS. 8(a) and (b), the n-type doped polycrystalline silicon layer forming the floating gate 12 is After etching and removing it in alignment with the control gate 14 made of polycrystalline silicon, as shown in FIGS. 10(a) and 10(b),
Even if the source region 16 and drain region 15 are formed by the As ion implantation method and the n-type diffusion region 8 under the field oxide film 9 is connected to the drain region 15 at this time, the effects of the present invention will not be impaired.

[Effects of the Invention] As explained above, the present invention provides a misalignment margin around the second thin glue oxide film as seen in the prior art, so that the drain and floating gate are aligned with the first gate. -A field oxide film with a thickness of about 1.0 μm between the drain and floating gate is sufficient for the part where there is no part facing each other with an oxide film interposed therebetween, and which becomes the misalignment margin between the drain region and the second gate oxide film part. Since it is thick, the CFD is sufficiently small. Furthermore, since the source drain is aligned with the floating gate, there is no overlap between the drain and the floating gate, and there is no variation in the overlap area due to misalignment, as seen in the prior art. The only difference is X due to lateral diffusion of drain impurities. As described above, the memory transistor according to the present invention has the smallest additional capacitance CPD other than the capacitance C2 of the second thin gate oxide film between the drain and the floating gate, and is stable because it does not include variations due to misalignment. Can be made smaller. As a result, the electric field can be stably and efficiently concentrated on the I-channel oxide film, and stable write/erase characteristics can be obtained at high speed and with small fluctuations.

[Brief explanation of drawings]

FIGS. 1(a), (b), and (c) are the first embodiments of the present invention, respectively.
A schematic plan view, A-A sectional view, and B of one embodiment of the invention of
-B sectional view, Fig. 2 (a), (b) to Fig. 7 (a>,
(b) is an AA' sectional view and a BB' sectional view shown in the order of steps for explaining the second invention of the present invention, and FIG.
), (b) to FIG. 10 (a), (b) are the second embodiments of the present invention.
Figures 5 (a>, (b) to 7 (a), (b) of the invention of
11(a) and 11(b) are a schematic plan view of a conventional memory transistor and its AA' sectional view. , FIG. 12 is an equivalent circuit diagram showing the capacitive coupling between each electrode of the memory transistor shown in FIG. 11 (a>, (b)), and FIG. 13 (a) to FIG.
(e) is a cross-sectional view of an element shown in order of steps to explain a conventional method of manufacturing a memory transistor. 7... P-type semiconductor substrate, 8... Drain region extending under the field oxide film for insulation isolation, 9... Field oxide film for isolation isolation, 10... First gate oxide film,
11... Second gate oxide film, 12... Floating gate, 13... Third gate oxide film, 14... Control gate), Cr... Floating gate-semiconductor substrate capacitance,
C2...Floating game in the second gate oxide film part? --Drain capacitance, C3...Floating gate I--control gate capacitance, CFs...Floating gate-source capacitance, CFD
・Capacitance between floating gate and drain other than C2. 1111"艷、／、、、。!' 71-4 Do mountain enemy formation 11 reception lθS 彎 11th gate ﾾ promotion stubborn 3 betsugo 4 autopsy) 6 Kanuma 7 drunken θ country Kayo fan 1θ Time Ylzki Kayano'3 Kō]

Claims (2)

[Claims] (1) Source and drain regions of a conductivity type opposite to that of the semiconductor substrate provided on one main surface of the semiconductor substrate of one conductivity type, and a first gate insulating film formed on the semiconductor substrate between the two regions; a floating gate formed in at least a part of the drain region so as to face the drain region with a thin second gate insulating film interposed therebetween; and a third gate insulating film formed on the floating gate with a third gate insulating film interposed therebetween. In a nonvolatile semiconductor memory device having a control gate, the drain region extends under a field insulating film for isolation, and a part of the drain region extends under the field insulating film for isolation. The floating gate is formed by etching away the field insulating film for isolation, and forming a thin second
A nonvolatile semiconductor memory device characterized in that two gates are opposed to each other with a gate insulating film interposed therebetween. (2) A step of forming a diffusion layer region of a conductivity type opposite to that of the semiconductor substrate on the main surface of a semiconductor substrate of one conductivity type, and an insulating isolation field such that a part of the diffusion layer region extends to the activation region. forming an insulating film; forming a first gate insulating film on the diffusion layer region of the activation region and on the semiconductor substrate; after etching away the field insulating film to expose the diffusion layer region, forming a second gate insulating film on the diffusion layer region; covering the second gate insulating film and exposing the diffusion layer region; a step of forming a floating gate extending from above the first gate oxide film; and a step of forming a floating gate extending from above the first gate oxide film; 1. A method of manufacturing a nonvolatile semiconductor memory device, the method comprising: forming a nonvolatile semiconductor memory device as if it were connected.