KR100214516B1 - Eeprom cell and manufacturing method thereof - Google Patents
Eeprom cell and manufacturing method thereof Download PDFInfo
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- KR100214516B1 KR100214516B1 KR1019960052007A KR19960052007A KR100214516B1 KR 100214516 B1 KR100214516 B1 KR 100214516B1 KR 1019960052007 A KR1019960052007 A KR 1019960052007A KR 19960052007 A KR19960052007 A KR 19960052007A KR 100214516 B1 KR100214516 B1 KR 100214516B1
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- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000926 separation method Methods 0.000 claims abstract description 3
- 238000007667 floating Methods 0.000 claims description 14
- 230000005641 tunneling Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
본 발명은 이이피롬 셀 및 그 제조방법에 관한 것으로, 기판에 웰을 형성하고 분리공정으로 채널이 형성될 영역과 필드 산화막을 분리한 다음 채널이 형성될 영역에 채널산화막을 형성하는 공정과, 이후 포토레지스트로 매몰 접합영역이 형성될 영역을 정의하고 이온주입 공정으로 매몰 접합영역을 형성하는 공정과, 이후 상기 포토레지스트를 마스크로 채널 산화막 및 매몰 접합영역을 식각하여 터널창을 형성하는 공정과, 이후 상기 포토레지스트를 제거하고 상기 터널창 내에 터널산화막을 형성하는 공정과, 부유게이트, 제어게이트 및 소스/드레인을 형성하는 공정으로 구현되는 이이피롬 셀을 제공하는데, 이러한 본 발명은 특별히 양질의 얇은 터널산화막을 요구하지 않으며 터널 산화막과 터널산화막을 동시에 조절가능하므로 공정을 단순화할 수 있는 효과가 있다. 또한, 프로그램/소거 동작이 이루어지는 패스가 서로 다르므로 막질이 저하되는 문제를 해결할 수 있으므로 소자의 신뢰성을 향상시킬 수 있으며, 큰 커플링 레이쇼가 아니더라도 셀이 동작하며 터널산화막의 성장시 텍스쳐드 산화막(textured oxide)이 형성되어 프로그램/소거의 효율을 증가시킬 수 있는 효과가 있다.The present invention relates to an ipyrom cell and a method of manufacturing the same, which comprises forming a well in a substrate, separating a region where a channel is to be formed from a field oxide layer by a separation process, and then forming a channel oxide layer in a region where the channel is to be formed. Defining a region where the buried junction region is to be formed by photoresist and forming a buried junction region by an ion implantation process, and then forming a tunnel window by etching the channel oxide film and the buried junction region using the photoresist as a mask; Thereafter, the photoresist is removed, and a tunnel oxide film is formed in the tunnel window, and a buried gate, a control gate, and a source / drain are formed by a process of providing an ipyrom cell. It does not require tunnel oxide and can control tunnel oxide and tunnel oxide at the same time, simplifying the process. That there is an effect. In addition, since the program / erase operation paths are different, the problem of deterioration in film quality can be solved, and thus the reliability of the device can be improved. (textured oxide) is formed to increase the efficiency of the program / erase.
Description
본 발명은 이이피롬 셀 및 그 제조방법에 관한 것으로, 특히 프로그램 및 소거의 측면에서 고효율성을 기대할 수 있는 이이피롬 셀 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ipyrom cell and a method of manufacturing the same, and more particularly, to an ipyrom cell and a method of manufacturing the same which can be expected to have high efficiency in terms of programming and erasing.
종래의 이이피롬 셀의 제조방법에 대해 도 1을 참조하여 설명하면 다음과 같다.Referring to Figure 1 with respect to the conventional method of manufacturing a pyromium cell as follows.
먼저, 도1(a)에 도시한 바와 같이 기판(1)에 웰을 형성하고 분리(isolation) 공정으로 채널이 형성될 영역과 필드 산화막(3)을 분리한 다음 채널이 형성될 영역에 채널 산화막(즉, 게이트 산화막)(2)을 형성한다.First, as shown in FIG. 1A, a well is formed in the substrate 1, and a region in which a channel is to be formed and a field oxide layer 3 are separated by an isolation process, and then a channel oxide layer is formed in a region in which a channel is to be formed. (I.e., gate oxide film) 2 is formed.
이어서, 도 1(b)에 도시한 바와 같이 기판(1) 내에 매몰 접합 영역(4)이 형성될 영역을 정의하고 엔타입으로 도핑한 다음 열처리 공정을 거쳐 매몰 접합영역(4)을 형성한다. 이후, 상기매몰 접합영역(4) 내에 매몰산화막(5)을 500∼1000Å의 두께로 형성한다. 그 다음, 도 1(c)에 도시한 바와 같이 상기 매몰산화막(5)을 식각하여 터널창(6)을 형성한 다음 이터널창(6) 내에 터널산화막(7)을 80Å이하의 두께로 형성하는데, 이때 터널산화막(7)의 두께 조절이 공정의 핵심이라고 할 수 있다.Subsequently, as illustrated in FIG. 1B, a region in which the buried junction region 4 is to be formed in the substrate 1 is defined, doped into an N type, and then the buried junction region 4 is formed through a heat treatment process. Thereafter, the buried oxide film 5 is formed in the buried junction region 4 to a thickness of 500 to 1000 GPa. Next, as shown in FIG. 1C, the buried oxide film 5 is etched to form a tunnel window 6, and then the tunnel oxide film 7 is formed in the eternal window 6 to a thickness of 80 kPa or less. At this time, it can be said that the thickness control of the tunnel oxide film 7 is the core of the process.
이후, 도 1(d)에 도시한 바와 같이 일반적인 스프리트 게이트(split gate)구조의 이이피롬과 동일하게 공정을 진행시킨다.Thereafter, as shown in FIG. 1 (d), the process is performed in the same manner as in the case of Y pyrom having a common split gate structure.
즉, 폴리실리콘을 증착 및 식각하여 부유게이트(8)를 형성하고 폴리간 산화막(9)을 형성한 다음 그 위에 다시 폴리실리콘을 증착 및 식각하여 제어 게이트(10)를 형성하고, 마지막으로 소스(13) 및 드레인(12)을 형성한다.That is, the polysilicon is deposited and etched to form the floating gate 8, the interpoly oxide film 9 is formed, and then the polysilicon is deposited and etched again to form the control gate 10, and finally, the source ( 13) and drain 12 are formed.
이때, 도 1(d)에서 알 수 있는 바와 같이 선택 트랜지스터(11)가 형성된다.At this time, as shown in FIG. 1 (d), the selection transistor 11 is formed.
이와같은 종래 이이피롬 셀의 동작에 대해 도 1(d)를 참조하여 설명하면, 아울러 노드하임 터널링(F-N Tunneling)에 의해 얇게 형성된(80Å) 터널산화막(7)으로 매몰 접합영역(6)의 전자를 주입하고 빼내옴으로써 프로그램 및 소거가 이루어진다(도면의 화살표 방향).Referring to FIG. 1 (d), the operation of the conventional Y-pyrom cell is thinly formed by FN Tunneling. 80 ms) Program and erase are performed by injecting and withdrawing electrons from the buried junction region 6 into the tunnel oxide film 7 (arrow direction in the drawing).
이때, 선택트랜지스터(11)의 온/오프에 의해 셀을 선택적으로 프로그램/소거할 수 있다.In this case, the cell may be selectively programmed / erased by turning on / off the selection transistor 11.
그러나, 상기와 같은 종래의 기술은, 터널산화막(7)을 통해서 전자의 주입이 이루어짐으로 질이 매우 좋은 얇은 산화막의 형성을 요구하는데, 이 터널산화막(7)은 채널산화막(3) 보다 훨씬 얇게 형성해야 하므로 두 산화막을 분리하여 각각 형성해야 하는 번거로움이 있다.However, the conventional technique as described above requires the formation of a thin oxide film of very good quality due to the injection of electrons through the tunnel oxide film 7, which is much thinner than the channel oxide film 3. Since there is a need to form, there is a hassle to separate the two oxide film to form each.
또한 , 상기 터널 산화막(7)의 동일 위치에서 전자가 주입되고 소거되므로 프로그램/소거 동작이 반복될 경우 터널 산화막(7)의 막질 저하에 따른 신뢰성 저하의 문제가 발생한다.In addition, since electrons are injected and erased at the same position of the tunnel oxide film 7, when the program / erase operation is repeated, a problem of deterioration in reliability due to a decrease in film quality of the tunnel oxide film 7 occurs.
또한, 터널산화막(7) 간의 높은 전압강하를 필요로 하는 파울러 노드하임 터널링(F-N Tunneling)에 의해 프로그램/소거 동작이 이루어지므로 프로그램/소거 전압 또한 높은 전압이 요구되고 높은 커플링 레이쇼(Coupling ratio)를 갖는 셀의 디자인 및 공정 기술이 요구되는 문제가 발생하게 된다.In addition, since the program / erase operation is performed by FN Tunneling, which requires a high voltage drop between the tunnel oxide films 7, the program / erase voltage also requires a high voltage and a high coupling ratio. A problem arises that requires the design and processing technology of a cell with
본 발명은 상기와 같은 종래의 문제를 해결하기 위하여 창안된 것으로, 매몰 접합영역과 부유게이트간의 에쥐(edge)에 집중된 필드를 이용하여 전자의 주입이 이루어지게 함으로써, 양질의 얇은 터널산화막의 형성을 요구하지 않고서도 높은 효율을 얻을 수 있도록 한 이이피롬 셀 및 그 제조방법을 제공함에 그 목적이 있다.The present invention was devised to solve the conventional problems as described above, and the electrons are injected by using a field concentrated at the edge between the buried junction region and the floating gate, thereby forming a thin tunnel oxide film of good quality. It is an object of the present invention to provide an ypyrom cell and a method for manufacturing the same, which can achieve high efficiency without requiring it.
제1a도 내지 d도는 종래 이이피롬 셀의 제조를 나타낸 공정수순도.1a to d is a process flowchart showing the manufacturing of conventional ypyrom cells.
제2a도 내지 e도는 본 발명 이이피롬 셀의 제조를 나타낸 공정수순도.2a to e is a process flowchart showing the production of the present invention pyromium cell.
제3도은 이이피롬 셀의 동작의 조건을 나타낸 표.3 is a table showing the conditions of operation of the Y pyrom cell.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20 : 기판 21 : 터널산화막20 substrate 21 tunnel oxide film
22 : 필드산화막 23 : 포토레지스트22: field oxide film 23: photoresist
24 : 매몰 접합 영역 25 : 터널창영역24: investment junction area 25: tunnel window area
26 : 터널산화막 27 : 부유게이트26 tunnel oxide layer 27 floating gate
28 : 폴리간 산화막 29 : 제어게이트28: poly interoxide oxide film 29: control gate
30 : 선택 트랜지스터 31 : 소스30: select transistor 31: source
32 : 드레인32: drain
상기와 같은 목적을 달성하기 위한 본 발명 이이피롬 셀의 제조방법은, 기판상에 웰을 형성하고 분리공정으로 채널이 형성될 영역과 필드산화막을 분리한 다음 채널이 형성될 영역에 터널산화막을 형성하는 공정과, 이후 포토레지스트로 매몰 접합영역이 형성될 영역을 정의하고 이온주입 공정으로 매몰 접합영역을 형성하는 공정과, 이후 상기 포토레지스트를 마스크로 채널 산화막 및 매몰 접합영역을 식각하여 터널창을 형성하는 공정과, 이후 상기 포토레지스트를 제거하고 상기 터널창 내에 터널산화막을 형성하는 공정과, 부유게이트 제어게이트 및 소스/드레인을 형성하는 공정으로 본 발명의 공정이 완료된다.In order to achieve the above object, the present invention provides a method of manufacturing a pyromium cell, by forming a well on a substrate and separating a region in which a channel is formed and a field oxide layer by a separation process, and then forming a tunnel oxide in a region in which a channel is to be formed. And forming a buried junction region using a photoresist, and forming a buried junction region by an ion implantation process, and then etching the channel oxide film and the buried junction region using the photoresist as a mask. The process of the present invention is completed by forming, removing the photoresist and forming a tunnel oxide film in the tunnel window, and forming a floating gate control gate and a source / drain.
상기와 같은 공정에 의해 구현된 본 발명 이이피롬 셀은, 기판과, 상기 기판내에 트랜치 구조의 터널창을 이루며 형성된 매몰 접합영역과, 상기 터널창 내에 형성된 터널산화막과, 상기 매몰 접합영역 내 터널산화막 위의 영역을 포함하여 형성되는 부유게이트와, 상기 부유게이트와 폴리간 산화막을 사이에 두고 형성되는 제어게이트와, 기판내의 소스 및 드레인으로 구성된다.The present ypyrom cell implemented by the above process, the buried junction region formed by forming a tunnel window of the trench structure in the substrate, the tunnel oxide film formed in the tunnel window, the tunnel oxide film in the buried junction region A floating gate formed including the above region, a control gate formed with the floating gate and an inter-poly oxide film interposed therebetween, and a source and a drain in the substrate.
이와같은 본 발명에 대해 도 2 및 도 3을 참조하여 설명하면 다음과 같다.This invention will be described with reference to FIGS. 2 and 3 as follows.
먼저, 도 2(a) 도시한 바와 같이 기판(20)에 웰을 형성하고 분리(isolation) 공정으로 채널이 형성될 영역과 필드산화막(22)을 분리한 다음 채널이 형성될 영역에 채널산화막(즉, 게이트 산화막)(21)을 형성한다.First, as shown in FIG. 2 (a), a well is formed in the substrate 20, and a region in which a channel is formed and a field oxide layer 22 is separated by an isolation process, and then a channel oxide layer ( That is, the gate oxide film 21 is formed.
이어서, 도 2(b)에 도시한 바와 같이 기판(20) 내에 매몰 접합영역(24)이 형성될 영역을 포토레지스트(23)로 정의하고 엔타입으로 도핑한 다음 열처리 공정을 거쳐 매몰 접합영역(24)을 형성한다.Subsequently, as shown in FIG. 2B, a region in which the buried junction region 24 is to be formed in the substrate 20 is defined as a photoresist 23, doped in an N type, and then a buried junction region is subjected to a heat treatment process. 24).
이후, 도 2(c)에 도시한 바와 같이 상기 포토레지스트(23)를 마스크로 하여 채널산화막(21) 및 매몰 접합영역(24)을 건식 식각하여 트랜치 구조의 터널창(25)을 형성한다. 이때, 매몰접합영역(24)의 접합깊이를 넘어가지 않도록 매몰 접합영역(24) 내에서 식각이 끝나도록 주의한다.Thereafter, as shown in FIG. 2C, the channel oxide film 21 and the buried junction region 24 are dry-etched using the photoresist 23 as a mask to form a trench window 25 having a trench structure. At this time, care should be taken so that etching is completed in the buried junction region 24 so as not to exceed the junction depth of the buried junction region 24.
그 다음, 도 2(d)에 도시한 바와 같이 상기 포토레지스트(23) 및 채널산화막(21)을 제거하고 터널창(25) 내에 터널산화막(26)을 형성하는데 , 이때 터널산화막(26) 및 채널산화막(25')을 동시에 형성할 수 있게 된다.Next, as shown in FIG. 2 (d), the photoresist 23 and the channel oxide film 21 are removed and the tunnel oxide film 26 is formed in the tunnel window 25, wherein the tunnel oxide film 26 and It is possible to simultaneously form the channel oxide film 25 '.
따라서, 프로그램/소거 동작이 매몰 접합영역(24)과 부유게이트(27) 간의 샤프(sharp)한 에쥐(edge)부의 필드에 의존하여 이루어지므로 터널산화막(26)의 두께를 특별히 조절할 필요가 없기 때문이다. 이에 따라, 공정이 단순해진다.Therefore, since the program / erase operation is performed depending on the sharp edge portion field between the buried junction region 24 and the floating gate 27, there is no need to adjust the thickness of the tunnel oxide layer 26 in particular. to be. This simplifies the process.
또한, 상기 터널산화막(26)은 건식 식각된 매몰 접촉창의 에쥐 및 표면에 형성되므로 택스쳐드 산화막(textured oxide)이 형성되어 필드 인헨스먼트(field enhancement)에 의해 프로그램/소거 효율이 증대된다. 즉, 스피드가 향상된다.In addition, since the tunnel oxide layer 26 is formed on the edge and the surface of the dry-etched buried contact window, a textured oxide layer is formed to increase program / erase efficiency by field enhancement. That is, speed is improved.
따라서, 터널산화막(26)의 두께에 영향을 받지않게 된다.Therefore, the thickness of the tunnel oxide film 26 is not affected.
마지막으로, 도 2(e)에 도시한 바와 같이 일반적인 스프리트 게이트(split gate)구조의 이이피롬과 동일하게 공정을 진행시킨다.Finally, as shown in FIG. 2 (e), the process proceeds in the same manner as in the case of Y. pyrom of the general split gate structure.
즉, 폴리실리콘을 증착 및 식각하여 터널창(25) 영역을 포함하는 부유게이트(27)를 형성하고 폴리간 산화막(28)을 형성한 다음 그위에 다시 폴리실리콘을 증착 및 식각하여 제어 게이트(29)를 형성하고, 마지막으로 소스(31) 및 드레인(32)을 형성한다.That is, polysilicon is deposited and etched to form a floating gate 27 including the tunnel window 25 region, an interpoly oxide layer 28 is formed, and then polysilicon is deposited and etched on the control gate 29. ), And finally, the source 31 and the drain 32 are formed.
이때, 도 1(e)에서 알 수 있는 바와 같이 선택 트랜지스터(30)가 형성된다.At this time, as shown in FIG. 1E, the selection transistor 30 is formed.
이와 같은 본 발명의 동작은 종래와 마찬가지로 파울러 노드하임 터널링(F-N Tunneling)에 의해 터널산화막(26)으로 매몰 접합영역(24)의 전자를 주입하고 빼내옴으로써 프로그램 및 소거가 이루어지며 선택 트랜지스터(30)의 온/오프에 의해 셀을 선택적으로 프로그램/소거할 수 있는데 , 이를 도 3을 참조하여 좀 더 상세히 설명하면 다음과 같다.The operation of the present invention is programmed and erased by injecting and withdrawing electrons from the buried junction region 24 into the tunnel oxide layer 26 by FN Tunneling as in the related art. The cell can be selectively programmed / erased by turning on / off of the same), which will be described in more detail with reference to FIG. 3 as follows.
먼저, 프로그램은 도 3(b)의 조건으로 소스(32) 및 제어게이트(29)에 높은 전압(Vpp)을 인가하고 비트라인(즉, 드레인)(31)에 접지(GND) 시킴으로써 동작이 이루어지는데, 이는 터널창(25)에서 매몰 접합영역(24)과 부유게이트(27)의 샤프(sharp)한 에쥐(edge)에 필드가 집중이 되어 주고 패스①을 통해 전자가 부유게이트(27)로 주입된다.First, the program is operated by applying a high voltage Vpp to the source 32 and the control gate 29 and grounding the bit line (ie, the drain) 31 under the condition of FIG. 3 (b). This is because the field is concentrated on the sharp edge of the buried junction region 24 and the floating gate 27 in the tunnel window 25, and electrons are transferred to the floating gate 27 through the pass ①. Is injected.
이 경우 종래의 플랫(flat)한 면을 통해 주입되는 것보다 로우 필드(low field)에서도 전자의 주입이 가능하다.In this case, electrons can be injected even in a low field rather than through a conventional flat surface.
다음으로, 소거는 도 3(a)의 조건으로 종래와 같은 원리로 패스②를 통해 부유게이트(27)의 전자를 빼내옴으로써 이루어진다.Next, the erasing is performed by drawing electrons of the floating gate 27 through the path ② on the same principle as the conventional condition under the condition of FIG. 3 (a).
이때, 프로그램/소거를 위한 높은전압(Vpp)을 종래 보다 낮출 수 있어 종래 고전압(high voltage) 소자 기술의 어려움을 덜어줄 수 있다.At this time, the high voltage (Vpp) for the program / erase can be lowered than the conventional can reduce the difficulty of the conventional high voltage (high voltage) device technology.
이와 같은 본 발명은 특별히 양질의 얇은 터널산화막(26)을 요구하지 않으며 터널산화막(26)과 채널산화막(21')을 동시에 조절가능하므로 공정을 단순화할 수 있는 효과가 있다.The present invention does not require a particularly thin tunnel oxide film 26 of high quality, and can simultaneously control the tunnel oxide film 26 and the channel oxide film 21 ', thereby simplifying the process.
또한, 프로그램/소거 동작이 이루어지는 패스가 서로 다르므로 막질이 저하되는 문제를 해결할 수 있으므로 소자의 신뢰성을 향상시킬 수 있다.In addition, since the paths through which the program / erase operations are performed are different from each other, the problem of deterioration in film quality can be solved, thereby improving the reliability of the device.
또한, 큰 커플링 레이쇼가 아니더라도 셀이 동작하며 터널산화막(26)의 성장시 텍스쳐드 산화막(textured oxide)이 형성되어 프로그램/소거의 효율을 증가시킬 수 있는 효과가 있다.In addition, even if a large coupling race is not present, the cell operates and a textured oxide is formed when the tunnel oxide layer 26 is grown, thereby increasing the program / erase efficiency.
Claims (5)
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