JPS62206857A - Forming method for projection-shaped electrode - Google Patents
Forming method for projection-shaped electrodeInfo
- Publication number
- JPS62206857A JPS62206857A JP61048413A JP4841386A JPS62206857A JP S62206857 A JPS62206857 A JP S62206857A JP 61048413 A JP61048413 A JP 61048413A JP 4841386 A JP4841386 A JP 4841386A JP S62206857 A JPS62206857 A JP S62206857A
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- copper
- electrode
- capillary
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 63
- 239000010949 copper Substances 0.000 abstract description 54
- 229910052802 copper Inorganic materials 0.000 abstract description 52
- 230000015572 biosynthetic process Effects 0.000 abstract description 18
- 239000004065 semiconductor Substances 0.000 abstract description 17
- 239000010931 gold Substances 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 235000015115 caffè latte Nutrition 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、半導体チップ実装のために設けら4−−■
二と、空1j−II”tl?kl;MIIシGrn−−
1−j:ノ雷=1−)L!!l−4−1(従来の技術)
従来より、半導体チップを実装するため半導体チップ、
配線基板或はその他の基板のド地Eに形成された配線層
に、銅(Cu )ポール及び半田(Pb−Sn)から成
る突起状電極を形成する方法が提案されている。[Detailed Description of the Invention] (Industrial Application Field) The present invention provides a method for mounting semiconductor chips.
2 and the sky 1j-II"tl?kl; MIIshiGrn--
1-j: no thunder=1-)L! ! l-4-1 (Conventional technology) Conventionally, in order to mount semiconductor chips, semiconductor chips,
A method has been proposed in which protruding electrodes made of copper (Cu) poles and solder (Pb--Sn) are formed on a wiring layer formed on a ground E of a wiring board or other substrate.
第3図は従来方法によって形成された突起状電極を示す
断面図である。この突起状電極を7リツプチツプ11ヒ
に設けた配線層13hに形成する。この配線層13は一
般にはアルミニウムにシリコンを添加して成るA交eS
t層(A文バッド) 17、酸化lQ(パッシベーショ
ン膜) 19、バリア層としての金属層21.23.2
5から成っている。FIG. 3 is a sectional view showing a protruding electrode formed by a conventional method. This protruding electrode is formed on the wiring layer 13h provided on the seven-lip chip 11. This wiring layer 13 is generally made of aluminum with silicon added.
T layer (A pattern bad) 17. Oxidized lQ (passivation film) 19. Metal layer as barrier layer 21.23.2
It consists of 5.
この従来の突起状電極の形成方法につ3第3図を参照し
て説明する。This conventional method for forming protruding electrodes will be explained with reference to FIG. 3.
先ず、配線層13Eに’MU (P’b −Sn )層
33をメッキ処理によって形成する。この時、焦電解メ
ッキで金属にッケルNi)層27及び金属(金Au)層
28が順次に表面に形成されている銅ポール31を多数
用意する。この銅ポール31は通常は125gm程度の
直径の微細なポールである。First, the 'MU (P'b-Sn) layer 33 is formed on the wiring layer 13E by plating. At this time, a large number of copper poles 31 are prepared, each of which has a metal (Ni) layer 27 and a metal (gold/Au) layer 28 sequentially formed on their surfaces by pyrolytic plating. This copper pole 31 is normally a fine pole with a diameter of about 125 gm.
次いで、配線層13の電極形成位置(A立・S1層17
の酸化膜19で覆われていない部分)に対応させた位置
に穴が設けられている金属マスク(アパーチャとも称す
)と、フリップチップ11との位置合せを行う。この位
置合せを行った状態でL述した銅ポール31を金属マス
クLへ振り注いで全ての穴に1個ずつ入れて、銅ポール
31をフリップチップ11の全ての電極形成位置に配置
する。Next, the electrode formation position of the wiring layer 13 (A vertical/S1 layer 17
The flip chip 11 is aligned with a metal mask (also referred to as an aperture) provided with a hole at a position corresponding to the portion not covered with the oxide film 19). With this alignment performed, the copper poles 31 described above are poured into the metal mask L and placed one in each hole, so that the copper poles 31 are arranged at all electrode formation positions of the flip chip 11.
この後、銅ポール31を半田層33丘に載置したまま、
ベルト炉において水素雰囲2中で半田層33の溶融を行
う、これによって、4753図に断面図で示すように銅
ポール31を半田層33丘に含んで成る突起状電極15
が形成される。After this, with the copper pole 31 placed on the solder layer 33 hill,
The solder layer 33 is melted in a hydrogen atmosphere 2 in a belt furnace, thereby forming a protruding electrode 15 comprising copper poles 31 in the solder layer 33 as shown in cross-section in FIG. 4753.
is formed.
(発明が解決しようとする問題点)
しかしながら、L述した従来方法では、銅ポールの位置
決めを金属マスクに設けた穴を用いて行なっているが非
常に微細なポールを金属マスクの穴に入れる作業が困難
であり、従ってこの穴入れ作業に多くの時間を要するた
め突起状1[極の形成か効率良く容易に行えないという
問題点があった。(Problems to be Solved by the Invention) However, in the conventional method described above, the copper poles are positioned using holes provided in the metal mask, but the process involves inserting very fine poles into the holes in the metal mask. The problem is that the formation of the protrusion 1 [pole] cannot be done efficiently and easily because it takes a lot of time to make the hole.
又、ポールを14 [11層にに配置するために金属マ
スクの穴位置をド地りの電極形成位置へ合せる作業が難
しく、シかもフリップチップ了のド地カニに位置合せを
行うので作業性が悪いという問題点があった。In addition, in order to arrange the poles in 14 [11 layers], it is difficult to align the hole position of the metal mask with the electrode formation position on the ground, and it may be difficult to align the holes on the ground of the flip chip. The problem was that it was bad.
又、ポールが配線層に固定されていないため、半導体チ
ップ交換時にポールが半導体チップ又は配線基板の何れ
か一方に片寄って残らずに半導体チップ及び配線基板の
両方へばらついて残ってしまう、この結果、従来方法に
よって形成した突起状電極では半導体チップの交換作業
が煩雑になるという問題点があった。In addition, since the poles are not fixed to the wiring layer, when replacing the semiconductor chip, the poles do not remain biased toward either the semiconductor chip or the wiring board, but instead remain spread out on both the semiconductor chip and the wiring board. However, with the protruding electrodes formed by the conventional method, there is a problem in that replacing the semiconductor chip becomes complicated.
この発明の目的は、L述した従来方法の問題点を解決し
、電極形成工程の筒中化を図って電極形成時の作業性及
び作業効率を向丘し、又、半導体チップ交換時の煩雑さ
を除去出来る突起状電極の形成方法を提供することにあ
る。The purpose of this invention is to solve the problems of the conventional method mentioned above, to improve the workability and efficiency of electrode formation by incubating the electrode formation process, and to reduce the complexity of replacing semiconductor chips. An object of the present invention is to provide a method for forming a protruding electrode that can be removed.
(問題点を解決するための手段)
この目的の達成を図るため、この発明の突起状電極の形
成方法によれば、半導体チップ、基板又はその他の好適
な下地Eに形成された配線層に対し金属ポール等の粒状
金属体を加圧接触させる工程と、この粒状金属体を配線
層に固定する工程とを含むことを特徴とする。(Means for Solving the Problems) In order to achieve this object, according to the method for forming a protruding electrode of the present invention, a wiring layer formed on a semiconductor chip, a substrate, or other suitable base material E is provided. The method is characterized by including a step of bringing a granular metal body such as a metal pole into contact with pressure, and a step of fixing the granular metal body to a wiring layer.
粒状金属体の加圧接触及び固定は、同時に行っても良い
し或は又この粒状金属体を配線層に加圧接触させた後に
両者の接触状態が保持されている間に固定を行っても良
い。粒状金属体の形状はポール形状に限定されず任意の
形状のものを用いることが出来、又、粒状金属体の形成
材料としてWA(Cu ) 、金(Au ) 、アルミ
ニウム(AIL)その他の材料を適宜に用いることが出
来る。Pressure contact and fixing of the granular metal body may be performed at the same time, or the granular metal body may be pressed into contact with the wiring layer and then fixed while the contact state between the two is maintained. good. The shape of the granular metal body is not limited to the pole shape, and any shape can be used. Also, WA (Cu), gold (Au), aluminum (AIL), and other materials can be used as the forming material of the granular metal body. It can be used as appropriate.
この発明の実施に当り、従来ICチップにワイヤをポン
ディングするために用いられているワイヤボンディング
技術を用いてこの加圧接触を行うのが好適である。In practicing the invention, it is preferred to make this pressure contact using wire bonding techniques conventionally used to bond wires to IC chips.
又、この発明の実施に当り、粒状金属体の固定を超音波
を用いて行うのが好適である。Further, in carrying out the present invention, it is preferable to use ultrasonic waves to fix the granular metal bodies.
(作用)
このような構成によれば、突起状電極の形成に当り、粒
状金属体を金属マスクの穴に入れる困難な作業を含まず
加圧接触と固定という筒中な工程の組合せによって突起
状電極の形成が行われる。(Function) According to such a configuration, when forming the protruding electrode, the protruding electrode is formed by a combination of the cylindrical processes of pressurized contact and fixing, without involving the difficult work of inserting the granular metal body into the hole of the metal mask. formation takes place.
又、この発明の構成によればL述したワイヤポンチイン
ク技術を適用して粒状金属体の電極形成位置への位置合
せを筒中化することが出来る。Further, according to the configuration of the present invention, by applying the wire punch ink technique described above, it is possible to align the granular metal bodies to the electrode forming positions in the cylinder.
又1粒状金属体を配線層に固定するので半導体チップの
交換時に粒状金属体は固定された配線層に必ず残る。Furthermore, since one granular metal body is fixed to the wiring layer, the granular metal body always remains on the fixed wiring layer when the semiconductor chip is replaced.
(実施例)
以丁、図面を参照しながらこの発明の実施例につき説明
する。尚、図はこの発明が理解出来る程度に概略的に示
しであるにすぎず、区、以ドに、説明する実施例では、
この発明の好ましい特定の数値的条件、材料、その他の
条件のrで説明するがこれらはriなる・例であるにす
ぎず、この発明はこれらの実施例にのみ限定されるもの
ではないことを理解されたい。(Embodiments) Examples of the present invention will now be described with reference to the drawings. It should be noted that the figures are only schematic illustrations to the extent that the invention can be understood, and the embodiments described below are as follows:
Although preferred specific numerical conditions, materials, and other conditions of this invention are explained below, these are merely examples, and it should be understood that this invention is not limited only to these examples. I want to be understood.
第1図(A)〜(F)は実施例の電極形成工程の説明図
である。この実施例においては従来通常用いられている
ワイヤポンティング装置を用いる場合につき説明する。FIGS. 1(A) to 1(F) are explanatory diagrams of the electrode forming process of the example. In this embodiment, a case will be explained in which a conventional wire pointing device is used.
7rSI図(A)において41はフランジ、43は銅ワ
イヤを示し、フランジ41には直径20gmの銅ワイヤ
41が巻かれている。又、45はクランプ、及び47は
ポンディングアーム49に支持されたセラミック製キャ
ピラリを示す。銅ワイヤ43はクランプ45を経てキャ
ピラリ47に挿通しである。銅ワイヤ43の先端には粒
状金属体として直径約100牌mの銅ホール(粒状体)
51が形成されている。ここで銅ワイヤ43に代え、
金(Au ) 、アルミニウム(All)その他の金属
iI!lI線を用いて粒状金属体を構成することも出来
る。In FIG. 7rSI (A), 41 is a flange, 43 is a copper wire, and the flange 41 is wound with a copper wire 41 having a diameter of 20 gm. Further, 45 indicates a clamp, and 47 indicates a ceramic capillary supported by a pumping arm 49. The copper wire 43 is inserted into the capillary 47 via the clamp 45. At the tip of the copper wire 43, there is a copper hole (granular body) with a diameter of about 100 tiles as a granular metal body.
51 is formed. Here, instead of the copper wire 43,
Gold (Au), aluminum (All) and other metals II! It is also possible to construct a granular metal body using II radiation.
53は、突起状電極を形成すべき配線層を具えた、f地
例えばフリップチップを示す。このr地は実装方式に応
じてフリップチップ以外の半導体チップ、配線基板その
他とすることが出来る。Reference numeral 53 indicates a flip chip, for example, a flip chip, which is provided with a wiring layer on which a protruding electrode is to be formed. This r ground can be a semiconductor chip other than a flip chip, a wiring board, or the like depending on the mounting method.
ところで、従来通常用いられるワイヤボンディング装置
によってICチ、プにワイヤのポンディングを行うには
、ワイヤの・端を半導体チップのポンティングバットヘ
ホンティングしくファーストポンド (工程))、次い
でワイヤの他端を配線基板の導体部ヘポンテインクする
(セカンドポンド (工程))というようにファースト
及びセカンドポンドをそれぞれ異なる位tで行うやしか
しながら、この発明の実施のためにワイヤボンディング
装置を使用する場合にはファースト及びセカンドポンド
を同一位置で行って以rに詳述するように突起状電極の
形成を行う。By the way, in order to bond a wire to an IC chip using a conventional wire bonding device, the end of the wire is first bonded to the bonding butt of the semiconductor chip (first bonding process), and then the other end of the wire is bonded to the bonding butt of the semiconductor chip. The first and second pounds are performed at different times, such as bonding the end to the conductor portion of the wiring board (second bonding process). However, when using a wire bonding machine to carry out this invention, and a second pound at the same position to form a protruding electrode as described in detail below.
突起状電極形成に当っては電極形成位置毎に1個の銅ポ
ール31を加圧接触し固定すれば良いのでまた2度打ち
による銅ポールの損傷を避けるために、ファーストポン
ドは、第1図(B)及び(C)に示すように、銅ポール
51の配線層への加圧接触・固定を行わない(空打ちす
る)。When forming protruding electrodes, it is only necessary to press and contact and fix one copper pole 31 at each electrode formation position.Also, in order to avoid damage to the copper pole due to double striking, the first pound is as shown in Fig. 1. As shown in (B) and (C), the copper pole 51 is not pressed into contact with or fixed to the wiring layer (blank firing).
先ず、キャピラリ47とフリップチップ53の位置合せ
によって銅ポール51を7リツプチツプ53の配線層従
って電極形成位置の直りに配置する。この位を合せの後
、銅ポール51及び配線層が接触しないように(例えば
銅ポール51が配線層1zO,5mmの位lに来るまで
)キャピラリ47を降′Fさせ(第1図CB))、次い
でキャピラリ47をE昇させて(詔1図(C) ) 、
ffiポール51のポンディングを行わずにファース
トポンドを終える。First, by aligning the capillary 47 and the flip chip 53, the copper pole 51 is placed directly on the wiring layer of the 7-lip chip 53, and therefore on the electrode formation position. After aligning these positions, lower the capillary 47 so that the copper pole 51 and the wiring layer do not come into contact with each other (for example, until the copper pole 51 comes to the wiring layer 1zO, 5 mm apart (FIG. 1 CB)). Then, raise the capillary 47 to E (Edict 1 (C)),
Finish the first pound without pounding ffi pole 51.
次にセカンドポンドでは、第1図(D)及び(E)に示
すように、銅ボール51の配線層への加圧接触及び内定
を行う。Next, in the second pound, as shown in FIGS. 1(D) and 1(E), the copper ball 51 is brought into pressure contact with the wiring layer and a preliminary decision is made.
先ず、キャピラリ47及びフリップチップ53はファー
ストポンド時と同−位置に保持したまま、従って電極形
成位置において配線層に対し銅ポール51を加圧接触さ
せる。銅ポール51の加圧接触はポンディングアーム4
3及びキャピラリ47によって50〜too gの負荷
荷重を負荷して行う。この加圧接触の後或は加圧接触と
同時に超音波を用いて銅ポール51を配線層に固定する
。この固定は加圧接触されている銅ポール51に超音波
を数ヒm5ecの間だけ照射して行う。銅ポール51の
加圧接触及びat丘波振動によって配線層と銅ポール5
1との接触面に合金が形成され、その結果銅ポール51
と配線層とが接合されると考えられている(7JS1図
(D))。First, while the capillary 47 and the flip chip 53 are held in the same position as at the time of the first pound, the copper pole 51 is pressed into contact with the wiring layer at the electrode forming position. The pressurized contact of the copper pole 51 is with the pounding arm 4
3 and capillary 47 with a load of 50 to too g. After or simultaneously with this pressure contact, the copper pole 51 is fixed to the wiring layer using ultrasonic waves. This fixation is performed by irradiating the copper pole 51, which is in pressurized contact, with ultrasonic waves for only a few seconds m5ec. The wiring layer and the copper pole 5 are connected to each other by pressure contact of the copper pole 51 and at hill wave vibration.
An alloy is formed on the contact surface with copper pole 51, resulting in the formation of an alloy on the contact surface with copper pole 51.
It is thought that the wiring layer and the wiring layer are bonded to each other (Fig. 7JS1 (D)).
銅ポール51の加圧接触及び固定の後、キャピラリ47
を適量丘昇させキャピラリ47の先端部に銅ワイヤ43
を所望の長さだけ突出させたままクランプ45によって
銅ワイヤ43を把持する。次いでキャピラリ47及びク
ランプ45を共にL昇させて、銅ワイヤ43と固定した
銅ポール51とを分離しセカンドポンドを終rする。こ
の結果、配線層には銅ポール51のみがポンディングさ
れて残る(第1図(E))。After pressurized contact and fixation of the copper pole 51, the capillary 47
A suitable amount of copper wire 43 is raised to the tip of the capillary 47.
The copper wire 43 is held by the clamp 45 while leaving it protruding by a desired length. Next, the capillary 47 and the clamp 45 are both raised L to separate the copper wire 43 and the fixed copper pole 51, and the second pound is completed. As a result, only the copper pole 51 is bonded and remains in the wiring layer (FIG. 1(E)).
次に第1図CF)に示すようにキャピラリ47から突出
するワイヤ43の先端部にトーチロッド55を近接させ
、放電によって銅ワイヤ43の先端部に新たな銅ポール
51を形成する。この後、トーチロット55は銅ポール
51を次の電極形成位置で加圧接触及びrI11定する
作業の支障とならない位置に戻す。Next, as shown in FIG. 1CF), a torch rod 55 is brought close to the tip of the wire 43 protruding from the capillary 47, and a new copper pole 51 is formed at the tip of the copper wire 43 by electric discharge. Thereafter, the torch rod 55 returns the copper pole 51 to a position where it does not interfere with the pressure contact and rI11 determination work at the next electrode forming position.
ヒ述した一連の作業を繰り返し行うことによってフリッ
プチップ53の全ての突起状電極形成位置に銅ポール5
1を設け、以って突起状電極を形成することが出来る。By repeating the above-described series of operations, all the protruding electrode formation positions of the flip chip 53 are covered with copper poles 5.
1 can be provided to form a protruding electrode.
第2図は、この実施例によって形成した突起状電極を示
した断面図である。尚、第1図及び第3図に示した構成
成分と同一の構成成分については同・の符号を付して示
しその詳細な説明は省略する。FIG. 2 is a sectional view showing a protruding electrode formed according to this example. Components that are the same as those shown in FIGS. 1 and 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.
同図において、57は配線層13に形成された突起状電
極を示す、この突起状電極57は銅ポール51を金属層
59で被覆して成る。金属層59の被覆は銅ボール51
を配線層13に固定した後に電気めっき処理によって行
うのが良い、電気めっきによればフリップチップ53)
−の電極形成部分以外の部分を損傷することなく容易に
電極形成部分のみに金属層59を被覆することが出来る
。突起状電極57の構成は例えば、金属層57を゛ト田
(Pb−Sn)のみの中層、或は銅ポール51hに順次
にニッケル(Ni)層、金(Au )層、半田(Pb
−3n )層を設けて成る多層金属層を設けた構成とし
ても良いし、又、金属層57を設けずに銅ポール51の
みから成る構成とすることも出来る。これら構成は、フ
リップチップ53の実装時における突起状電極の電気的
接続状Jlに応じて好適な構成を選択すれば良い。In the figure, reference numeral 57 indicates a protruding electrode formed on the wiring layer 13. The protruding electrode 57 is formed by covering the copper pole 51 with a metal layer 59. The metal layer 59 is covered with a copper ball 51
It is preferable to perform an electroplating process after fixing the flip chip to the wiring layer 13 (according to electroplating, flip chip 53)
It is possible to easily cover only the electrode forming portion with the metal layer 59 without damaging the portion other than the electrode forming portion. The structure of the protruding electrode 57 can be, for example, a metal layer 57 that is a middle layer made of only solder (Pb-Sn), or a copper pole 51h that has a nickel (Ni) layer, a gold (Au) layer, a solder (Pb) layer, and a nickel (Ni) layer, a gold (Au) layer, and a solder (Pb
-3n) layer may be provided, or a structure may be provided in which only the copper pole 51 is provided without providing the metal layer 57. A suitable configuration may be selected from these configurations depending on the electrical connection Jl of the protruding electrodes when the flip chip 53 is mounted.
又、突起状゛−[極55を設けた配線層13は配線層の
・構成例を掲げたものであって、配線層の構成はこれに
限定されるものではない。Further, the wiring layer 13 provided with the protruding poles 55 is an example of the configuration of the wiring layer, and the configuration of the wiring layer is not limited to this.
この実施例によれば金属マスクの穴に銅ポールを入れる
工程がなくなり、突起状電極形成の作業性及び作業効率
の向丘を期待出来る。According to this embodiment, the step of inserting the copper pole into the hole of the metal mask is eliminated, and improvements in workability and efficiency in forming protruding electrodes can be expected.
又、この実施例によれば銅ポール51を電極形成位置へ
設けるための位置合せは従来のように金属マスクを用い
るのではなくワイヤホンディング技術を適用出来る。従
って1つのフリップチップ53につき、全ての電極形成
位置をワイヤボンディング装置に一度設定すればフリッ
プチップ53毎に位置合せを行わずに済み、以後間・構
成のフリップチップ53については困難な位置合せ作業
を伴うことなく容易に効率良く位置合せが達成出来る。Further, according to this embodiment, the wire bonding technique can be used for positioning the copper pole 51 at the electrode forming position instead of using a metal mask as in the conventional case. Therefore, once all the electrode formation positions for one flip chip 53 are set in the wire bonding device, there is no need to perform alignment for each flip chip 53, and from then on, difficult alignment work is required for flip chips 53 of different configurations. Alignment can be easily and efficiently achieved without any complication.
従って突起状電極の形成が従来よりも容易に効率良く行
える。Therefore, the protruding electrode can be formed more easily and efficiently than before.
又、この実施例によればフリップチップ53の配線層1
3に銅ポール51を固定する。徒ってフリップチップ5
3の交換時にフリップチップ53に設けた全ての銅ポー
ル51をフリップチップ53と共に取り除くことが出来
るので、交換作業が従来のように煩雑とならず、簡単に
行える。Further, according to this embodiment, the wiring layer 1 of the flip chip 53
A copper pole 51 is fixed to 3. Flip chip 5
Since all the copper poles 51 provided on the flip chip 53 can be removed together with the flip chip 53 when replacing the flip chip 53, the replacement work is not complicated and can be easily performed.
ヒ述した実施例ではファーストポンドを空打ちしセカン
ドポンドで銅ポールをポンディングしたがファーストポ
ンドで銅ポールをポンディングしセカンドポンドで空打
ちを行うようにしても良い。In the embodiment described above, the first pound is used to pound the copper pole, and the second pound is used to pound the copper pole. However, the first pound may be used to pound the copper pole, and the second pound may be used to pound the copper pole.
また、辷述した実施例ではこの発明の実施にE述のワイ
ヤボンディング装置を適用し銅ポールをポンディングす
る工程及び空打ちを行う工程の2[程で1つの銅ポール
をポンディングしていたが、空打ちをせずに1F程で銅
ポールをポンディングするような装置を用いることも出
来る。In addition, in the embodiment described above, the wire bonding apparatus described in E was applied to carry out the present invention, and one copper pole was bonded in step 2 of the step of bonding the copper pole and the step of performing blank bonding. However, it is also possible to use a device that pounds the copper pole at about 1F without dry firing.
(発明の効果)
と述した説明から明らかなように、この発明の突起状電
極の形成方法によれば、突起状電極の形成に当り粒状金
属体を金属マスクの穴に入れる困難な作業を含まず、加
圧接触と固定という簡単な工程の組合せによって電極形
成を行うので作業性及び作業効率の向丘を期待出来る。(Effects of the Invention) As is clear from the above description, according to the method for forming a protruding electrode of the present invention, forming a protruding electrode involves the difficult work of inserting a granular metal body into a hole in a metal mask. First, since electrode formation is performed by a combination of simple steps of pressurized contact and fixing, improvements in workability and work efficiency can be expected.
又、粒状金属体の電極形成位置への位置合せは、ICチ
ップにワイヤをポンディングするためのワイヤボンディ
ング技術を適用出来、従って位置合せを従来より簡単に
かつ効率良く行える。その結果、電極形成の作業性及び
作業効率の向丘を図れる。Further, the wire bonding technique for bonding wires to the IC chip can be applied to align the granular metal bodies to the electrode formation positions, and therefore the alignment can be performed more easily and efficiently than before. As a result, the workability and efficiency of electrode formation can be improved.
さらに、粒状金1一体は突起状電極を形成すべき配線層
に固定されるので、半導体チップの交換作業が煩雑とな
らず簡単に行える。Further, since the granular gold 1 is fixed to the wiring layer in which the protruding electrodes are to be formed, the replacement work of the semiconductor chip is not complicated and can be easily performed.
【図面の簡単な説明】
7JS1図はこの発明の・実施例の■程説明図、7Jt
IZ図は実施例において形成された突起状電極を示した
断面図、
第3図は従来の突起状電極の形成方法の説明に供する断
面図である。
l3・・・配線層、 51・・・粒状金属体5
3・・・下地、 57・・・突起状電極。
特許出願人 沖電気丁業株式会社
代理人 弁理上 大 垣 孝
/J 配Nc/qI
f7八見5I/9
f(/ 酸化I!¥(ハ0.アシへ−シランR聡)2
f、2J、2f 金属層
57°欠B扶電徐
57 金属A
笑□ラテ七七、lI列によると礎、14日ζ、訳1モ)
′オ伽の吋市国第2図
ハ へ
シー
手続補正書
昭和62年1月20日
許庁長官 黒1)引速 殿
件の表示 昭和61年特許願04841、発明の名称
突起状電極の形成方法
正をする者
件との関係 特許出願人
所(〒−105)
東京都港区虎ノ門1丁目7番12号
称(029)沖電気工業株式会社
代表者 橋本 南海男
埋入 〒170 廿(988)5583所 東京都
豊島区東池袋1丁目20番地5正の対象
副書の発明の詳細な説明の欄及び図面
正の内容 別紙の通り
(1)、明細書の第2頁第8〜9行、第3頁第5行及び
第8〜9行、第4頁第5行、第7頁第18行、第8頁第
19行及び第20行、第9頁第11行、第11頁第1行
及び第13〜14行、第12頁第2〜3行、第14行、
第16行及び第17〜18行、第13頁第2行、第3〜
4行、第4行及び第5行の「フリップチップ」を「半導
体チップ1と訂正する。
(2)、同、第7頁第18〜20行の「フリップチップ
以外の・・・・・・・・・配線基板その他」を「半導体
チップ以外の配線基板その他Jと訂正する。
(3)、同、第8頁第14行の「銅ポール31」を「銅
ポール51jと訂正する。
(4)0回、第12頁第1行の「金属層57」をr金属
層59Jと訂正し、同頁第5行の「突起状電極55」を
「突起状電極51jと訂正する。
(5)0図面の第1図(A)を、添付した訂正図の通り
訂正する。
第1図[Brief explanation of the drawings] Figure 7JS1 is an explanatory diagram of the embodiment of this invention, 7Jt
The IZ diagram is a cross-sectional view showing a protruding electrode formed in the example, and FIG. 3 is a cross-sectional view illustrating a conventional method for forming a protruding electrode. l3... Wiring layer, 51... Granular metal body 5
3... Base, 57... Protruding electrode. Patent Applicant: Oki Denki Chogyo Co., Ltd. Agent Takashi Ogaki/J Sei Nc/qI f7 Yami 5 I/9 f (/ Oxidation I! ¥ (Ha0. Ashihe - Silane R Satoshi) 2
f, 2J, 2f Metal layer 57° missing B Fudensu 57 Metal A lol □ Latte 77, according to II column, foundation, 14th ζ, translation 1 mo)
``Oga no Ishikuni Figure 2 C Hessy procedural amendment January 20, 1988 Director General of the License Agency Black 1) Retraction speed Indication of property 1985 patent application 04841, name of invention Formation of protruding electrodes Relationship with the person who corrects the method Patent applicant's office (〒-105) 1-7-12 Toranomon, Minato-ku, Tokyo (029) Oki Electric Industry Co., Ltd. Representative Nankai Hashimoto 〒170 廿 (988) 5583, 1-20-5 Higashiikebukuro, Toshima-ku, Tokyo Contents of detailed description of the invention and drawings in the subject subscript As attached (1), page 2 of the specification, lines 8-9, Page 3, line 5 and lines 8-9, page 4, line 5, page 7, line 18, page 8, lines 19 and 20, page 9, line 11, page 11, line 1 and lines 13-14, page 12, lines 2-3, line 14,
Lines 16 and 17-18, page 13, line 2, 3-
Correct "flip chip" in lines 4, 4 and 5 to "semiconductor chip 1." (2), same page 7, lines 18-20, "other than flip chip... . . . "Wiring boards and others" is corrected to "Wiring boards and others other than semiconductor chips J." (3), "Copper pole 31" on page 8, line 14 of the same page is corrected to "Copper pole 51j." (4 ) 0 times, "metal layer 57" in the first line of page 12 is corrected as r metal layer 59J, and "protruding electrode 55" in the fifth line of the same page is corrected as "protruding electrode 51j." (5) Figure 1 (A) of drawing 0 is corrected as shown in the attached correction diagram.
Claims (3)
るに当り、 該配線層に対し粒状金属体を加圧接触させる工程と、 該粒状金属体を前記配線層に固定する工程とを含む ことを特徴とする突起状電極の形成方法。(1) When forming a protruding electrode on a wiring layer formed on a base, a step of bringing a granular metal body into pressure contact with the wiring layer, and a step of fixing the granular metal body to the wiring layer. A method for forming a protruding electrode, the method comprising:
行うことを特徴とする特許請求の範囲第1項記載の突起
状電極の形成方法。(2) The method for forming a protruding electrode according to claim 1, wherein the pressure contact is performed using a wire bonding technique.
特許請求の範囲第1項記載の突起状電極の形成方法。(3) The method for forming a protruding electrode according to claim 1, wherein the fixing is performed using ultrasonic waves.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61048413A JPS62206857A (en) | 1986-03-07 | 1986-03-07 | Forming method for projection-shaped electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61048413A JPS62206857A (en) | 1986-03-07 | 1986-03-07 | Forming method for projection-shaped electrode |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62206857A true JPS62206857A (en) | 1987-09-11 |
Family
ID=12802618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61048413A Pending JPS62206857A (en) | 1986-03-07 | 1986-03-07 | Forming method for projection-shaped electrode |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62206857A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0228935A (en) * | 1988-07-19 | 1990-01-31 | Omron Tateisi Electron Co | Method for forming junction metal particle for mounting |
US5003373A (en) * | 1987-11-30 | 1991-03-26 | Mitsubishi Denki Kabushiki Kaisha | Structure of electrode junction for semiconductor device |
US5124277A (en) * | 1990-01-10 | 1992-06-23 | Mitsubishi Denki Kabushiki Kaisha | Method of ball bonding to non-wire bonded electrodes of semiconductor devices |
JP2006520103A (en) * | 2003-03-10 | 2006-08-31 | フェアチャイルド・セミコンダクター・コーポレーション | Flip chip coated metal stud bumps made of coated wire |
JP2014157884A (en) * | 2013-02-14 | 2014-08-28 | Olympus Corp | Semiconductor substrate, semiconductor device, image pickup element and image pickup device |
-
1986
- 1986-03-07 JP JP61048413A patent/JPS62206857A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5003373A (en) * | 1987-11-30 | 1991-03-26 | Mitsubishi Denki Kabushiki Kaisha | Structure of electrode junction for semiconductor device |
JPH0228935A (en) * | 1988-07-19 | 1990-01-31 | Omron Tateisi Electron Co | Method for forming junction metal particle for mounting |
US5124277A (en) * | 1990-01-10 | 1992-06-23 | Mitsubishi Denki Kabushiki Kaisha | Method of ball bonding to non-wire bonded electrodes of semiconductor devices |
JP2006520103A (en) * | 2003-03-10 | 2006-08-31 | フェアチャイルド・セミコンダクター・コーポレーション | Flip chip coated metal stud bumps made of coated wire |
US7932171B2 (en) | 2003-03-10 | 2011-04-26 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
JP2014157884A (en) * | 2013-02-14 | 2014-08-28 | Olympus Corp | Semiconductor substrate, semiconductor device, image pickup element and image pickup device |
CN105074893A (en) * | 2013-02-14 | 2015-11-18 | 奥林巴斯株式会社 | Semiconductor substrate, semiconductor deviceimage pickup device, and imaging device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0244666B1 (en) | Balltape structure for tape automated bonding, multilayer packaging and universal chip interconnection | |
US6653170B1 (en) | Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit | |
US5873512A (en) | Application of low temperature metallurgical paste to form a bond structure to attach an electronic component to a carrier | |
EP1386356B1 (en) | Fluxless flip chip interconnection | |
KR960006967B1 (en) | Method for bonding lead with electrode of electronic device | |
US5128746A (en) | Adhesive and encapsulant material with fluxing properties | |
US20030042621A1 (en) | Wire stitch bond on an integrated circuit bond pad and method of making the same | |
US6378758B1 (en) | Conductive leads with non-wettable surfaces | |
US5877079A (en) | Method for manufacturing a semiconductor device and a method for mounting a semiconductor device for eliminating a void | |
US20100309641A1 (en) | Interposer substrate, lsi chip and information terminal device using the interposer substrate, manufacturing method of interposer substrate, and manufacturing method of lsi chip | |
US8046911B2 (en) | Method for mounting electronic component on substrate and method for forming solder surface | |
US6889428B2 (en) | Method of manufacturing sheet material and method of manufacturing circuit device using the same | |
JPS62206857A (en) | Forming method for projection-shaped electrode | |
JP3442615B2 (en) | Substrate heating method | |
US3765590A (en) | Structure for simultaneously attaching a plurality of semiconductor dice to their respective package leads | |
US20050072834A1 (en) | Connection site coating method and solder joints | |
JP3887993B2 (en) | Connection method between IC chip and circuit board | |
JPH0350736A (en) | Manufacture of bump of semiconductor chip | |
JPH0737890A (en) | Method and apparatus for bonding solder ball | |
JPH05175408A (en) | Material and method for mounting semiconductor element | |
JP2000340594A (en) | Transfer bump sheet and manufacture thereof | |
WO2009145196A1 (en) | Semiconductor chip, intermediate substrate and semiconductor device | |
JPH03184353A (en) | Film carrier with bump and manufacture thereof | |
Oppermann et al. | Reliability investigations of hard core solder bumps using mechanical palladium bumps and SnPb solder | |
JPH04127547A (en) | Lsi mounting structure |