JPS62206855A - Wiring structure of semiconductor device - Google Patents

Wiring structure of semiconductor device

Info

Publication number
JPS62206855A
JPS62206855A JP4972986A JP4972986A JPS62206855A JP S62206855 A JPS62206855 A JP S62206855A JP 4972986 A JP4972986 A JP 4972986A JP 4972986 A JP4972986 A JP 4972986A JP S62206855 A JPS62206855 A JP S62206855A
Authority
JP
Japan
Prior art keywords
wiring
correction
semiconductor device
pattern
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4972986A
Other languages
Japanese (ja)
Inventor
Tomoyuki Fujita
藤田 友之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4972986A priority Critical patent/JPS62206855A/en
Publication of JPS62206855A publication Critical patent/JPS62206855A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To correct a wiring path for a semiconductor device manufactured once partially and easily, and to improve productivity by previously forming a wiring pattern row for correction to the uppermost layer section of a semiconductor substrate. CONSTITUTION:A wiring pattern 1 for correction is arranged to the uppermost layer section of a semiconductor substrate 5, and shaped to a section upper than the layer of an existing wiring 2 cut by laser beams or the like. An insulating film (SiO2) 3 is also cut off simultaneously together with the existing wiring 2 by the cutting operation of the existing wiring 2. A spot 6 for connection of laser-beams is directed between the cut existing wiring 2 and the adjacent wiring pattern 1 for correction to connect the wiring 2 and the wiring pattern 1. The spot 6 for connection can connect a fixed pattern for wiring in an uppermost layer gradually in the same manner. A wiring path 7 corrected by such operation is acquired.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の配線構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a wiring structure of a semiconductor device.

〔従来技術とその問題点〕[Prior art and its problems]

基板上に製造した半導体装置は、配線経路上に生じる信
号伝播時間の遅延やパターンの欠陥などにより、不良動
作を起こすことがある。これらの特性上の理由及び製造
技術1の理由などにより欠陥をもった半導体装置は、配
線経路を部分的に修正することにより救済できる場合が
多い。
Semiconductor devices manufactured on a substrate may malfunction due to delays in signal propagation time or pattern defects that occur on wiring paths. Semiconductor devices that are defective due to these characteristics and manufacturing technique 1 can often be repaired by partially correcting the wiring route.

従来、半導体装置の配線経路を修正するには、修正した
い経路をレーザ・ビームなどを用いて切断した後に、そ
の切断点に新しい経路を接続し、結線を行なわなければ
ならない、この結線は、修正すべき半導体装置上に導電
性の高い金属をプラズマ化した状態を形成し、目的の個
所にレーザ・ビームを照射して、プラズマ中の金属を半
導体装置の表面に付着させる方法により、スポット状の
導伝体を形成することができる。したかて、一方の切断
点からスポットを少しずつ動かしなから導伝体を形成し
、他方に至る経路を形成することができる。しかし、こ
のような従来の方法では、レーザ・ビームのスポットの
数に比例して経路の描画に時間がかかること、及びプラ
ズマ状になっている金属を半導体装置の表面に付着させ
て結線に用いているためパターンの信頼性が低いことな
どにより、半導体装置の配線経路を修正することが困難
であるという欠点がある。
Conventionally, in order to modify the wiring route of a semiconductor device, it was necessary to cut the route to be modified using a laser beam, etc., and then connect a new route to the cut point to make the connection. By forming a highly conductive metal into plasma on the semiconductor device to be processed, and then irradiating the target area with a laser beam, the metal in the plasma adheres to the surface of the semiconductor device. A conductor can be formed. Thus, by nudging the spot from one cutting point, a conductor can be formed to form a path to the other. However, with such conventional methods, it takes time to draw the path in proportion to the number of laser beam spots, and metal in the form of plasma is attached to the surface of the semiconductor device and used for wiring. This has the disadvantage that it is difficult to modify the wiring route of a semiconductor device due to low reliability of the pattern.

本発明の目的は、一度製造した半導体装置の配線経路の
部分的な修正を容易にすることにより、不良動作が生じ
た場合の救済を行ない、半導体装置の生産性を向上させ
ることにある。
SUMMARY OF THE INVENTION An object of the present invention is to improve the productivity of semiconductor devices by facilitating partial correction of wiring routes in a semiconductor device once manufactured, thereby providing relief in the event of a defective operation.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の配線構造は、基板上の層間に交互
に形成された配線層と絶縁膜及び近接する配線層を接続
するために絶縁膜の一部分を開口して形成されたコンタ
クト・ホールとからなり、前記層間の最上層である配線
層にあらかじめ形成した修正用配線パターン列を備えて
いる。
The wiring structure of the semiconductor device of the present invention includes contact holes formed by opening a part of the insulating film to connect the wiring layers and the insulating film alternately formed between layers on the substrate and the adjacent wiring layers. The correction wiring pattern array is formed in advance on the wiring layer which is the uppermost layer between the layers.

半導体装置を基板上にはじめて作成する際には、最上層
を配線に使用せずに実現する。今日の半導体装置の設計
・製造技術では、ここで実現した半導体装置は、配線経
路が長さに応じて遅延時間が大きくなったり、あるいは
パターンの欠陥が生じたりして、動作不良を生じる場合
がよくある。
When a semiconductor device is first created on a substrate, it is realized without using the top layer for wiring. With today's semiconductor device design and manufacturing technology, the semiconductor devices realized here may have malfunctions due to increased delay time depending on the length of the wiring path or pattern defects. It happens often.

そこで、以下の方法により、この不良動作を救済する。Therefore, the following method is used to remedy this defective operation.

まず、不良部分を含んでいる個所を切断する。つぎに、
その切断点から最上層にある最も近い配線パターンを、
導電性の高い金属プラズマ中にスボ・ソト状のレーデ−
・ビームを照射する等の方法を用いて接続する。続いて
、最上層にて上記修正用の配線パターン同志を接続して
、もう一方の切断点に至る結線を実現する。
First, cut out the part that contains the defective part. next,
The closest wiring pattern on the top layer from that cutting point,
Subo-soto-like radar in highly conductive metal plasma
・Connect using methods such as beam irradiation. Subsequently, the above-mentioned wiring patterns for correction are connected to each other on the uppermost layer to realize a connection that reaches the other cutting point.

この一連の操作において、既配線を切断した後に必要な
スポット状のレーザ・ビームの量は、経路全体に対して
ではなく、修正用の固定パターン間を接続する部分だけ
である、したがって、スボ・ソトの数が少なくなるため
修正を高速に行なうことができ、なおかつ修正された経
路はレーザ・ビームによって形成されるパターンが少な
くなるため信頼性の高い修正を行なうことができる。
In this series of operations, the amount of spot laser beam required after cutting the existing wiring is not for the entire path, but only for the connection between fixed patterns for correction. Corrections can be made faster because there are fewer paths, and the corrections can be made more reliably because the corrected path has fewer patterns formed by the laser beam.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)ないしくd>は本発明の一実施例の配線切
断から修正までの状況を示す平面図、第2図(a)及び
(b)は第1図(a)のA−A線での配線切断前及び配
線切断後の断面図、第2図(c)は第1図((1)のB
−B@での断面図である。
1(a) to d> are plan views showing the situation from wiring cutting to repair in one embodiment of the present invention, and FIGS. 2(a) and 2(b) are A-A in FIG. 1(a). Cross-sectional views before and after cutting the wiring at line A, Figure 2 (c) is the same as Figure 1 (B in (1)
It is a sectional view at -B@.

本実施例は修正用配線パターン1、既配線2、絶縁11
13、絶縁酸化膜4及び半導体基板5を有する。第1図
及び第2図に示すように、半導体基板5の最上層部に修
正用配線パターン1を配列し、レーザビームなどによっ
て切断される既配線2の層より上部に設ける。
This embodiment includes a wiring pattern for modification 1, an existing wiring pattern 2, and an insulation pattern 11.
13, an insulating oxide film 4 and a semiconductor substrate 5. As shown in FIGS. 1 and 2, wiring patterns 1 for correction are arranged on the uppermost layer of a semiconductor substrate 5 and are provided above the layer of existing wiring 2 to be cut by a laser beam or the like.

既配線2の切断操作は、第1図(a)の切断6面A−A
を例にとると、対応する断面図である第2図(a)に示
された状態がら、既配線2とともに絶縁膜(Si02)
3も同時に切除され、第2図(b)に示される状態とな
る。つづいて第1図(b)に示すように、切断された既
配線2と近接する修正用配線パターン1との間にレーザ
・ビームの結線用スポット6を当てて接続を行なう9こ
の結線用スポット6は、同様にして最上層にある配線用
の固定パターンを接続していくことができる。この配線
パターン同志を接続する結線用スボ・ソト6の平面図を
第1図(e)に示す、この時点で図中B−Bに対応する
断面図は第2図(り)に示される9以上の操作により第
1図(d)に示すような修正された配線経路7が得られ
る。第1図のパターン範囲の修正に、従来の方法では1
5f11の結線用スポットが必要であったが、本実施例
では3個の結線用スポットで接続が行なえるつ 〔発明の効果〕 以上説明したように本発明は、半導体基板の最上層部に
修正用配線パターン列をあらかじめ形成することにより
、半導体装置の経路パターン修正に必要なレーザ・ビー
ムの結線用スポットの数を少なくすることができ、従っ
て、経路修正の高速化を実現できる効果がある。さらに
、あらがしめ用意されている配線パターンは、下部に位
置する配線層と同じ製造技術を用いることが可能であり
、修正されたパターンの信頼性を向上させることができ
る。また、遅延時間の大きな配線に対しては、修正用配
線パターンを用いて迂回経路を設けることにより、配線
抵抗を減少させ、遅延時間を小さくすることができる。
The cutting operation for the existing wiring 2 is carried out on the 6th cutting surface A-A in Fig. 1(a).
For example, in the state shown in FIG. 2(a), which is a corresponding cross-sectional view, the insulating film (Si02) is
3 is also excised at the same time, resulting in the state shown in FIG. 2(b). Next, as shown in FIG. 1(b), a laser beam connection spot 6 is applied between the cut existing wiring 2 and the adjacent correction wiring pattern 1 to make a connection.This wiring spot 9 6, fixed patterns for wiring in the uppermost layer can be connected in the same manner. A plan view of the connection slot 6 that connects the wiring patterns is shown in FIG. Through the above operations, a modified wiring route 7 as shown in FIG. 1(d) is obtained. The conventional method for correcting the pattern range shown in Figure 1 is
5F11 wiring spots were required, but in this embodiment, connections can be made with 3 wiring spots. [Effects of the Invention] As explained above, the present invention provides a method for making connections on the top layer of a semiconductor substrate. By forming the wiring pattern array in advance, it is possible to reduce the number of laser beam connection spots necessary for correcting the path pattern of a semiconductor device, and therefore, there is an effect that speeding up the path correction can be realized. Furthermore, it is possible to use the same manufacturing technology as the underlying wiring layer for the wiring pattern that has been prepared in a rough manner, and the reliability of the corrected pattern can be improved. Further, for wiring with a large delay time, by providing a detour route using a correction wiring pattern, the wiring resistance can be reduced and the delay time can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)ないしくd)は本発明の一実施例の配線切
断から修正までの状況を示す平面図、第2図(a)及び
(b)は第1図(a)のA−A線での配線切断前及び配
線切断後の断面図、第2図(c)は第1図(d)のB−
B線での断面図である。 1・・・修正用配線パターン、2・・・既配線、3・・
・絶縁膜、4・・・絶縁酸化膜、5・・・半導体基板、
6・・・結CG)
FIGS. 1(a) to d) are plan views showing the situation from wiring cutting to repair in one embodiment of the present invention, and FIGS. 2(a) and (b) are A--A in FIG. 1(a). Cross-sectional views before and after cutting the wiring at line A, FIG. 2(c) is B- in FIG. 1(d)
It is a sectional view taken along the B line. 1... Wiring pattern for correction, 2... Existing wiring, 3...
- Insulating film, 4... Insulating oxide film, 5... Semiconductor substrate,
6...Yui CG)

Claims (1)

【特許請求の範囲】[Claims]  基板上の層間に交互に形成された配線層と絶縁膜及び
近接する配線層を接続するために絶縁膜の一部分を開口
して形成されたコンタクト・ホールとからなる半導体装
置の配線構造において、前記層間の最上層である配線層
にあらかじめ形成した修正用配線パターン列を備えるこ
とを特徴とする半導体装置の配線構造。
In the wiring structure of a semiconductor device comprising wiring layers alternately formed between layers on a substrate, an insulating film, and a contact hole formed by opening a part of the insulating film to connect adjacent wiring layers, 1. A wiring structure for a semiconductor device, comprising a correction wiring pattern array formed in advance on a wiring layer that is the uppermost layer between layers.
JP4972986A 1986-03-06 1986-03-06 Wiring structure of semiconductor device Pending JPS62206855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4972986A JPS62206855A (en) 1986-03-06 1986-03-06 Wiring structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4972986A JPS62206855A (en) 1986-03-06 1986-03-06 Wiring structure of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62206855A true JPS62206855A (en) 1987-09-11

Family

ID=12839274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4972986A Pending JPS62206855A (en) 1986-03-06 1986-03-06 Wiring structure of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62206855A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63183481A (en) * 1987-01-27 1988-07-28 三菱電機株式会社 Circuit board and repairs thereof
EP0409256A2 (en) * 1989-07-21 1991-01-23 Kabushiki Kaisha Toshiba Semiconductor IC device and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63183481A (en) * 1987-01-27 1988-07-28 三菱電機株式会社 Circuit board and repairs thereof
EP0409256A2 (en) * 1989-07-21 1991-01-23 Kabushiki Kaisha Toshiba Semiconductor IC device and method for manufacturing the same
JPH0353547A (en) * 1989-07-21 1991-03-07 Toshiba Corp Semiconductor integrated circuit device and manufacture thereof
US5160995A (en) * 1989-07-21 1992-11-03 Kabushiki Kaisha Toshiba Semiconductor IC device with dummy wires

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