JPS62205455A - One chip cache memory - Google Patents

Abstract

PURPOSE:To connect plural cache memories in parallel and to execute the writing to a main memory without disturbance by providing a writing buffer register in a cache memory chip and outputting 1 to a writing buffer busy terminal during the writing. CONSTITUTION:When a writing request to a main memory is executed, the command of the memory writing is impressed from a processor P through a processor access terminal PC to a control circuit 13. Then, the circuit 13 investigates a cache chip selecting terminal CS, when this is 0, any action is not executed, when the terminal CS is 1, the circuit investigates a writing buffer busy signal terminal WB, when this is 1, it is awaited that 0 is impressed, and the memory address impressed to a processor address terminal PA is set to an address register 11. The writing data impressed to a processor data terminal PD are set to a writing buffer register 17, and the signal to inform the terminal PC that the access is completed is impressed.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to a one-chip cache and memory that incorporates a directory and data memory in one chip integrated circuit, and particularly relates to a one-chip cache and memory that incorporates a directory and data memory in one chip integrated circuit. The present invention relates to an expandable one-chip cache memory that can realize a large capacity cache memory by connecting cache memories.

(Prior art and its problems) By installing a small-capacity, high-speed buffer memory between the processor and main memory, the effective main memory access time can be sped up. It is generally well known as described in detail in Coaxputlng 5urvey, Vol. 14, No. 3, 1982, pages 473-530.

This method is usually called cache calculation and is widely used in computer systems. This takes advantage of the property that there is locality in memory access of programs executed on a computer system. By fetching the contents of the ninth memory location t (usually called a block) from main memory to cache memory, most memory accesses are done by accessing the fast cache memory, and slow Access to main memory can be reduced.

As will be described in detail later, the cache and memory are composed of address registers, data registers, IJs, data memory, control circuits, etc., but conventionally, these have been constructed by combining integrated circuit chips such as logic gates and meshes. Te*I! It's been L. However, in integrated circuits, high-speed logic operations or memory operations are possible within the chip, but when the signal lines are taken out of the chip, the pivoting of the signal lines outside the chip is difficult. Because it consumes a lot of delay time compared to the case inside the chip,
There is a drawback that it is difficult to increase the processing speed of cache and memory as a whole.

On the other hand, as the degree of integration per chip increases due to advances in integrated circuit technology, the performance of the cache memory can be greatly improved by storing the entire cache memory in one chip. becomes possible. however,
If the cache and memory are implemented using a t-1 chip, it is not necessarily possible to store a sufficient capacity of cache memory in one chip due to the limitation of the degree of integration.

It is necessary to realize a large-capacity cache memory by combining multiple caches and memory chips.

In such a case, if an ethical circuit for cache and memory expansion is provided outside the chip, a large amount of delay time will be required between the cache memory chip and the external logic circuit.
Compared to a one-chip case, the processing speed of searches, updates, etc. will be lower, and the advantages of using a one-chip cache memory as described above will be diminished.

The present invention was made to improve the drawbacks of the conventional methods described above, and an object of the present invention is to combine multiple one-chip cache memories to create a large-capacity cache memory without causing a decrease in processing speed performance. - To provide an expandable one-chip cache memory that can realize memory.

(Means for Solving the Problems) The one-chip cache memory according to the present invention includes a cache, a ninth directory for managing blocks held in the memory, and a data memory for holding block data. , and a write buffer resistor that holds committed data from the CPU to the main memory, and serves as the ninth input/output terminal for communication of memory access requests from the processor to the cache memory.
a first access control signal terminal for a completion signal etc., fo
A first address signal terminal for the memory address from the processor, a first data signal terminal for exchanging data with the processor, and a comparison input for communication of memory access requests from the cache memory to the main memory. A second access control signal terminal, a second address signal terminal, a second data signal terminal as output terminals, and a method for specifying whether or not a memory access request from the processor to the cache memory chip exists. Cache chip 7'J selection terminal, write buffer busy signal terminal indicating that the write buffer register has not completed the commitment to the main memory and data is still held, a value is sent to the cache chip selection terminal. It can operate as a cache memory only when ``r'' is applied, and is further configured to wait for a J write from the processor when the write buffer busy signal terminal is ``]#. .

Since it is configured in this way, a plurality of the one-chip cache mem- bers are used to transmit the memory access request control signal N&, address line, and data line from the processor to all of the one-chip cache memories. the first access control signal terminal of the first address signal terminal, connected to the first data signal terminal of all the one-chip cache memories;
A second address/1st number terminal and a second data signal terminal are connected to the main memory via a memory access request control signal line, an address line, and a data line, respectively, and A cache chip selection signal is exclusively applied from the processor to the cache chip selection terminal, and the write buffer bits of each of the one-chip cache memories are connected to each other, so that when a memory access request is received from the processor, the cache chip selection signal is applied to the cache chip selection terminal. Only the one-chip cache and memory chip designated by the cache chip selection signal operates as a cache and a memory.
In particular, any 1 in response to a memory 4 request from the processor.
As long as memory convolution is not completed from one one-chip cache memory, the next memory four-fold request can be made to wait. This way you can expand your memory with multiple caches,
Moreover, these cache and memories operate without confusion.

(Example) Configuration The present invention will be explained in detail. First, one structure of a cache memory chip in an embodiment of the present invention will be explained with reference to FIG. In this embodiment, the cage and the memory chip have terminals for power supply, ground, clock, etc. (not shown), and terminals for communication with the processor, for notifying requests for access to the memory from the processor and for communicating with the processor. Cache, frossette access terminal PC for notification of completion of access in memory, processor address terminal PA for notification of memory address.

It has a processor data terminal PD for exchanging data, and also has a memory access terminal MC, a memory address terminal MA, and a memory data terminal MD as terminals for communication with the main memory.

In addition, the cache memory chip indicates that there is data in the cache tick selection terminal C8 and the write buffer register of the main memory for specifying the cache memory chip to operate upon a memory access request from the processor. It has a write buffer busy signal terminal WBt.

The processor address terminal PA is connected to the input side of the address register 11, and the output of the block address portion of the address register 11 is applied to the directory 12 and also to the memory address terminal MA.

The output of the intra-block word address portion of the address register 11 is applied together with the word address generated by the control circuit 13 to the data memory 14 as an intra-block word address, and is also applied to the memory address terminal MA. Directory 12 matching address output FBA
is applied to the data memory 14 as a block address, and is also applied to the replacement circuit 15.

The ten address addresses on the data memory 14 to be replaced, generated by the replacement circuit 15, are applied to the directory 12 as write addresses. The match detection signal F from the directory 12 is marked on the control circuit 13.
has been done.

The output side of the read data register 16 and the input side of the write buffer register 17 are connected to the processor data child PD. Read data from the data memory 14 is applied to the read data register 160, and the output of the write buffer register 17 is applied as write data to the data memory 14 via the write data register 1B, as well as to the memory data terminals. has been done. Write data register 18 receives write data from write buffer register 17 or memory data terminal OLD. The cache check 7'' selection terminal C8 is connected to the control circuit 13.The fo'lJ control circuit 13 receives the input from the processor access terminal PC,
It is a sophisticated control circuit that receives memory initialization requests, memory write and read requests, and performs the corresponding processing.
The access request to the main memory generated here has not been applied to the memory access terminal MC.

Operation The operation of the cache memory chip in the embodiment of the present invention will now be described.

When a memory read signal is applied from the read processing processor P to the control circuit 13 via the processor access terminal PC, the control circuit 13 checks the cache chip selection terminal C8, and if it is marked with K[0'# This cage,
No operation is performed in the memory chip fC. If the value "'11 is applied to the cache chip f selection terminal C8, the memory address to which the processor address 1 child PAK is applied is set in the address register 11, and then The value of this block address part is the directory]2
Search for. If this search finds a match, i.e.
If the block containing the address requested for access exists in its own cache memory, the directory 12
Serial placement 1Qjlf by matching ejection address FBA outputted by! 15 and also directory 1
The data memory 14 is read using the block address FBA outputted by the processor 2 and the word address fll in the block of the address register 11 as an address. A signal is applied to indicate that the access has been completed.

If a match is not detected in the directory 12, that is, if the block containing the incorrect address requested for access does not exist in the internal memory, the control circuit 13 performs the following processing for the loaded member of the Glock.

First, the replacement circuit 15 determines 10 blocks on the data memory 14 to be replaced, and sets the value of the block address part of the address register 11 to the corresponding entry in the directory 12. In particular, the output of the 10 address part of the address 9 address register 11 and the control circuit 13
By applying the word address in the Glock generated in the memory address terminal to the memory address terminal and the memo 'JM read request to the memory access terminal Me, the main memory is read, and the read data is immediately written to the memory data terminal. 4F @ is loaded into the data memory 14 via the register 18t.
After doing this for all words belonging to the block, the process of loading the diblock is completed by logging in the directory 12 that this block is valid. Reading from the processor is performed by re-executing the memory offset process.

Write Process When there is a write request to the main memory, the following process is performed in this embodiment. That is, when a memory write command is applied from the access tp to the control circuit 13 via the fa set length access terminal PC, the control circuit 13 checks the 100% selection terminal C8 and finds that the value "O" is applied to it. In this case, this cache memory chip C performs no operation. Chiyashi, when the value "l" is applied to the f selection terminal C8, check whether "1-" is applied to the terminal No.
If "l" is applied and temperature is ℃, wait for "O" to be applied to F4J, set the memory address applied to the address PA to the address register i1, and transfer the memory address to the processor data terminal PD. Set the storage data applied to n into the storage buffer register 17, apply a signal to the processor access terminal PC to notify that the access has been completed, and set the storage buffer pidgy signal #1 to the processor access terminal PC.
', apply #1 and # to the p terminal, and then search the directory 12 directly from 1 of the 10 address section of the address register 11. If a match is detected in the memory, the control circuit 13 of the corresponding memory chip commits from the commit buffer register 17 to the data memory 14 via the write data register 18. At the same time, writing is also performed to the main memory. If a match is not detected in the cache memory, the cache does not perform the famic load to the memory chip, but only performs an oath to the memory. This is done by immediately applying the address set in the address register 11 to the memory access terminal, and immediately applying the write data set in the buffer register 17 to the memory data terminal. This is done by applying a memory 4 load request to ζ. When the storage into the main memory is completed, the storage bag 7 Abino 1 No. 15 in front of the terminal will be set to 101.

Middle Yash Memory System Next, with reference to FIG. The one-f decaching is implemented using memory chips 08-04, and the component of the memory access request to each chip is performed using the special two bits of the memory address in a known manner. I take it as a thing.

For this purpose, the output of the two picts b, ,b, of the memory address from the processor P is applied to the decoder DCD, and each of the four output lines of the decoder DCD is connected to the cache memory f
yp C1t Cx +, Cg + C4 are connected to Nohira Yasshi & Degg selection terminal C8.

Access from processor P*1. The request signal line, address signal line, and data signal line are all connected to the 1,000-yash memory chip C1tC! *c, l C4 are connected to corresponding terminals PC, PA, PD K, and similarly all cache memories fy are connected to c1*'tmC
The memory access terminal MC of B+04, the memory address line, and the memory address line MD are connected to the access request signal line, address signal line, and data signal line, respectively, and the main memory M
Connected to M and °C. The storage buffer nodes WB of all cache memory steps C1*Ct+CstC4 are interconnected.

By using this configuration and arranging the cache memory capacity to be 4 tons, the main memory capacity to be shared by each cache and memory tag is one-fourth that of a single cache memory chip. Therefore, it is possible to increase the probability that the necessary data will be found in the memory.

Although the embodiments of the present invention have been described above, the present invention also requires that the T-tube be held on the same chip! rock'
I&: F has a built-in data memory for holding the tth directory and block data, and serves as an input/output terminal for communication of memory access requests from the processor to the cache memory.
First access +++'II control signal terminal for a friend such as a partner, first address signal terminal for memory address from the processor, first data signal terminal for data exchange with the processor. , the ninth input/output terminal of the iWIM for memory access between the cache memory and the main memory is the second access control signal terminal, the second address signal terminal, the second data signal terminal, and the fourth input/output terminal of the iWIM. , a program for determining whether the memory access from the processor to the memory chip is valid, f
Data selection terminal, all 41 data from fa set to memory
It has a terminal that indicates that it is in the middle, and it can operate as a thousand-yash memory only when the value "l" is stamped on the cache and f-selection terminals. The data transfer from the processor to the memory is done via a terminal K++r o.
4 is set to L5, which can be completed when the voltage is applied.

This dress! Using a plurality of cache memories, the memory access request control signal line, address line, and router from the processor are connected to all the plurality of word/decker caches 111 and the first access ItIj control signal terminal of the memory. , a first address signal terminal, a first data signal terminal, and a second access control signal terminal, an address signal terminal of 42, a second data signal terminal of all the one f-tube cache memories. r terminals are respectively connected to the main memory via a memory access request control signal line, an address line, and a data line, and all of the write buffer busy terminals are interconnected; By exclusively applying a cache & chip selection signal from the processor to the selection shoulder, the cache f is
Only the one-chip cache and memory chip specified in Tsude Selection No. 1- operates as a thousand-year memory, and all one-chip caches are used to transfer data from the processor to the memory in the load. It can be expanded as a cache memory system by completing the process when the memory's honor signal becomes 0-.

It will be obvious that several modifications can be made as long as they do not violate this spirit. For example, in the case of ttub select, in the embodiment described above, the allocation to each cache memory chip is performed using two pits in the memory address field, but it is not necessarily necessary to do this, and in this embodiment, the processor All bits of the memory address of are applied to the cache memory chip, but 1! is applied to the cache memory chip allocation! ! It is not necessarily necessary to apply the two bits of the address used.

Furthermore, in the description of the above-mentioned embodiment, since it is not directly related to the gist of the invention, we will discuss the detailed implementation method and timing of the control circuit 13, such as applying a memory access request and a completion signal to the terminal. Tiger dart control,
A detailed explanation of the application and reception of read and write data to the data terminals will be omitted, but it is obvious that these can be realized using conventionally known techniques6.
-Also, in this embodiment, the directory 12% replacement circuit 15, etc. can be configured in nine configurations depending on the mapping method adopted by the 1000-yash memory. However, in a multiprocessor system consisting of multiple processors, each of which is equipped with a cache memory according to the present invention, a trough-length cache memory and main memory are assumed. Consideration must be given to maintaining consistency of content between the two, but various conventionally known methods can be applied to this as well.

(Effect of the Invention) As described above, according to the present invention, a built-in buffer register is provided in the cache memory chip, and "16" is output to the input terminal during writing. Because of the structure, multiple caches and memories can be connected in parallel and writing to the main memory can be performed without confusion with these memories.
- Since the chip is designed to operate only when 1" is given to the step selection terminal from the processor, it is easy to create an expanded memory system using multiple memory chips. , and high speed is not lost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a ramie memory chip according to the present invention, and FIG. 2 is a block diagram showing a cache memory system using 1,000 ash memory chips according to the invention. 11... Address signal terminal, 12... Directory, 13... Control circuit, 14... Data memory, 15
... Replacement circuit, 16... Read data register, 17... Commitment buffer register, 18
...Write data register, MC...memory access terminal, MA...memory address terminal, MD...memory data terminal, PC...processor access terminal,
PA...Processor address terminal, FD...Processor data terminal, C8...Chip selection terminal, WB
...Write buffer busy terminal, MM ...Main memory,
CI *c, l cse C4"" Cache memory chip, P...Procera? , DCD...decoder. Monkey 1 Figure Ya 20

Claims (1)

[Claims] (1) A directory for managing blocks held in the chip, a data memory for holding block data, and a write buffer register for holding write data from the processor to the main memory are built-in on the same chip, As an input/output terminal for communicating memory access requests from the processor to the cache memory, a first access control signal terminal for memory access requests, completion signals, etc., and a first address for memory addresses from the processor. a signal terminal, a first data signal terminal for exchanging data with the processor; a second access control signal terminal as an input/output terminal for communication of memory access requests from the cache memory to the main memory; a second address signal terminal; a second data signal terminal; a chip selection terminal for specifying whether a memory access request from the processor to the cashier memory chip is valid; and a chip selection terminal for writing to the write buffer register. a write buffer busy terminal in which data is held and a write buffer busy signal indicating that the cache memory is writing data to main memory in response to a memory write request from the processor is output, the cache chip selection terminal; It operates as a cache memory only when the value "1" is applied to the memory, and in the case of a memory write request, it waits for the write buffer busy terminal to become "0" and accepts the write request, at the same time this write buffer A one-chip cache memory that applies "1" to a busy terminal and sets a write buffer busy terminal to "0" when data writing to the main memory is completed.