JPH0266653A - One-chip cache memory - Google Patents

Abstract

PURPOSE: To write the string data at a high speed by providing a coincidence detecting circuit corresponding to a write data block buffer register and an FF and writing data blocks which is temporarily written memories into the buffer register in memory en masse.

CONSTITUTION: In the case the value '1' is applied to a cache chip selection terminal CS, the memory address applied to a processor address terminal PA is set at an address register 11. The write data applied to a processor data terminal PD is set at a write buffer register 17. Then a signal is applied to a processor access terminal PC to inform the end of an access, and a directory 12 and a coincidence detecting circuit 19 are retrieved by the value of the block address part of the register 11. When the coincidence is detected at the directory 12, a control circuit 13 of the corresponding cache memory chip performs a writing job to a data memory 14 from the register 17 via a write data register 18. At the same time, a writing action is also given to a main memory.

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