JPH0266653A - One-chip cache memory - Google Patents

One-chip cache memory

Info

Publication number
JPH0266653A
JPH0266653A JP63218836A JP21883688A JPH0266653A JP H0266653 A JPH0266653 A JP H0266653A JP 63218836 A JP63218836 A JP 63218836A JP 21883688 A JP21883688 A JP 21883688A JP H0266653 A JPH0266653 A JP H0266653A
Authority
JP
Japan
Prior art keywords
register
data
memory
write
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63218836A
Other languages
Japanese (ja)
Inventor
Sadanobu Ikeda
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP63218836A priority Critical patent/JPH0266653A/en
Publication of JPH0266653A publication Critical patent/JPH0266653A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To write the string data at a high speed by providing a coincidence detecting circuit corresponding to a write data block buffer register and an FF and writing data blocks which is temporarily written memories into the buffer register in memory en masse.
CONSTITUTION: In the case the value '1' is applied to a cache chip selection terminal CS, the memory address applied to a processor address terminal PA is set at an address register 11. The write data applied to a processor data terminal PD is set at a write buffer register 17. Then a signal is applied to a processor access terminal PC to inform the end of an access, and a directory 12 and a coincidence detecting circuit 19 are retrieved by the value of the block address part of the register 11. When the coincidence is detected at the directory 12, a control circuit 13 of the corresponding cache memory chip performs a writing job to a data memory 14 from the register 17 via a write data register 18. At the same time, a writing action is also given to a main memory.
COPYRIGHT: (C)1990,JPO&Japio
JP63218836A 1988-09-01 1988-09-01 One-chip cache memory Pending JPH0266653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63218836A JPH0266653A (en) 1988-09-01 1988-09-01 One-chip cache memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63218836A JPH0266653A (en) 1988-09-01 1988-09-01 One-chip cache memory

Publications (1)

Publication Number Publication Date
JPH0266653A true JPH0266653A (en) 1990-03-06

Family

ID=16726103

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63218836A Pending JPH0266653A (en) 1988-09-01 1988-09-01 One-chip cache memory

Country Status (1)

Country Link
JP (1) JPH0266653A (en)

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