JPS62204662A - Data generating circuit for zigzag head - Google Patents

Abstract

PURPOSE:To obtain a simpler zigzag head data generating circuit by using a switch circuit so as to put an inputted serial data into an S/P conversion circuit and an S/P conversion circuit with a delay circuit one by one bit alternately. CONSTITUTION:A serial signal from an input terminal 1 is inputted to the S/P conversion circuit 6 and the S/P conversion circuit 8 with a delay circuit by a switch circuit 5 alternately while being distributed at every bit. An even number order data is inputted directly to the circuit 6 and an odd number order data is inputted to a shift register 9. Thus, the odd number order data inputted at the same time as the existing data in the circuit 6 exists at the first half of the register 9 and the data of the odd number order before one line is given to the latter half of the register 9 and the odd number order data before two lines exists in a shift register 10. Thus, in inputting a strobe signal to an input terminal 2, the even order number data inputted just before is outputted from a drive circuit 7 and the odd number order of data inputted before two lines is outputted from a drive circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data generation circuit for a staggered head that can be used in a recording device that records electrical signals as visible images.

2. Description of the Related Art In recent years, with the spread of office automation, there has been a growing demand for recording devices that convert electrical signals into visible images, so-called printers, and higher quality performance is also required. Among various recording devices, recording devices that conduct electricity through electrode needles, such as discharge breakdown recording devices, electrolytic recording devices, current-carrying thermal recording devices, and current-carrying transfer recording devices, are superior in terms of high speed, record preservation, and economic efficiency. (Hard Copy Technology, published by Japan Technical Center, June 1981). In order to achieve high resolution, it is necessary to make the electrode needles thinner. However, thinning the electrode needles has its limitations due to problems with strength and durability, so by arranging thick electrode needles in a staggered manner, high resolution electrodes It is possible to configure the head. However, in order to print using a staggered head, the data to be printed must also be reconfigured for the staggered head.

If reconfiguration is performed using software, processing time is required and speeding up cannot be achieved. Various methods have been proposed to solve this problem.

Hereinafter, an example of a data generation circuit for a staggered head will be described with reference to the drawings.

5 and 6 are a block diagram and a timing diagram of a conventional data generation circuit for a staggered head. The even data conversion circuit 21 includes a serial-parallel conversion circuit 22 and a three-stage shift register 23, and the output signal of the data conversion circuit 21 is input to a drive circuit 24 connected to the even numbered electrode needles 25. 26 is an input terminal for serially arranged print data to the serial-parallel conversion circuit 22, and 27 is a clock input terminal of the shift register 23. Similarly, the odd data conversion circuit 28 is the serial-parallel conversion circuit 2.
9 and a three-stage shift register 30, the output signal of the data conversion circuit 28 is input to a drive circuit 31 connected to odd-numbered electrode needles 32. 33 is an input terminal for serially arranged print data to the serial-parallel conversion circuit 29, and 34 is a clock input terminal of the shift register 30. As mentioned above, the even number data conversion circuit and the odd number data conversion circuit have exactly the same configuration, and the arrangement of the electrode needles is such that when the even numbered electrode needle is in the m row position, the odd numbered electrode needle is in the m row position.
-It is an array located at the 2nd row position.

Even data input from the data input terminal 26 is converted into parallel data by the serial-parallel conversion circuit 22 and input to the shift register 23 in response to a clock signal. By inputting a clock signal three times for one data input, even-numbered data is output to the drive circuit 24 and printed through the even-numbered electrode needles 25. On the other hand, the odd data similarly converted to parallel data is transferred to the first stage of the shift register 30 by a clock signal input to the clock input terminal 34 at the same time as the third clock signal input to the even data conversion circuit 21. At the same time, the third stage data is outputted and printed through the electrode needle 32. Therefore, even numbered electrode needles 25 are m
When printing the line, the odd-numbered electrode meter 32 prints the m-2th line.

Problems to be Solved by the Invention In such a conventional data generation circuit for a staggered head, a shift register of an even number data conversion circuit is unnecessary, and two types of clock signals must be generated. Furthermore, since parallel signals are input to the shift register, there is a problem in that the number of connections between the serial-parallel conversion circuit and the shift register increases.

The present invention aims to solve these problems and provide a simpler data generation circuit for a staggered head.

Means for Solving the Problems In order to solve the above problems, the present invention comprises a serial-to-parallel conversion circuit, a serial-to-parallel conversion circuit with a delay circuit, and a switch circuit, and input serial data is transmitted through the switch circuit. 1 in the serial-to-parallel conversion circuit and the serial-to-parallel conversion circuit with a delay circuit;
This is a circuit that generates data for a staggered head by distributing bits alternately.

Effect The present invention has the above-mentioned configuration, so that the data for the staggered head can be stored in one piece.
The number of lines to be shifted is determined by the length of the shift register, and the shift register and serial
It is possible to obtain a data generation circuit for a staggered head having a simple configuration in which only one wire is required for connection to the parallel conversion circuit.

Embodiment [Embodiment 1] FIG. 1 is a block diagram showing an embodiment of a data generation circuit for a staggered head according to the present invention. In FIG. 1, 1 is an image signal input terminal, 2 is a strobe signal input terminal, 3 is an even number clock signal input terminal, 4 is an odd number clock signal input terminal, 5 is a switch circuit, 6 is a serial-parallel conversion circuit, 7 is an even number drive circuit, 8 is a serial with delay circuit.
Parallel conversion circuit, 9 is a shift register with a length equivalent to two rows of data, 10 is a serial-parallel conversion circuit, 1) is an odd number drive circuit, 12 is an odd numbered electrode needle, 13 is an even numbered electrode needle Electrode needle, odd numbered electrode needle 1
The distance between the example No. 2 and the example of the even-numbered electrode needles 13 is two lines. FIG. 2 is a timing diagram corresponding to FIG. The serial signal inputted from the image signal input terminal 1 is distributed to a serial-to-parallel converter circuit 6 and a serial-to-parallel converter circuit with a delay circuit 8 alternately one bit at a time by a switch circuit 5. Since even-numbered data is directly input to the serial-parallel conversion circuit 6 and odd-numbered data is input to the shift register 9, the odd-numbered data that is input at the same time as the data currently in the serial-parallel conversion circuit 6 is The shift register 9 has the first half, the second half of the shift register 9 has the odd numbered data of the previous row, and the shift register 10 has the odd numbered data of the two previous rows. Therefore, by inputting a strobe signal to the strobe signal input terminal 2, the even-numbered data that was input immediately before is sent from the drive circuit 7, and the odd-numbered data that was input two lines before is sent from the drive circuit 1). Output.

As described above, by adjusting the shift of the electrode needles due to the staggered arrangement by adjusting the length of the shift register, it becomes possible to perform printing compatible with the staggered head without rearranging data using software.

[Embodiment 2] FIG. 3 is a block diagram showing another embodiment of the data generation circuit for a staggered head according to the present invention. In FIG. 3, 1 is an image signal input terminal, 2 is a strobe signal input terminal, 14 is a bistable circuit for holding data, 15 is a reset signal input terminal of the bistable circuit 14, 16 is a clock signal input terminal, 5 is a switch circuit, 6 is a serial-parallel conversion circuit, 7 is an even number drive circuit, and 8 is a serial circuit with a delay circuit.
Parallel conversion circuit, 9 is a shift register with a length equivalent to two rows of data, 10 is a serial-parallel conversion circuit, 1) is an odd number drive circuit, 12 is an odd numbered electrode needle, 13 is an even numbered electrode needle Electrode needle, odd numbered electrode needle 1
The distance between column No. 2 and the even-numbered column of electrode needles 13 is two rows. FIG. 2 is a timing diagram corresponding to FIG. The serial signal inputted from the image signal input terminal 1 is divided into 1 bit by 7 bits by the switch circuit 5, and is inputted to each bistable circuit and held there. Clock signal input terminal 1
The data held in the bistable circuits are converted into serial-to-parallel converter circuits 6 by the clock signals input to 6.
is input to the shift register 9, and then a reset signal is input to the reset signal input terminal 15 to reset the bistable circuit. The subsequent operation is the same as in the first embodiment.

As mentioned above, a bistable circuit can be connected to a switch circuit and a serial circuit.
By installing it between the parallel conversion circuit 6 and the shift register 9, the number of clock signals can be reduced to one type.

Effects of the Invention As is clear from the above explanation, in order to solve the above problems, the present invention is composed of a serial-to-parallel conversion circuit, a serial-to-parallel conversion circuit with a delay circuit, and a switch circuit. By alternately distributing one bit at a time to the serial-to-parallel conversion circuit and the serial-to-parallel conversion circuit with delay circuit using a switch circuit, data for the staggered head can be created with one delay circuit, and it is possible to create data for the staggered head with one delay circuit. It is possible to obtain a data generation circuit for a staggered head with a simple configuration, which is determined by the length of the shift register, and requires only one connection between the shift register and the serial-parallel conversion circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a timing diagram of one embodiment of the present invention, FIG. 3 is a block diagram of another embodiment of the present invention, and FIG. 4 is a block diagram of another embodiment of the present invention. FIG. 5 is a circuit diagram of a conventional data generation circuit for a staggered head, and FIG. 6 is a timing diagram of a conventional data generation circuit for a staggered head. 5... Switch circuit, 6... Serial-parallel conversion circuit, 7,1)... Drive circuit,
8... Serial-parallel conversion circuit with delay circuit, 9... Shift register, 10... Serial-parallel conversion circuit, 14... Bistable circuit, 21.28...Data conversion circuit, 22, 2
9... Serial-parallel conversion circuit, 23.3
0...3-stage shift register, 24.31...
...Drive circuit. Name of agent: Patent attorney Toshio Nakao 1 person 5-m-switch circuit 6-1 Serial-parallel caress circuit Figure 1 7. II-Motor circuit 8-Tail 1 circuit village serial-parallel variation detection circuit S-switch circuit 1-m-serial-parallel variation detection circuit 7, no/
---One Horse Gai Dango Kaiku 8-1 Kanara Circuit vs. Serial-Parallel 3rd TI! i
Vehicle inspection circuit 1)゜21.28-Temperature IL clamp circuit 22.29-Serial-parallel I/Rj: J road No. 5 Figure 23.30-3-stage shift register 24.31-M first circuit

Claims (3)

[Claims] (1) Consists of a serial-to-parallel conversion circuit, a serial-to-parallel conversion circuit with a delay circuit, and a switch circuit.
A data generation circuit for a staggered head, characterized in that it alternately distributes one bit at a time to a parallel conversion circuit. (2) A data generation circuit for a staggered head according to claim (1), wherein the delay circuit is a shift register. (3) Data generation for a staggered head according to claim (1), characterized in that a bistable circuit is provided between the switch circuit, the serial-to-parallel conversion circuit, and the serial-to-parallel conversion circuit with a delay circuit, respectively. circuit.