JPS6220421A - Reference voltage circuit of differential logic circuit - Google Patents

Abstract

PURPOSE:To evade the change of an output voltage and unstableness of an output by using an average value of the non-inverted output voltage and the inverted output voltage of a differential logic circuit as the gate reference voltage. CONSTITUTION:The differential logic circuit is provided with FETs 1 and 2, and an input signal Vin is supplied to the gate of the FET 1, and the reference voltage is given to the gate of the FET 2. An average voltage value V is given in accordance with V=(V1+V2) where V1 and V2 are the non-inverted output voltage and the inverted output voltage of the differential logic circuit respectively. Voltages V1 and V2 are constant independently of the variance of the supply voltage, and the voltage V is gate biased to stabilize the reference voltage. Thus, the change of the output voltage and unstableness of the output are evaded.

Description

[Detailed description of the invention] 〔overview〕 In logic operation reference voltage generation circuits of integrated circuits.

By generating a reference voltage from the output voltage of a differential logic circuit.

This is intended to create a differential logic circuit having a stable output that is not affected by changes in power supply voltage, ambient salinity, or element parameters.

[Industrial application field]

The present invention relates to improvements in reference voltage supply circuits for differential logic circuits in integrated circuits.

The output level of the differential logic circuit changes when the input voltage value reaches the dark value. Since this dark value is determined by the reference voltage applied to the differential logic circuit, it is desirable to supply a stable reference voltage in order to operate the circuit stably.

[Conventional technology]

Conventionally, differential logic circuits are constructed using integrated circuits.

A reference voltage generated by another external circuit is supplied to each gate of each differential logic circuit.6 Conventional reference voltage supply circuits adjust the output reference voltage depending on fluctuations in power supply voltage and changes in element parameters. As a result, the input voltage value of the differential logic circuit changes, making it impossible to obtain a stable output waveform.

Furthermore, even if the sheet metal reference voltage is held at a constant value, the output voltage level of the differential logic circuit in the integrated circuit may fluctuate due to variations in the characteristics of the two temperature-varying circuit elements, differences in circuit format, etc. There is something to know.

[Problem that the invention seeks to solve]

The present invention addresses changes in the output voltage due to fluctuations in the reference voltage in a differential logic circuit, variations in characteristics of one circuit element due to temperature fluctuations, etc.
The present invention aims to provide a reference voltage supply circuit that avoids output instability.

(Means for solving problems) The above problem is.

This problem is solved by the integrated circuit reference voltage circuit according to the present invention, which uses the average value of the non-inverted output voltage and the inverted output voltage of the differential amplifier circuit as the gate reference voltage.

[Effect]

The non-inverting output voltage of the differential logic circuit is vL, and the inverting output voltage is v
2, the average voltage value V becomes V = (vl + v2) / 2.

The output voltages vl and v2 of the differential logic circuit are constant values irrespective of fluctuations in the power supply voltage, and the reference voltage is stabilized by setting ■ to the gate bias.

Also, when the parameters of the FET elements of the integrated circuit change, the differential logic circuit's 1. Although the amplitude of v2 varies.

If the above average voltage is used as the reference voltage, the dignity ratio of the element characteristic output waveform is always kept constant.

〔Example〕

The invention will now be described in detail according to illustrated embodiments.

FIG. 1 is a circuit diagram showing an embodiment of the integrated circuit reference voltage circuit of the present invention, in which the reference voltage is generated from its own output section in a differential logic circuit.

The differential logic circuit includes FETs 1 and 2, and an input signal V
in is supplied to the gate of JET 1. The reference voltage is F
Given to the gate of ET2.

The logic output voltage vL v2 of the differential logic circuit is equal to 2
averaged by the resistors 3 and 4, v= (vl+ν2)/
2 is applied to the gate of FET 2 as a reference voltage.

(2) is the dark value of the input voltage, and the logical output voltage vL v2 hardly changes even if the power supply voltage changes, so the voltage V becomes a stable reference voltage.

FIG. 2 is a circuit diagram showing another embodiment of the reference voltage supply circuit, in which the reference voltage of the differential logic circuit is generated from the output section of the differential logic circuit in the preceding stage and is supplied to the differential logic circuit 5 in the succeeding stage. Show what you are looking for.

FET 1. The logic output voltage vL v2 of the differential logic circuit equipped with FET 2 is applied to the resistor 23.2 as in the case of FIG.
4 is averaged and supplied to the subsequent differential logic circuit 5 as a reference voltage of v=(vi+v2)/2.

In this case, even if the logic output voltage fluctuates due to variations in the characteristics of the elements and the logic amplitude changes, the reference voltage is set at the midpoint of the output voltages of the two wheels, so the logic operation of the subsequent differential logic circuit becomes stable.

Figure 3 shows the input voltage Vin vs. output voltage Vo of the differential logic circuit.
A characteristic diagram of ut is shown.

In the differential logic circuit, the output voltage is inverted between logic voltage values vl and v2 at a threshold value νref of the input voltage. Vref
is equal to the reference voltage. In the present invention, it is taken at the midpoint between the two output voltages, that is, at the intersection of the curves of change of the two output voltages.

FIG. 4 shows a configuration diagram of the average voltage ordering circuit.

Resistor 3.4 or 23 in Figure 1 or Figure 2
．． 24 as FET 6. It is composed of T.

By configuring the resistance element with a FIET element, the area occupied by the reference voltage generation circuit on the semiconductor chip is reduced, allowing for high-density integration.

FIG. 5 is a block circuit diagram of an embodiment in which differential logic circuits are connected in series.

The output of the front-stage differential logic circuit 8 is sent to the rear-stage differential logic circuit 9.
10. In this case, the output logic voltage value vl of 8,
The average value of v2 is supplied to circuits 9 and 10 as a reference voltage, and even if vl+v2 changes due to parameter fluctuations in one circuit 9 and 10, the output inversion threshold vth is at the midpoint between vl and v2.

〔Effect of the invention〕

As described above, according to the present invention, the power supply voltage.

It is possible to create a reference voltage generation circuit within the device that operates stably without being affected by temperature fluctuations or variations in device characteristics.
Enables high-density construction without the need for external supply wiring,
It provides a high-speed circuit, and its effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a reference voltage circuit diagram of an embodiment of the present invention. FIG. 2 is a reference voltage circuit diagram of another embodiment of the present invention. Figure 3 is an input/output voltage characteristic diagram of a differential logic circuit. FIG. 4 is a diagram of an average voltage generation circuit according to an embodiment of the present invention. FIG. 5 is a cascade connection circuit diagram of a differential logic circuit according to an embodiment of the present invention. In fig. 1.2 and 6.7 are FETs. 3. 4.23.24 is resistance. 5.8.9.10 shows the logic circuit.

Claims (1)

[Claims] A reference voltage circuit for a differential logic circuit, characterized in that a gate reference voltage is an average value of a non-inverting output voltage and an inverting output voltage of the differential logic circuit.