JPS62203525U - - Google Patents
Info
- Publication number
- JPS62203525U JPS62203525U JP1986092614U JP9261486U JPS62203525U JP S62203525 U JPS62203525 U JP S62203525U JP 1986092614 U JP1986092614 U JP 1986092614U JP 9261486 U JP9261486 U JP 9261486U JP S62203525 U JPS62203525 U JP S62203525U
- Authority
- JP
- Japan
- Prior art keywords
- comparator
- delay time
- output
- output voltage
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Description
第１図はこの考案の一実施例による回路のブロ
ツク図、第２図および第３図はその動作を説明す
るための各部の波形図、第４図、第５図はその要
部のブロツク図、第６図は第５図の動作を説明す
るための各部波形図、第７図はこの考案の一実施
例による要部のブロツク図、第８図はその各部の
波形図、第９図は従来の回路を示すブロツク図、
第１０図はその動作を説明するための各部の波形
図である。
図中、１はＲＳフリツプフロツプ回路、１０は
ランプ電圧発生回路、１５，３０は比較器、１９
，２１は微分用コンデンサ、２０，２２は同じく
抵抗器、２５および２６はダイオードである。な
お、各図中同一符号は同一または相当部分を示す
。
Figure 1 is a block diagram of a circuit according to an embodiment of this invention, Figures 2 and 3 are waveform diagrams of various parts to explain its operation, and Figures 4 and 5 are block diagrams of its main parts. , FIG. 6 is a waveform diagram of each part to explain the operation of FIG. 5, FIG. 7 is a block diagram of the main part according to an embodiment of this invention, FIG. A block diagram showing a conventional circuit,
FIG. 10 is a waveform diagram of each part for explaining the operation. In the figure, 1 is an RS flip-flop circuit, 10 is a lamp voltage generation circuit, 15 and 30 are comparators, and 19
, 21 are differential capacitors, 20 and 22 are resistors, and 25 and 26 are diodes. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
とを比較する第１比較器と、この比較器の出力電
圧を微分回路を介して第２比較器に導入するとと
もに、この第２比較器の出力電圧により前記第１
比較器をラツチングすることにより、遅延時間お
よび出力パルス幅を所定値にそれぞれ制御できる
ようにした遅延時間調整回路。 (2) 上記微分回路の出力端と第２比較器の入力
端との間にダイオードによるサプレス回路を挿入
してなる実用新案登録請求の範囲第１項記載の遅
延時間調整回路。[Claims for Utility Model Registration] (1) A first comparator that compares the output voltage of the lamp voltage generation circuit with a reference voltage, and the output voltage of this comparator is introduced into a second comparator via a differentiating circuit. At the same time, the output voltage of the second comparator causes the first
A delay time adjustment circuit that can control the delay time and output pulse width to predetermined values by latching the comparator. (2) The delay time adjustment circuit according to claim 1, which comprises a diode suppressor inserted between the output end of the differentiating circuit and the input end of the second comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986092614U JPS62203525U (en) | 1986-06-18 | 1986-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986092614U JPS62203525U (en) | 1986-06-18 | 1986-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62203525U true JPS62203525U (en) | 1987-12-25 |
Family
ID=30954473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986092614U Pending JPS62203525U (en) | 1986-06-18 | 1986-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62203525U (en) |
-
1986
- 1986-06-18 JP JP1986092614U patent/JPS62203525U/ja active Pending
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