JPS6220341A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent between electrodes from improperly contacting even if a solder depositing is displaced by disposing a plurality of probe testing conductors around a bump wiring terminal, and connecting with probe testing wiring pattern. CONSTITUTION:A plurality of probe testing conductors 6 are disposed around bump wiring terminals 5A, 5B provided on a mother chip 2 which places a semiconductor chip 3, and electrically connected with a probe testing wiring pattern 6A. The conductors 6 and the pattern 6A are, for example, formed of conductors to be readily moistened with solder of Cr/Cu/Au. They are formed of the same mask as the terminals 5A, 5B. Thus, even if the solder depositing is displaced, since a solder 4C is connected at any of the conductors 6 and the pattern 6A, the terminals 5A, 5B are electrically connected effectively by 100%.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device, and in particular to a technique that is effective when applied to a probe test technique in a semiconductor device that employs flip-chip type face-down bonding. .

[Background technology]

A semiconductor device employing flip-chip face-down bonding has a large number of I4 conductor chips mounted on a silicon wiring board (hereinafter referred to as a mother chip) using flip-chip face-down bonding (for example, Publication No. 73564/1983). Therefore, the number of bump electrodes is, for example, 100 to 300.

When the number of bump electrodes increases in this way, it is extremely difficult to perform a probe test to test for poor contact between the bump electrodes and the wiring, disconnection of the wiring, etc.

Therefore, for example, a method can be considered in which solder is deposited across two bump electrodes (solder bridge) and two wirings connected to these two bump electrodes are connected using a probe to confirm continuity. After checking with a probe, the solder is wetted back and separated, and the two bump electrodes are confirmed to be non-conductive to return to the mounted state.

However, when the solder bridge is wetted back, the solder tends to be biased toward one bump and separate, as shown in FIG. For this reason, there is a problem in that the height and appearance of the solder remaining on the bump electrode (b) differs, resulting in poor contact during reflow.

In order to solve the above problem, as shown in FIG.
Probe test wiring (a) is arranged on the wiring board on which the semiconductor chip is mounted, solder (c) is vapor-deposited to short-circuit the predetermined bump wiring terminals (b), and the wafer 1 is further packed. The present applicant has developed a means for opening the short circuit and easily performing a probe test (Japanese Patent Application No. 59-1.42373).

However, in the above method, when short-circuiting (Show 1~) the predetermined bump wiring terminals (B) by vapor depositing the solder (C), as shown in FIG. 9, due to the total pitch accuracy of the metal mask, the solder There was a problem in that the vapor deposition misalignment occurred and the electrical connection between the bump wiring terminals (electrodes) (b) was not 100% reliable, making it impractical.

[Purpose of the invention]

An object of the present invention is to provide a technique that can 100% reliably prevent connection failures between electrodes even if the solder deposition misalignment occurs.

Another object of the present invention is to provide a technique that can make the height and amount of solder remaining on bump wiring terminals substantially uniform when deposited solder is wet-backed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

Outline of typical inventions disclosed in this application is as follows.

That is, in a flip-chip semiconductor device, a plurality of probe test conductors are arranged around bump wiring terminals provided on a wiring board on which a semiconductor chip is mounted,
By connecting these probe conductors 1 to 1 with a probe test wiring pattern, poor contact between the electrodes can be prevented even if solder evaporation misalignment occurs.

Hereinafter, the configuration of the present invention will be explained along with examples.

It should be noted that throughout the explanation of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof will be omitted.

〔Example〕

1 to 6 are diagrams for explaining a semiconductor device according to an embodiment of the present invention. FIG. 1 is a plan view of a state in which solder is deposited on the main parts, and FIG. 1. FIG. 3 is a sectional view taken along section line A-'A in FIG. 1. FIG. 4 (A) and (B) are sectional views taken along section line BB in FIG. A cross-sectional view of the part shown in the figure wet-backed,
FIG. 5 is a schematic overall configuration diagram of a flip-chip semiconductor device, and FIG. 6 is a plan view of essential parts for explaining the operation of this embodiment.

1 to 6, 1 is a package board, 2 is a mother chip with wiring (wiring board), 3 is a semiconductor chip, 4A and 4B are solder bump electrodes, and 4C is solder (Sb/Sn ), 5A, and 5B are bump wiring terminals of wiring provided on the mother chip 2, for example, C
It is made of a conductor that is easily wetted by solder, such as r/Cu/A11. 6 is a probe test conductor;
As shown in FIG. 1, they are arranged at a plurality of locations around each of the bump wiring terminals 5A and 5B provided on the mother chip 2 on which the semiconductor chip 3 is mounted. These probe test conductors 6 are electrically connected by a probe test wiring pattern 6A. The probe test conductor 6 and wiring pattern 6A are made of, for example, Cr/C.
It is made of a conductor that is easily wetted by solder, such as u/Au. These are formed using the same mask as the bump wiring terminals 5A and 45B. 7 is a bonding pad 8A installed on the mother chip 2.

8B is the wiring provided on the mother chip 2, 9 is the lead,
10 is a bonding wire, and 11Δ and jIB are terminals of the measuring device.

As shown in FIG. 5, the flip-chip type semiconductor device of this embodiment has a 1', s-body chip 1 mounted on a mother chip 2 by a flip-chip method, and a bonding pad 7.
and leads 9 are electrically connected to each other by bonding wires 10, and the mother chip 2 includes:
As shown in FIGS. 1 to 4, probe test conductors 6 are arranged at multiple locations around each of the bump wiring terminals 5A and 5B, and these probe test conductors 6
is electrically connected to the Blobutes 1 using a wiring pattern 6A.

Next, probe test 1 in this embodiment will be explained.

First, as shown in FIGS. 1 to 3, 14C of vapor deposition is performed on L of the mother chip 2 using a vapor deposition mask for half a day. This causes a short circuit between the two bump wiring terminals 5A and 5B. In this state, as shown in FIG. 6, a probe test is performed by contacting the terminals 11A and IIB of the measuring device with the bonding pads 7A and 7B of the mother chip 2 to check the continuity of the two wirings 8A and 8B. at the same time.

Furthermore, by performing wet back, solder 4C
becomes round, and as shown in FIGS. 4A and 4B, bump wiring terminals 5A and 5B are physically and electrically separated to form solder bump electrodes 4A and 4B. In this state, connect the terminal 1 of the measuring device to the bonding pads 7A and 7B.
1A and IIB, and two solder bump electrodes 4A
and 4B. When the wet back is performed, the height and amount of the solder bumps remaining on the bump wiring terminals 5A and 5B are uniform due to ``IL'' and the solder bumps are bridged.

In this way, the probe test conductors 6 are arranged at multiple locations around the bump wiring terminals 5A and 513 installed on the mother chip on which the semiconductor chip 3 is mounted, and these probe test conductors 6 are By electrically connecting the 1- conductor 6 to the blow test 1 with the wiring pattern 6A, the half-[
(Even if there is a deviation of one vapor deposition, the solder 4C will be connected somewhere between the probe test conductor 6 and the probe test wiring pattern 6A.

The bump wiring terminals 5A and 5B are electrically connected with 100% certainty.

Further, when web 1-back is performed, the height and amount of solder bumps remaining on the bump wiring terminals 5A and 5B become uniform, so that poor contact that occurs during reflow can be prevented.

Further, the probe test 1- can be easily performed and the work efficiency can be improved.

Further, by selecting a combination of solder bump electrodes to be connected using the probe test conductor 6 and the probe test I/wiring pattern 6A, the number of tests can be reduced.

-8~ Moreover, as shown in FIG. 7, the configuration can be simplified by devising the shapes and combinations of the probe test conductor 6 and the probe test wiring pattern 6A.

Note that since the wiring terminals 5A, 5B, the probe test conductor 6, and the probe test wiring pattern 6A can be formed of the same metal, the number of manufacturing steps is not increased.

〔effect〕

As explained above, according to the novel technical means disclosed in this application, it is possible to obtain the hair effects described in the first section.

(1) In a flip-chip semiconductor device, probe test conductors are arranged at multiple locations around the wiring terminals provided on the mother chip on which the semiconductor chip is mounted, and these probe test conductors are Connect electrically with the wiring pattern for probe testing.

By creating a structure in which predetermined bump wiring terminals are short-circuited by solder deposition, and the short-circuit can be opened by backing up the web 1, even if misalignment of solder deposition occurs, the solder can be used to connect probe test conductors and Since the connection is made somewhere in the wiring pattern for the probe dess L-, the bump wiring terminals (electrodes) can be reliably electrically connected.

(2) According to (1) above, when wet backing is performed, the height and amount of solder bumps remaining on the bump wiring terminals can be made uniform, so poor contact that occurs during reflow can be prevented.

(3) According to (1) above, even if the device has a large number of bump electrodes, a probe test can be easily performed.

(4) By selecting a combination of solder bump electrodes to be connected using the probe test conductor and probe test wiring pattern of (1) above, the number of tests can be reduced.

(5) By devising the probe test conductor and probe test wiring pattern described in (1) above, the test detection rate can be further improved.

(6) According to (1) to (5) above, the probe test can be performed accurately and the work efficiency can be improved.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.

For example, it goes without saying that the arrangement of the probe test conductors, the shape of the wiring pattern, and the connection combinations of the solder bump electrodes can be variously selected as necessary.

In the embodiments described above, the mother chip was used as a wiring board, but it goes without saying that the present invention can be applied to other boards as well.

[Brief explanation of drawings]

1 to 5 are diagrams for explaining a semiconductor device according to an embodiment of the present invention. FIG. 1 is a plan view of a state in which solder is deposited on the main parts, and FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 2. FIG. 5 is a schematic overall configuration diagram of a flip-chip semiconductor device. , FIG. 6 is a plan view of essential parts for explaining the operation of this embodiment, FIG. 7 is a plan view showing the structure of another embodiment of the probe test conductor and wiring pattern of the present invention, and FIG. Figure to 1st
FIG. 0 is a diagram for explaining problems in the semiconductor device probe test according to the present invention. In the figure, 1...Package board, 2...Mother chip, 3...Semiconductor chip, 4, 4A, 4B...Solder bump electrode, 4C...Solder, 5A, 5B...Bump wiring Terminal, 6... Conductor for probe test, wiring pattern for probe test, 7... Bonding pad, 8A
, 8B... Wiring, 9... Lead, 10... Bonding wire, 11... Terminal of the measuring device.

Claims (1)

[Claims] 1. In a flip-chip semiconductor device, a plurality of probe test conductors are arranged around bump wiring terminals provided on a wiring board on which a semiconductor chip is mounted, and these probe test conductors are provided. A semiconductor device characterized in that conductors are connected by a wiring pattern. 2. The semiconductor device according to claim 1, wherein a semiconductor wiring board is used as the wiring board. 3. The probe test conductor and wiring pattern are structured so that predetermined bump wiring terminals are short-circuited by solder deposition, and further wet-back is performed to open the short circuits, thereby reducing the number of tests. A semiconductor device according to claim 1 or 2 characterized by: 4. The structure of claim 1 is characterized in that the number of tests can be reduced by selecting bump wiring terminals to be short-circuited using the wiring provided on the substrate. 2. The semiconductor device according to item 2.