JPS62202625A - Frame synchronization decision circuit - Google Patents

Abstract

PURPOSE:To prevent missing of data by providing a clock control circuit controlling number of read clocks so as to make two periods coincident when missing or duplication of transmission data is caused in a frame synchronization decision circuit. CONSTITUTION:If a slip takes place, number of clocks fed to a counter 3 is controlled at a clock control circuit 4 by using a write slip (W-Slip) signal or a read slip (R-Slip) signal sent from a bit buffer circuit (BB circuit) 1 and a narrow clock T-CK to make the counter period coincident with the frame period thereby holding the frame synchronization. Since an out of synchronism signal from a collation circuit 2 is not sent to a synchronizing circuit, the event of data missing until the resynchronization establishment is not caused and only a data causing a slip is in error.

Description

[Detailed Description of the Invention] [Summary] In the frame synchronization determination circuit, when data loss or duplication occurs in the bit buffer circuit, the write slip signal or read slip signal from this circuit is used to add the data to the counter. The clock is increased or decreased so that the count period of the counter matches the frame period of the transfer data, thereby preventing loss of transfer data.

[Industrial application field]

The present invention relates to an improvement in a frame synchronization determination circuit used, for example, in a subscriber-based transmission device.

Generally, data from a terminal device installed on the subscriber side is transmitted to, for example, a telephone office via an interface section and a subscriber line, but since the reference clock on the subscriber side has jitter, It is asynchronous to the clock.

Therefore, the data on the subscriber side is synchronized with the reference clock on the central office side using a bit buffer circuit (hereinafter abbreviated as B8 circuit) included in the interface section, but even if data is missing or duplicated at this time, It is desired to minimize the loss of transferred data.

[Conventional technology]

Figure 4 is a block diagram of the conventional example, and Figure 5 is an explanatory diagram of the operation of Figure 4, where Figure 5 (a) shows normal operation and Figure 5 (b) shows when a slip occurs (data loss). .

Therefore, the operation of FIG. 4 will be explained with reference to FIG. 5. The symbols on the left side of FIG. 5 indicate the waveforms of the portions with the same symbols in FIG.

+1) During normal operation - see Fig. 5(a) 8B circuit 1 contains, for example, data of one frame 8-bit configuration with one frame pulse (F) 1 pin and data pulse (0 to 6) 7 bits, extracted from this data. Write clock (hereinafter −
A read clock asynchronous to -CK (hereinafter R- (abbreviated as J) is input (see Figure 5(a)).
-■, W-CK, R-CK).

Therefore, the input data is written to the flip-flop (hereinafter abbreviated as FF) 11 using -CK and outputs Dl, which is then converted into a narrow clock generated by the T-CK circuit 14 using -CK and R-CK. T-CK is written to FF 12 to output D2, which is further written to R-GK to FF 13 and output D3, for example, an exclusive OR circuit (hereinafter abbreviated as EX-OR circuit). Verification circuit 2 consisting of
(Fig. 5(a)-01, T-CK, D2
．． (See D3).

On the other hand, counter 3 is an octal counter (because the l frame has an 8-pin configuration), and when the count value is 0, the output is sent to the verification circuit 2.
Therefore, the collation circuit 2 constantly collates the count period and the frame period of the transferred data using an EX-OR circuit, and if they match, it is determined that frame synchronization has been achieved (Figure 5). (a)-03, see ■).

In addition, the matching/mismatching of the cycles can be checked, for example, as shown in Fig. 5(a).
As shown in -03 and ■, if the timings of frame F and count value O fail once, the cycles match, and if they do not match, the cycles do not match.

5) When a slip occurs - see Figure 5 (b) Figure 5 (b)
- The input data with jitter as shown in ■ is extracted from this data.
The □ that is output and written to T-CK″rFF 12 is
Data “4” in Dl is “4” before being written to FF12.
5'', so it is missing (Fig. 5 (bl-W-
GK, D 1. T-CK, D2), and FF
The output port 2 of 12 is R-GK written to the FF 13, and the output D3 is applied to the verification circuit 2, but since one bit is missing, one frame period is shorter than in the normal state.

On the other hand, since the counter is operating normally, the counter period remains the same as in Figure 5) - ■, so the two periods do not match, and the verification circuit 2 determines that the synchronization is out of order, and the signal is sent from the terminal OUT to the synchronization circuit (Figure 5). (not shown), and resynchronization is taken here (see FIG. 5(b)-D3.■).

The above state is called a write slip (hereinafter abbreviated as -5lip), and the state where data overlaps is called a read slip (hereinafter abbreviated as R-slip). In the latter case, the frame period becomes longer and two The cycles will be inconsistent. Further, 15 of the 88 circuits are slip detection circuits that send out a -5lip or R-slip signal to the outside when a slip occurs.

[Problem that the invention seeks to solve]

When a slip occurs as explained above, the verification circuit 2
Since the synchronization circuit must resynchronize using the output from the synchronization circuit, there is a problem in that the data until resynchronization is established is lost.

[Means for solving problems]

The above problem is solved by providing a clock control circuit 4 that controls the number of read clocks so that the two periods match when a dropout or duplication of transfer data occurs in the frame synchronization determination circuit, as shown in FIG. This problem is solved by the frame synchronization determination circuit of the present invention.

[Effect]

The present invention combines the W-slip signal or R-slip signal sent from the BB circuit 1 when a slip occurs and the T-C
K is used to control the number of clocks added to the counter '3 by the clock control circuit 4 so that the counter cycle matches the frame cycle and frame synchronization is maintained. As a result, since no out-of-synchronization signal is sent from the verification circuit 2 to the synchronization circuit, data loss does not occur until resynchronization is established, and only the data in which the slip has occurred is erroneous.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the clock control circuit in FIG. 1, FIG. 3 is an explanatory diagram of the operation of FIG. 1, and FIG. In the case of Qip, FIG. 3 (bl is the case of R-slip, but the symbols on the left side show the waveform diagram of the same symbols in FIG. 1).

Note that the same symbols indicate the same objects throughout the figures.

Therefore, the operation shown in FIG. 1 will be explained with reference to FIGS. 2 and 3.

(1) In the case of W-sljp - see Figure 3 (a) First, data with jitter, -CK extracted from this data, and R-CK without jitter are added to the &B circuit 1 (Figure 3). (a)-■, W-CK, R-CK),
FIG. 5 (Similar to bl, when the data is "4", -5lip occurs and this data is lost, the W-slip signal is applied to the clock control circuit 4 (FIG. 3(a)-02
, W-slip).

Since R-CK and T-GK are also added to this circuit, the NAND 41 in Fig. 2 makes it "L" by the width of T-CK, and the AND 43 stops sending the clock only while it is "L". Therefore, as shown in FIG. 3(a)-0, one clock is divided into two and passes through the OR 44 to the counter 3.
added to. Therefore, the output of counter 3 is shown in Figure 3 (a
) - As shown in ■, it advances by two steps, "4" and "5", so
The data applied to the verification circuit 2 and the period of the counter match (see FIG. 3 (al-03, ■)).

(In the case of 2J R-slip - see Figure 3(b) As shown in Figure 3(b)-03, data is read out in duplicate, so the frame period becomes longer, but the R-slip applied from the BB circuit 1 - Since the inverted version of the slip signal (state II) is added to AND 42, one bit of R-C is blocked and the counter period becomes longer, resulting in a match as shown in Figure 3(b)-0. .

Therefore, even if a slip occurs, an out-of-synchronization signal is not sent out from the collation circuit 2, so resynchronization is not performed and no data is lost. Note that the data when a slip occurs is incorrect, but the other data is normal.

〔Effect of the invention〕

As explained in detail above, even if a slip occurs, synchronization does not occur, so there is an advantage that data loss does not occur.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of the clock control circuit in Fig. 1, Fig. 3 is an explanatory diagram of the operation of Fig. 1, and Fig. 4 is a block diagram of a conventional example. , FIG. 5 shows an explanatory diagram of the operation of FIG. 4. In the figure, 1 is a bit buffer circuit, 2 is a collation circuit, 3 is a counter, and 4 is a clock control circuit. ■ FOll 31t5b FO/
2 3W-slip Sen Ca) Cod! Figure's work theory EFI group 3 mouth
:l E(b) LL country's i6 explosives exemption man 5 Figure

Claims (1)

[Scope of Claims] A bit buffer circuit (1) that converts data synchronized with a write clock into data synchronized with a read clock and transfers the same, detects loss or duplication of transferred data, and outputs a signal; It consists of a counter (3) that counts read clocks, and a verification circuit (2) that checks whether the frame period of transfer data output from the bit buffer circuit matches the count period of the counter. In the frame synchronization determination circuit, a clock control circuit (4) is provided to control the number of read clocks to the counter (3) so that the two periods match when transmission data is lost or duplicated. A frame synchronization determination circuit characterized by: