JPS62202597A - Memory board device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a device comprising a plurality of semiconductor memory boards in an electronic computer system, in which the semiconductor memory board On the other hand, the present invention relates to a memory board device that allows additional memory to be added.

(Prior art) In a general electronic computer system, since the processing contents differ depending on each user, it is necessary to configure the system so that the internal memory can be expanded according to the requests of each user.
This conventional internal memory expansion means is configured such that a memory board on which a semiconductor memory is mounted can be attached and expanded separately from the standard circuit board.

<Problems to be Solved by the Invention> As mentioned above, when increasing the internal memory, the mounting is done in units of memory boards, so there is a problem that the mounting structure is complicated. As the number of boards increases, maintenance becomes more complicated.
Furthermore, there are various problems in mounting the driver circuit, such as the need to provide it on multiple boards.

<Purpose of the Invention> The present invention has been made in view of the above-mentioned problems, and it is possible to expand memory by connecting a memory expansion board on which a group of semiconductor memories is mounted to a memory board without increasing the number of memory boards. The object of the present invention is to provide a memory substrate device that can perform the following steps.

<Means for Solving the Problems> In order to achieve the above object, the memory board device of the present invention is a memory board device in which a plurality of semiconductor memory boards in an electronic computer system are unitized. A group of semiconductor memories are standard equipment,
It has a memory expansion area and a memory control circuit, and the expansion area is provided with a pair of connectors to which data bus lines and address bus lines are respectively connected in advance, and a semiconductor memory group for expansion is provided. The gist of the present invention is to provide a memory expansion board which is detachably attached to the expansion area via the connector.

<Function> In the memory board device of the present invention configured as described above, when it is desired to add memory to an electronic computer system, by attaching an extension board equipped with a group of semiconductor memories to the extension area of the memory board via a connector, This connector is electrically connected to a memory board via a data bus line and an address bus line, so that memory capacity can be increased without increasing the number of memory boards.

<Example> Hereinafter, a preferred example of the present invention will be described in detail based on the drawings.

First, the technical background of the present invention will be explained with reference to FIG.
For example, various circuit boards A such as a CPU board, various control boards, and memory boards in an electronic computer system are housed in a chassis unit B in parallel, and each circuit board A is formed in pairs in the chassis unit B. is held by a guide rail (not shown) and is removably inserted,
A connector plug (not shown) provided at the lower end of each is connected to a connector jack (not shown) on the motherboard in chassis unit B for electrical connection. Also, during maintenance, each circuit board A
A bypass board is interposed between each unit so that it can be led out from unit B. In addition, conventionally, when expanding memory, a circuit board for memory expansion is installed as described above, so it is necessary to prepare space and connection configuration for installing a considerable number of expansion boards in unit B. .

The memory board 1 of the present invention, which is housed and attached to such a unit B, has a structure as shown in FIG. That is,
At the lower end, a connector 3 that is electrically connected to the connector jack on the motherboard mentioned above is protruded, and at the lower left, semiconductor memories 4a are arranged in a matrix and soldered directly to the board 1. A semiconductor memory group 4 having a capacity of, for example, 1 Mbyte is provided as standard equipment. Further, there are expansion areas 5a at three locations around this semiconductor memory group 4 for expanding memory.

5b and 5c are respectively provided, and data bus connectors 6a and 6b connected to data bus lines are respectively provided in the expansion areas 5a, 5b and 5c.
, 6c, an address/control bus connector 7a connected to the address bus line and the connection path line, respectively.
7b and 7c are attached by soldering, and the data bus connectors 6a to 6c are tilted at a predetermined angle with respect to the horizontally located address bus and control bus connectors 7a to 7C, and are arranged non-parallel to each other. It is set up. Also, a pair of connectors 6a, 7a, 6b, 7b in each of the expansion areas 5a to 5C.

6c and 7c both have the same arrangement shape.

In addition, the semiconductor memory group 4 and each expansion area 5a to 5
A memory control circuit 8 is provided in which memory control ICs 8a are arranged in an L-shape and attached to the periphery so as to surround the semiconductor memory group 4 and each user. Controls the memory being added.

A semiconductor memory group 10 is provided on the memory expansion board 9 mounted in the expansion areas 5a to 5C. The semiconductor memory group 10 is formed by arranging semiconductor memories 10a identical to the semiconductor memory group 4 in the same shape and soldering them. In addition, each expansion area 53
~5c each pair of connectors 5a, 7a, 6b, 7b, 6
A pair of connectors 1) corresponding to c and 7c. 12 are arranged in the same shape on the component mounting surface, one connector 1) is connected to the data bus of the semiconductor memory group 10, and the other connector 12 is connected to an address bus and a control bus. There is.

Then, if you want to add more memory to memory board 1,
From the state shown in Fig. 1, turn over the expansion board 9 as shown by the dashed-dotted line arrows and connect each connector 1). 12 to the corresponding connectors 6b, 7b, 6c, 7 of the expansion areas 5b, 5c, for example.
c and connect it electrically. As is clear from FIG. 2 showing the state of this installation, each semiconductor memory 10a is housed in the gap formed between the two boards 1 and 9 due to the lengths of the connectors 6b, 7b, 6c, and 7c. This makes it possible to reduce the thickness when adding memory.

That is, as shown in FIG. 4, the gaps between the circuit boards A arranged in tandem in the unit 7+-B are effectively utilized, and the entire device including the unit B can be downsized.

Furthermore, since the data bus connectors 6a to 6c are arranged at an angle with respect to the address/connection bus connectors 7a to 7C and are not parallel to each other, the data bus, address bus, and Misconnection with the control bus can be reliably prevented. Furthermore, each pair of connectors 6a, 7a in each expansion area 5a to 5c,
6b, 7b.

6c and 7c are formed in the same pin arrangement, and each pin signal is also assigned the same, so the expansion board 9 can be connected to any of the expansion areas 5a to 5c, and the expansion board 9 compatibility has been obtained. Furthermore, the semiconductor memory group 4 of the memory board 1 and the semiconductor memory group 10 of the expansion board 9 added to each of the expansion areas 5a to 5C have a structure in which the semiconductor memories 4a and 10a are arranged in the same shape. Therefore, it is also easy to maintain.

Next, in FIG. 3 showing the electrical configuration, the same or equivalent parts as in FIGS. 1 and 2 are given the same reference numerals, and will be described in detail below. CP of electronic computer system
The U circuit 13 performs command processing by outputting various signals according to a given command, and connects the connector 3 of the memory board 1 and each data bus connector 6a to 6 of the memory board 1.
Connecting portions 14a, 14b, 14c between C and the data bus connector 1) of each expansion board 9, address bus/control bus connectors 7a to 7C of the memory board 1, and address bus/control bus connectors 7a to 7C of each expansion board 9. The semiconductor memory group 4 of the memory board 1 and each expansion area 5a surrounded by broken lines are connected to the control bus connector 12 through the connection parts 15a, 15b, and 15c.
-5c are connected to each semiconductor memory group 10 of the expansion board 9, respectively. Each semiconductor memory group 4.10 is connected to a bidirectional data bus Do-31. In order to select each semiconductor memory group 4.10 while being supplied with lower address data ALo"n and a read/write control signal R/W indicating whether to read the contents of the memory or write data to the memory. Selection signals S a to S d are supplied to each semiconductor memory group 4 and 10 from address comparators 16 a to 16 d.

In addition, each semiconductor memory group 4.1 allocated by a switch etc.
0 of the output of the start address setting circuit, and preset constant data Kl indicating the difference between the start address of the semiconductor memory group 10 and the start address of the memory board 1, which are respectively added.

K2. and 3 are added in the adders 18a, 18b, and 18C, respectively, and the upper data A a % A d of the addresses of the semiconductor memory groups 4 and 10 outputted from the adders 18a to 18c are added to the address comparators 16b to 16d.
is supplied to Therefore, each address comparator 16a to 1
6d is upper address data AH from C, PU circuit 13
The semiconductor memory group 10 corresponding to o to 3 is selected. still,
Address comparators 16a to 16d, adders 18a to 18
c and the start address setting circuit 18 are constituted by the memory control circuit 8° shown in FIG. 1).

Now, if an electronic computer accesses the highest semiconductor memory group 10 of the groups shown in FIG.
Read/write control signal R/W indicating whether data is read or written from the circuit 13 and address data AL, AH
is output. Here, address comparators 16a to 16
d compares the output upper address data j614 with the upper data A aw A d of the address of the semiconductor memory group 4.10 determined by the address setting circuit 17 and the adders 18a to 18c. At this time, since the upper address data AH becomes equal to the upper address data Ab of the semiconductor memory group 10 shown at the top, the selection signal sb is output only from the second address comparator 16b.
The semiconductor memory group 10 shown at the top becomes active and can be accessed.

In this way, by allowing memory to be added to the single memory board 1, the memory can be added without increasing the number of memory boards, and the memory control circuit and the like can also be configured simply. Further, by separately arranging the semiconductor memory group 4 serving as a memory section and the control section, the function of the memory board 1 can be easily determined, and maintainability is improved.

<Effects of the Invention> As detailed above, according to the memory board device of the present invention,
Semiconductor memories can be added by connecting an expansion board equipped with a group of semiconductor memories to the expansion area of the memory board via a connector, so the memory capacity can be increased without increasing the number of memory boards, and the connector Because it is connected to the data path line and address bus line, the expanded semiconductor memory can be controlled by sharing the memory control circuit of a single memory board. There is no need to provide a memory control circuit, and the number of circuit boards on which this memory control circuit is provided does not increase. Therefore, since the number of substrates is small, mounting is simplified and maintainability is significantly improved.

[Brief explanation of drawings]

Each drawing shows an embodiment of the memory board device of the present invention, in which Fig. 1 is an exploded front view, Fig. 2 is a cutaway side view, Fig. 3 is a block diagram of electrical components, and Fig. 4 is a perspective view. It is. 1--Memory board 4--Semiconductor memory group 4a, 10a of memory board--Semiconductor memory 5a-5C-Expansion area 5a-5c, 7a-7c-Connector 8-
Memory control circuit 9--Expansion board

Claims (1)

[Claims] (1) In a memory board device in which a plurality of semiconductor memory boards are unitized in a computer system, the semiconductor memory board has a group of standard semiconductor memories, an area for memory expansion, and a memory control circuit. death,
The expansion area is provided with a pair of connectors to which a data bus line and an address bus line are respectively connected in advance, and is also provided with a semiconductor memory group for expansion, and is detachably attached to the expansion area via the connector. 1. A memory board device comprising a board for adding memory.