JPS62201588U

JPS62201588U -

Info

Publication number: JPS62201588U
Application number: JP8860586U
Authority: JP
Priority date: 1986-06-11
Filing date: 1986-06-11
Publication date: 1987-12-22

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例によるカツトオフ
調整回路の回路図、第２図はこの発明の一実施例
によるカツトオフ調整回路に用いられるスイツチ
回路の動作タイミングを示す図、第３図は従来の
カツトオフ回路を示す回路図である。１〜３は色差信号、４は輝度信号、５〜７はト
ランジスタ、８〜１０は抵抗、１１は電源、１２
は電源、１３〜１５は抵抗、１６は第１グリツド
、１７はＣＲＴ、１８はアノード、１９はフライ
バツクトランス、２０は高圧巻線、２１は抵抗、
２２は抵抗、２３はコンデンサ、２４は電源、２
５はスクリーングリツド、２６〜２８はドライブ
ＶＲ、３２〜３４は抵抗、３５〜３７はサンプル
ホールド回路、３９はスイツチ回路、４０は切換
入力。 FIG. 1 is a circuit diagram of a cut-off adjustment circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the operation timing of a switch circuit used in the cut-off adjustment circuit according to an embodiment of the present invention, and FIG. 3 is a diagram of a conventional cut-off adjustment circuit. FIG. 3 is a circuit diagram showing a cut-off circuit. 1 to 3 are color difference signals, 4 is a luminance signal, 5 to 7 are transistors, 8 to 10 are resistors, 11 is a power supply, 12
is a power supply, 13 to 15 are resistors, 16 is a first grid, 17 is a CRT, 18 is an anode, 19 is a flyback transformer, 20 is a high voltage winding, 21 is a resistor,
22 is a resistor, 23 is a capacitor, 24 is a power supply, 2
5 is a screen grid, 26 to 28 are drive VRs, 32 to 34 are resistors, 35 to 37 are sample and hold circuits, 39 is a switch circuit, and 40 is a switching input.

Claims

[Scope of Claim for Utility Model Registration] (1) In a cut-off adjustment circuit that adjusts the cut-off white balance of R, G, and B of a color television, sample-and-hold circuits for each of R, G, and B, and a cold flyback high-voltage winding are provided. a beam current detection unit that detects a beam current based on a potential difference generated by a beam current during a pedestal period provided on the side; a switching circuit that guides the potential difference generated in the beam current detection unit to each of the sample and hold circuits; The output of each sample and hold circuit is R
, G, B, and a negative feedback circuit that automatically sets cutoffs for R, G, and B by providing negative feedback to the respective output circuits of R, G, and B. (2) The above switching circuit is R, G, B for every 3 horizontal synchronizations.
2. The cut-off adjustment circuit according to claim 1, wherein the cut-off adjustment circuit sequentially and alternately guides the potential difference generated in the beam current detection section to the sample hold circuit.