JPH0467886U - - Google Patents
Info
- Publication number
- JPH0467886U JPH0467886U JP11089290U JP11089290U JPH0467886U JP H0467886 U JPH0467886 U JP H0467886U JP 11089290 U JP11089290 U JP 11089290U JP 11089290 U JP11089290 U JP 11089290U JP H0467886 U JPH0467886 U JP H0467886U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- brightness
- voltage
- automatic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Television Receiver Circuits (AREA)
- Processing Of Color Television Signals (AREA)
Description
第１図は本考案の一実施例を示す自動輝度制限
（ＡＢＬ）回路用ペデスタルレベル補正回路のブ
ロツク図、第２図は同第１図を説明するための各
部動作波形図である。
１は直流電圧発生回路、６は自動輝度制限回路
および自動コントラスト制限回路を前記自動輝度
制限電圧ＶＡＢ Ｌで同時に制御するマトリクス
用インタフエース集積回路である。
FIG. 1 is a block diagram of a pedestal level correction circuit for an automatic brightness limit (ABL) circuit showing an embodiment of the present invention, and FIG. 2 is a waveform diagram showing the operation of each part to explain FIG. 1. 1 is a DC voltage generation circuit, and 6 is a matrix interface integrated circuit that simultaneously controls an automatic brightness limiting circuit and an automatic contrast limiting circuit using the automatic brightness limiting voltage VABL.
Claims (1)
限回路および自動輝度制限回路を同一の制御電圧
で同時に制御する輝度信号Ｙおよび色差信号Ｒ−
Ｙ，Ｂ−Ｙを入力してＲ，Ｇ，Ｂ原色信号を出力
するマトリクス用インタフエース集積回路の輝度
信号入力回路に、前記自動輝度制限回路用制御電
圧に追従する直流電圧発生回路と入力輝度信号Ｙ
のペデスタルクランプ期間のみ同直流電圧発生回
路の出力電圧を挿入するスイツチ回路とを接続し
てなる画像のペデスタルレベルの補正を特徴とす
るテレビ受像機。 In the color signal processing circuit, a luminance signal Y and a color difference signal R- are used to simultaneously control an automatic contrast limiting circuit and an automatic brightness limiting circuit with the same control voltage.
A DC voltage generation circuit that follows the control voltage for the automatic brightness limiting circuit and an input brightness are added to the brightness signal input circuit of the matrix interface integrated circuit that inputs Y, B-Y and outputs the R, G, B primary color signals. Signal Y
A television receiver characterized by correction of the pedestal level of an image by connecting a switch circuit that inserts the output voltage of the DC voltage generating circuit only during the pedestal clamp period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11089290U JPH0467886U (en) | 1990-10-23 | 1990-10-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11089290U JPH0467886U (en) | 1990-10-23 | 1990-10-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0467886U true JPH0467886U (en) | 1992-06-16 |
Family
ID=31858295
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11089290U Pending JPH0467886U (en) | 1990-10-23 | 1990-10-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0467886U (en) |
-
1990
- 1990-10-23 JP JP11089290U patent/JPH0467886U/ja active Pending
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