JPS6220050A - Bus supervisory and control system - Google Patents
Bus supervisory and control systemInfo
- Publication number
- JPS6220050A JPS6220050A JP60160681A JP16068185A JPS6220050A JP S6220050 A JPS6220050 A JP S6220050A JP 60160681 A JP60160681 A JP 60160681A JP 16068185 A JP16068185 A JP 16068185A JP S6220050 A JPS6220050 A JP S6220050A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- abnormality
- peripheral
- main processing
- transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Small-Scale Networks (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は主処理装置に単一バスを介して複数の周辺部が
接続されたシステムにおけるバス監視flllJ御方式
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus monitoring control system in a system in which a plurality of peripheral units are connected to a main processing unit via a single bus.
従来、この種の・バス監視制御方式においては、バスに
接続され比濁辺部の障害により、バスが当該周辺部によ
りつかみ切りとなり解放されず同一バスに接続される他
の周辺部との情報転送が不可能で6つ九。Conventionally, in this type of bus monitoring and control system, due to a failure in a peripheral part connected to the bus, the bus becomes locked by the peripheral part, and is not released and information with other peripheral parts connected to the same bus is lost. Transfer is impossible and 6 to 9.
上述し几従来のバス監視制御方式では、バス制御に関す
る周辺部の障害発生時には、全周辺部の制御が不可能と
なりシステムの信頼性の低下を招き、この解決の几めに
はバス金二重化および三重化することが必要となる。As mentioned above, in the conventional bus monitoring and control system, when a failure occurs in a peripheral part related to bus control, it becomes impossible to control all peripheral parts, leading to a decrease in system reliability. It will be necessary to triplex the system.
本発明のバス監視制御方式は主処理装置に一本のバスを
介して接続される複数個の周辺部を備えるシステムにお
いて;前記周辺部との転送を制御するバス制御回路と、
転送異常を検出する転送監視回路と、前記周辺部に対す
るパス切離し指示を行うバス切離し信号発生回路と、主
処理プログラムに異常発生及び異常発生周辺部番号を通
知する異常発生通知回路とを備える前記主処理装置と;
この主処理装置からの切離し指示を受信時、前記バスか
ら自己全切離す制御回路を有する前記周辺部とから構成
されることを特徴とする。The bus monitoring control method of the present invention is applied to a system including a plurality of peripheral units connected to a main processing unit via a single bus; a bus control circuit that controls transfer with the peripheral units;
The main unit includes a transfer monitoring circuit that detects a transfer abnormality, a bus disconnection signal generation circuit that instructs the peripheral section to disconnect the path, and an abnormality occurrence notification circuit that notifies the main processing program of the occurrence of the abnormality and the number of the peripheral section where the abnormality has occurred. a processing device;
and the peripheral section having a control circuit that completely disconnects itself from the bus when receiving a disconnection instruction from the main processing unit.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の構成図であり、主処理装置
10はバス20により複数個の周辺部30八〜3ONと
接続され、各種情報の転送をバス20を介して行なう。FIG. 1 is a block diagram of an embodiment of the present invention, in which a main processing unit 10 is connected to a plurality of peripheral units 308 to 3ON via a bus 20, and various information is transferred via the bus 20.
第2図は第1図における主処理装置の構成を示す図であ
る。主処理装置10は主処理プロセッサ11、主処理メ
モリ12.およびバス制御部13とから構成される。こ
こで、制御部13は周辺部30A〜3ONとバスドライ
バ14およびバスレシーバ15を介して接続され、主処
理メモリ12と上記周辺部との間でのデータ転送を制御
するパス制御回路16と、バス転送動作の異常を監視す
る転送監視回路17と、異常検出時に周辺部に対して切
離し指示を送出する切離し信号発生回路18と、異常発
生時主処理プログラムに異常発生を障害周辺部番号と共
に通知する異常発生通知回路19とから構成される。FIG. 2 is a diagram showing the configuration of the main processing device in FIG. 1. The main processing unit 10 includes a main processing processor 11, a main processing memory 12. and a bus control section 13. Here, the control unit 13 is connected to the peripheral units 30A to 3ON via a bus driver 14 and a bus receiver 15, and includes a path control circuit 16 that controls data transfer between the main processing memory 12 and the peripheral units; A transfer monitoring circuit 17 that monitors abnormalities in the bus transfer operation, a disconnection signal generation circuit 18 that sends a disconnection instruction to the peripheral part when an abnormality is detected, and a main processing program that notifies the main processing program of the occurrence of an abnormality along with the faulty peripheral part number when an abnormality is detected. and an abnormality occurrence notification circuit 19.
第3図は第1図における周辺部30A〜3ONの構成ヲ
示す図でおる。ここでは、代表として1つの周辺部を示
す。周辺部は周辺制御プロセッサ31゜周辺制御メモリ
3スおよびバスインタフェース部33から構成される。FIG. 3 is a diagram showing the configuration of the peripheral parts 30A to 3ON in FIG. 1. Here, one peripheral portion is shown as a representative. The peripheral section is composed of a peripheral control processor 31, a peripheral control memory 3, and a bus interface section 33.
ここで、バスインタフェース部33はバスドライバ34
およびバスレシーバ35t−介して主処理装置10とバ
ス20で接続され、かつデータ転送制御を行うバス転送
制御回路36と切離し制御回路37とから構成される。Here, the bus interface section 33 is a bus driver 34.
It is connected to the main processing unit 10 via the bus 20 via the bus receiver 35t, and includes a bus transfer control circuit 36 and a disconnection control circuit 37 for controlling data transfer.
以下に動作を説明する。主処理装置10のバス制御回路
16はあらかじめ転送指示が主処理プログラムより出さ
れていた周辺部と各メモリ間のデータ転送を制御中、転
送監視回路17により、制御信号線のタイミング異常等
が検出され九場合、切離し信号発生回路18に通知し、
該当周辺部に対しバス20との切離しを指示する。ま之
、この時主処理プログラムに対しては、異常発生通知回
路19によシ割込方式等によシ転送異常発生を通知する
と共に異常発生周辺部番号をも通知する。The operation will be explained below. While the bus control circuit 16 of the main processing unit 10 is controlling the data transfer between the peripheral section and each memory for which a transfer instruction has been issued in advance from the main processing program, the transfer monitoring circuit 17 detects a timing abnormality in the control signal line. If so, notify the disconnection signal generation circuit 18,
The relevant peripheral area is instructed to disconnect from the bus 20. At this time, the main processing program is notified of the occurrence of the transfer abnormality by an interrupt method or the like through the abnormality occurrence notification circuit 19, and is also notified of the peripheral part number where the abnormality has occurred.
一方、切離し信号を受領し九該当周辺部は切離し制御回
路37により、バス転送制御回路36からの自局辺部が
転送中表水を基にバス20へのドライバ34のゲートを
閉じるよう制御を行う。このドライバ34のゲートは上
位装置からの解除指示があるまで閉じ友状態が保持され
、バス20から該幽周辺部は切離なされる。On the other hand, upon receiving the disconnection signal, the corresponding peripheral unit controls the disconnection control circuit 37 to close the gate of the driver 34 to the bus 20 based on the surface water being transferred by the own peripheral unit from the bus transfer control circuit 36. conduct. The gate of the driver 34 is kept closed until a release instruction is received from the host device, and the peripheral portion of the driver 34 is separated from the bus 20.
以上説明したように本発明によれば、バス転送異常を検
出してバスに接続される障害周辺部をバスから切離すこ
とによプ、バスが障害周辺部により持ち切りとなること
を防止でき、システムの信頼性を向上できる。As explained above, according to the present invention, by detecting a bus transfer abnormality and disconnecting the faulty peripheral part connected to the bus from the bus, it is possible to prevent the bus from becoming disconnected due to the faulty peripheral part. , system reliability can be improved.
第1図は本発明の一実施例を示す構成図、第2図は第1
図における主処理装置の構成を示す図。
第3図は第1図における周辺部の構成を示す図である。
10・・・・・・主処理装置、20・・・・・・バス、
30A〜3ON・・・・・・周辺部、11・・・・・・
主処理プロセッサ。
12・・・・・・主処理メモリ、13・旧・・バス制御
部、14・・・・・・バスドライバ、15・旧・・バス
レシーバ、16・・・・・・パス制御回路、17・・・
・・・転送監視回路、18・・・・・・切離し信号発生
回路、19・・・・・・異常発生通知回路、31・・・
・・・周辺制御プロセッサ、32・・・・・・周辺制御
メそり、33・・・・・・バスインタフェース部、34
・・・・・・バスドライバ、35・・・・・・パスレシ
ーバ。
36・・・・・・バス転送制御回路、37・・・・・・
切離し制御回路。FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
The figure which shows the structure of the main processing device in the figure. FIG. 3 is a diagram showing the configuration of the peripheral portion in FIG. 1. 10... Main processing unit, 20... Bus,
30A~3ON...peripheral part, 11...
Main processing processor. 12... Main processing memory, 13... Old bus control unit, 14... Bus driver, 15... Old bus receiver, 16... Path control circuit, 17 ...
...Transfer monitoring circuit, 18...Disconnection signal generation circuit, 19...Abnormal occurrence notification circuit, 31...
... Peripheral control processor, 32 ... Peripheral control processor, 33 ... Bus interface section, 34
... Bus driver, 35 ... Pass receiver. 36...Bus transfer control circuit, 37...
Disconnection control circuit.
Claims (1)
辺部を備えるシステムにおいて;前記周辺部との転送を
制御するバス制御回路と、転送異常を検出する転送監視
回路と、前記周辺部に対するバス切離し指示を行うバス
切離し信号発生回路と、主処理プログラムに異常発生及
び異常発生周辺部番号を通知する異常発生通知回路とを
備える前記主処理装置と;この主処理装置からの切離し
指示を受信時、前記バスから自己を切離す制御回路を有
する前記周辺部とから構成されることを特徴とするバス
監視制御方式。In a system including a plurality of peripheral units connected to a main processing unit via a single bus; a bus control circuit that controls transfer with the peripheral unit, a transfer monitoring circuit that detects a transfer abnormality, and a the main processing unit comprising a bus disconnection signal generation circuit for instructing the main processing unit to disconnect from the bus; and an abnormality occurrence notification circuit for notifying the main processing program of the occurrence of the abnormality and the peripheral unit number where the abnormality has occurred; and the peripheral section having a control circuit that disconnects itself from the bus when receiving the bus.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60160681A JPS6220050A (en) | 1985-07-19 | 1985-07-19 | Bus supervisory and control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60160681A JPS6220050A (en) | 1985-07-19 | 1985-07-19 | Bus supervisory and control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6220050A true JPS6220050A (en) | 1987-01-28 |
Family
ID=15720164
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60160681A Pending JPS6220050A (en) | 1985-07-19 | 1985-07-19 | Bus supervisory and control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6220050A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02236758A (en) * | 1989-03-10 | 1990-09-19 | Nec Corp | Bus protection system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58155433A (en) * | 1982-03-11 | 1983-09-16 | Fujitsu Ltd | Connecting system of separate input/output units |
JPS58176726A (en) * | 1982-04-09 | 1983-10-17 | Toshiba Corp | Detector of bus fault |
JPS59201126A (en) * | 1983-04-28 | 1984-11-14 | Nec Corp | Common bus control system |
-
1985
- 1985-07-19 JP JP60160681A patent/JPS6220050A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58155433A (en) * | 1982-03-11 | 1983-09-16 | Fujitsu Ltd | Connecting system of separate input/output units |
JPS58176726A (en) * | 1982-04-09 | 1983-10-17 | Toshiba Corp | Detector of bus fault |
JPS59201126A (en) * | 1983-04-28 | 1984-11-14 | Nec Corp | Common bus control system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02236758A (en) * | 1989-03-10 | 1990-09-19 | Nec Corp | Bus protection system |
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