JPS6220050A - Bus supervisory and control system - Google Patents

Abstract

PURPOSE:To prevent a bus from being used by a peripheral part of a fault, and to improve the reliability of a system by detecting a bus transfer abnormality, and detaching the peripheral part of the fault, which is connected to a bus, from the bus. CONSTITUTION:A bus controlling circuit 16 of a main processor 10 detaches a peripheral part and a bus 20 by a detaching signal generating circuit 18, when an abnormality is detected by a transfer supervising circuit 17, in the course of transferring a data between the peripheral part to which a transfer instruction has been outputted in advance from a main processing program, and each memory. Simultaneously, by an abnormality generation informing circuit 19, the generation of a transfer abnormality and an abnormality generation peripheral number are informed to the main processing program. The peripheral part which has received a detaching signal closes a gate of a driver 35 by a detachment controlling circuit and it is detached from the bus 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus monitoring control system in a system in which a plurality of peripheral units are connected to a main processing unit via a single bus.

[Conventional technology]

Conventionally, in this type of bus monitoring and control system, due to a failure in a peripheral part connected to the bus, the bus becomes locked by the peripheral part, and is not released and information with other peripheral parts connected to the same bus is lost. Transfer is impossible and 6 to 9.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional bus monitoring and control system, when a failure occurs in a peripheral part related to bus control, it becomes impossible to control all peripheral parts, leading to a decrease in system reliability. It will be necessary to triplex the system.

[Means for solving problems]

The bus monitoring control method of the present invention is applied to a system including a plurality of peripheral units connected to a main processing unit via a single bus; a bus control circuit that controls transfer with the peripheral units;
The main unit includes a transfer monitoring circuit that detects a transfer abnormality, a bus disconnection signal generation circuit that instructs the peripheral section to disconnect the path, and an abnormality occurrence notification circuit that notifies the main processing program of the occurrence of the abnormality and the number of the peripheral section where the abnormality has occurred. a processing device;
and the peripheral section having a control circuit that completely disconnects itself from the bus when receiving a disconnection instruction from the main processing unit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a main processing unit 10 is connected to a plurality of peripheral units 308 to 3ON via a bus 20, and various information is transferred via the bus 20.

FIG. 2 is a diagram showing the configuration of the main processing device in FIG. 1. The main processing unit 10 includes a main processing processor 11, a main processing memory 12. and a bus control section 13. Here, the control unit 13 is connected to the peripheral units 30A to 3ON via a bus driver 14 and a bus receiver 15, and includes a path control circuit 16 that controls data transfer between the main processing memory 12 and the peripheral units; A transfer monitoring circuit 17 that monitors abnormalities in the bus transfer operation, a disconnection signal generation circuit 18 that sends a disconnection instruction to the peripheral part when an abnormality is detected, and a main processing program that notifies the main processing program of the occurrence of an abnormality along with the faulty peripheral part number when an abnormality is detected. and an abnormality occurrence notification circuit 19.

FIG. 3 is a diagram showing the configuration of the peripheral parts 30A to 3ON in FIG. 1. Here, one peripheral portion is shown as a representative. The peripheral section is composed of a peripheral control processor 31, a peripheral control memory 3, and a bus interface section 33.

Here, the bus interface section 33 is a bus driver 34.
It is connected to the main processing unit 10 via the bus 20 via the bus receiver 35t, and includes a bus transfer control circuit 36 and a disconnection control circuit 37 for controlling data transfer.

The operation will be explained below. While the bus control circuit 16 of the main processing unit 10 is controlling the data transfer between the peripheral section and each memory for which a transfer instruction has been issued in advance from the main processing program, the transfer monitoring circuit 17 detects a timing abnormality in the control signal line. If so, notify the disconnection signal generation circuit 18,
The relevant peripheral area is instructed to disconnect from the bus 20. At this time, the main processing program is notified of the occurrence of the transfer abnormality by an interrupt method or the like through the abnormality occurrence notification circuit 19, and is also notified of the peripheral part number where the abnormality has occurred.

On the other hand, upon receiving the disconnection signal, the corresponding peripheral unit controls the disconnection control circuit 37 to close the gate of the driver 34 to the bus 20 based on the surface water being transferred by the own peripheral unit from the bus transfer control circuit 36. conduct. The gate of the driver 34 is kept closed until a release instruction is received from the host device, and the peripheral portion of the driver 34 is separated from the bus 20.

〔Effect of the invention〕

As explained above, according to the present invention, by detecting a bus transfer abnormality and disconnecting the faulty peripheral part connected to the bus from the bus, it is possible to prevent the bus from becoming disconnected due to the faulty peripheral part. , system reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
The figure which shows the structure of the main processing device in the figure. FIG. 3 is a diagram showing the configuration of the peripheral portion in FIG. 1. 10... Main processing unit, 20... Bus,
30A~3ON...peripheral part, 11...
Main processing processor. 12... Main processing memory, 13... Old bus control unit, 14... Bus driver, 15... Old bus receiver, 16... Path control circuit, 17 ...
...Transfer monitoring circuit, 18...Disconnection signal generation circuit, 19...Abnormal occurrence notification circuit, 31...
... Peripheral control processor, 32 ... Peripheral control processor, 33 ... Bus interface section, 34
... Bus driver, 35 ... Pass receiver. 36...Bus transfer control circuit, 37...
Disconnection control circuit.

Claims (1)

[Claims] In a system including a plurality of peripheral units connected to a main processing unit via a single bus; a bus control circuit that controls transfer with the peripheral unit, a transfer monitoring circuit that detects a transfer abnormality, and a the main processing unit comprising a bus disconnection signal generation circuit for instructing the main processing unit to disconnect from the bus; and an abnormality occurrence notification circuit for notifying the main processing program of the occurrence of the abnormality and the peripheral unit number where the abnormality has occurred; and the peripheral section having a control circuit that disconnects itself from the bus when receiving the bus.