JPH0916482A - Device connected to host device - Google Patents

Abstract

PURPOSE: To eliminate useless time required for a reconnection command repeated for the stipulated number of times form a host device generated in the fixed fault processing of a conventional peripheral controller and to accelerate the fixed fault processing. CONSTITUTION: The peripheral controller 200 is provided with a voltage monitoring circuit 206 for monitoring a power supply voltage supplied from a power supply part 5, a voltage abnormality detection circuit 207 for detecting the abnormality of the voltage by output signals from the circuit 206, an interruption circuit 205 for interrupting a processor 203 by the output signals from the circuit 207 and a memory 204 for storing a microprogram to be executed in the processor 203. When a fault is generated in a power supply, the processor 203 performs an interruption processing, controls a host interface control part and reports fault contents to the host device 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device connected to a host device which causes a fixed fault related to the device itself in a system such as a computer.

[0002]

2. Description of the Related Art In a conventional device, such as a peripheral control device, which is connected to a higher-level device by a higher-level interface, the following fault processing is performed when a fault occurs in the peripheral control device. That is, in order to improve the system operability, the command is re-executed when a failure occurs. If the re-execution is successful, the failed peripheral controller is continuously used, and if the re-execution is unsuccessful, the failed peripheral controller is disconnected from the system. If there is a replacement device, the process continues.

Also, in computer systems, there is a hot standby system. This is to prepare another standby system and allow the standby system to continue processing when the system in operation becomes unavailable due to a failure. In Japanese Patent Laid-Open No. 2-77941, the processing is continued in a normal computer system even if the processing capacity is reduced at the time of a failure, and the processing capacity normally performed at the time of a failure is continued in the hot standby system and the processing is continued. There is shown a technique for immediately switching to the standby system without doing this.

The details will be described with reference to FIG.
"1 is a central processing unit (CPU), 2 is an input / output device (I) for controlling a plurality of channel devices (CH) 20a to 20n.
OP), 21 is a microprogram control unit that controls the main control of IOP, and 22 is a register (REG).
The value is set by the service processor (SVP) 3 and the value can be referred to by the micro control unit 21. Further, the SVP 3 includes a control wear control unit that controls the main control of the SVP, and a file device (FD) 31 that stores information such as system configuration information, a microprogram of each device, and logout information at the time of failure. In addition, the SVP3 has a console device (CD) 3 for interfacing with the operator.
3 are connected. This information is information for instructing the failure processing method to the IOP 2, and is set by the system engineer using the CD 33 so that the failure processing is suitable for the system when the system is installed. This information is stored in the FD 31 and loaded into the REG 22 in the IOP 2 each time the power is turned on. The content of this information is as shown in FIG. 14, and consists of the number of bits for the number of channels, each bit corresponds to each channel, and when an unrecoverable fixed (solid) failure occurs in the corresponding channel, It defines the fault handling method that IOP2 should take. The bit being 0 means that
When a fixed failure occurs in the corresponding channel, a blocking process should be performed to stop only the subsequent operation of that channel, and the system uses the remaining channels to continue processing (that is, degenerate operation). It is instructed that processing can be performed. This setting is mainly performed when the system is operated as a single system. In addition, the fact that the bit is 1 indicates that when a fixed fault occurs in the corresponding channel, it is possible to immediately perform a fault process to stop the operation of the entire system. This setting is mainly done when the system is operated as a system with hot standby.

Next, a conventional peripheral control device will be described. FIG.
This will be described with reference to FIG. 1 is a host device (or central processing unit), 200 is a peripheral control device, 201 is a host interface controller that controls the host interface 10 with the host device 1, 6 is a peripheral device, and 202 is a lower interface 60 with the peripheral device 6. The lower interface controller 203 controls the CPU 203, the processor 203 executes the microprogram stored in the memory 204, the power source 5 and the power supply signals 50 and 210 for supplying power from the power source 5 are internal buses.

Next, the operation will be described with reference to FIG.
When the power supply unit 5 of the peripheral control device 200 fails, the supplied power is lost and the upper interface 10 is blocked. The higher-level device 1 recognizes that the higher-level interface 10 has been blocked, and issues a reconnection command to the peripheral control device 200 connected to the higher-level interface 10. However, the peripheral control device 200 cannot respond to the reconnection command, and this command times out. After that, the host device issues a reconnection command for the specified number of times, and the host device 1 recognizes that the peripheral control device 200 has a fixed failure only when all commands time out. The host device 1 blocks the host interface 10 to which the peripheral control device 200 is connected,
If there is an alternative device, the alternative device is used to continue the processing.

As described above, in the conventional peripheral control device, when a power failure occurs, the power supply of the peripheral control device is turned off and the upper interface is immediately blocked. That is, the upper interface was blocked on the peripheral control device side regardless of the state of the upper device. In this method, since the cause of the blockage is not notified to the host device before the host interface is blocked, even if the interface reconnection is unsuccessful due to a power failure, the host device notifies the peripheral controller as usual. The re-connection is repeated the number of times specified by the system, and the host device recognizes the occurrence of the fixed fault only after the re-connection of the specified number of times is unsuccessful. Therefore, in the case of a power failure in which reconnection is unsuccessful, there is a problem that the time for repeated reconnection is wasted. Of course, even in the failure processing method described in Japanese Patent Laid-Open No. 2-77941, reconnection is performed when a fixed failure is determined, and the same problem is present.

[0008]

When a host device recognizes a device connected to the host device by an interface, for example, a fixed failure such as a power failure, a reconnection command is issued a specified number of times, and this command is issued. Only when all have timed out does the fixed fault occur. For this reason, in the conventional device, the time of the reconnection command repeatedly issued a prescribed number of times from the host device when a fixed failure occurs is wasted.

An object of the present invention is to provide a device connected to a host device which eliminates the above waste.

Another object of the present invention is to provide a device connected to a higher-level device which speeds up fixed fault processing.

Another object of the present invention is to provide a device connected to a higher-level device, which enables quick disconnection of a faulty device or switching to a replacement device when a fixed fault occurs.

[0012]

The first device of the present invention comprises:
A device that is connected to a host device through a host interface and that detects an abnormality related to the device itself, and reports the occurrence of a failure to the host device based on the detection of this detection means, and then reports the host interface. And a processing means for processing the blockage.

A second device of the present invention is a device connected to a host device by a host interface, and based on the detection means for detecting an abnormality in the power source supplied to the own device and the detection by this detection means. And a processing unit for reporting the occurrence of a power failure to the host device and, after the report, processing for blocking the host interface.

According to a third device of the present invention, in the second device, the detecting means monitors the power supply voltage supplied to the own device, and a power supply is provided by an output signal from the voltage monitoring means. A power supply failure report means for detecting a power supply failure to the upper device based on the detection of the voltage abnormality detection means, and a power supply failure report means for detecting a voltage abnormality. Interface closing means for closing the upper interface after the completion of the power failure report by the means.

In a fourth device of the present invention, in the second device, the detection means controls and monitors the power supplied to the device, and a power supply state output from the power supply control means. A state transition detecting means for detecting a state transition of a signal; and a power source fault reporting means for reporting the occurrence of a power source fault to the host device by the processing means based on the detection of the state transition detecting means, and the power source fault. Interface closing means for closing the upper interface after the power failure report by the reporting means is completed is provided.

A fifth device of the present invention is a device connected to a host device through a host interface, and has a cooling abnormality detecting means for detecting an abnormality of a device that cools itself and a detection of this cooling abnormality detecting means. Processing means for reporting the occurrence of a cooling failure to the host device based on the above, and for processing the blocking of the host interface after the report.

According to a sixth aspect of the present invention, the processing means in the fifth aspect includes a cooling fault reporting means for reporting the occurrence of a cooling fault to a host device based on the detection of the cooling abnormality detecting means, Interface closing means for closing the upper interface after the cooling failure reporting by the cooling failure reporting means is completed.

A seventh device of the present invention is a device connected to a host device by a host interface, and is used for detecting temperature abnormality detecting means for detecting temperature abnormality in the own device and for detecting this temperature abnormality detecting means. And a processing unit for reporting the occurrence of the temperature abnormality to the host device based on the report and for blocking the host interface after the report.

An eighth apparatus of the present invention is the seventh apparatus, wherein the processing means reports a temperature abnormality occurrence to a higher-level device based on the detection of the temperature abnormality detection means. It is provided with reporting means and interface blocking means for blocking the higher-level interface after the temperature abnormality reporting by the temperature abnormality occurrence reporting means is completed.

A ninth device of the present invention is characterized in that the device is a peripheral control device in the first, second, third, fourth, fifth, sixth, seventh or eighth device. And

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the system applied to the present invention is a peripheral controller 20 which is an embodiment of the present invention.
0, the peripheral control device 200 and the host interface 10
A power supply unit 5 that supplies power to the peripheral device 6, which is connected via the power supply signal line 50, to the peripheral device 6, which is connected to the higher-level device 1 connected through Including.

The peripheral control device 200 according to the first embodiment of the present invention controls an upper interface control unit 201 for controlling the upper interface 10, a lower interface control unit 202 for controlling the lower interface 20, and these interface control units 201 and 202. It includes a memory 204 for storing a microprogram for controlling, and a processor 203 for explaining the microprogram from the memory 204 and controlling at least the interface control units 201 and 202.

One of the characteristics of the peripheral control device 200 according to the first embodiment of the present invention is that the power supply unit 5 is connected to the power supply signal line 5
A voltage monitoring circuit 20 that monitors a change in the power supply voltage supplied via 0 and outputs a signal according to a predetermined deterioration of the voltage.
6, a voltage abnormality detection circuit 20 for detecting the occurrence of an abnormality in the power supply voltage in response to the output signal from the voltage monitoring circuit 206
7, an interrupt circuit 205 for interrupting in response to the output signal from the voltage abnormality detecting circuit 207, and a processor 203 for executing interrupt processing in response to the interrupt signal from the interrupt circuit 205.

Another feature of the peripheral control device 200 according to the first embodiment of the present invention lies in the interrupt processing of the processor 203.

Next, the operation of the first embodiment of the present invention will be described in detail with reference to FIGS.

Referring to FIG. 1, when a failure occurs in the power supply unit 5 of the peripheral control device 200, the voltage monitoring circuit 2
06 monitors the voltage supplied through the power supply signal line 50, and detects a change in the voltage. The output signal from the voltage monitoring circuit 206 causes the voltage abnormality detection circuit 207 to operate the power supply unit 5
To detect the occurrence of abnormalities. The output signal from the voltage abnormality detection circuit 207 is input to the interrupt circuit 205, and the processor 2
Interrupted by 03.

An interrupt process executed by the processor 203, which is another feature of the present invention, will be described with reference to FIG.

Referring to FIG. 2, first, it is investigated whether the cause of the interrupt is a power failure. (Step 101).
Since the interruption is caused by the power failure, the process proceeds to step 102. In step 102, a power failure is reported to the host device 1.

Referring to FIGS. 1 and 2, more specifically, the upper interface controller 201 is controlled to report the occurrence of a power failure to the upper device 1. Next, it is checked whether the power failure report executed in step 102 has ended normally (step 103). After normal termination,
Proceed to next step 104. In step 104, the process of blocking the higher-level interface 10 is executed. This completes the interrupt processing.

The operation of the host device 1 will be described with reference to FIG.

After the peripheral controller 200 blocks the higher-level interface 10, the higher-level device 1 recognizes that the higher-level interface 10 is blocked and determines whether or not there is a fixed fault. Since the host device 1 has received the report of the occurrence of the power failure from the peripheral control device 200, it determines that the power supply to the peripheral control device 200 has failed. The host device 1 determines that the power failure of the peripheral control device 200 is a non-recoverable fixed failure, cancels the issue of the reconnection command, and disconnects the failed peripheral control device 200 from the system.

In the first embodiment of the present invention, the power supply voltage during power failure is monitored by the voltage monitoring circuit 206, and the power supply voltage abnormality is detected by the voltage abnormality detection circuit 207 by the output signal from the voltage monitoring circuit 206. To detect. Based on the output signal of this abnormality detection circuit 207, step 10
In 2, the occurrence of power failure is reported to the host device 1.
Then, in step 104, the process of blocking the upper interface 10 is executed.

In the first embodiment of the present invention, since the contents of the failure are reported to the higher-level device 1, there is an effect that the higher-level device 1 does not need to perform the failure processing of the reconnection command, which is conventionally performed.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 4, the system applied to the present invention is a second embodiment of the peripheral control device 2 according to the present invention.
00, this peripheral control device 200 and host interface 1
Host device 1 and peripheral control device 200 connected via 0
From the service processor of the system via the power supply unit 5 and the power supply control signal line 71 which supply power to the peripheral device 6 and the peripheral control device 200 connected via the power supply signal line 50 to the peripheral device 6 and the peripheral control device 200. Power on /
It includes a power supply control unit 7 that controls the power supply unit according to an off instruction and that monitors the state of the power supply unit 5 in response to the occurrence of a failure in the power supply unit 5.

The peripheral control device 200 according to the second embodiment of the present invention comprises an upper interface control unit 201 for controlling the upper interface 10, a lower interface control unit 202 for controlling the lower interface 20, and these interface control units 201 and 202. It includes a memory 204 for storing a microprogram for controlling, and a processor 203 for explaining the microprogram from the memory 204 and controlling at least the interface control units 201 and 202.

One of the characteristics of the peripheral control device 200 according to the second embodiment of the present invention is that it detects the state transition of the signal indicating the power supply state of the power supply unit 5 output from the power supply control unit 7 and outputs the output signal. A state transition detection circuit 208 to be activated, an interruption circuit 205 for making an interruption in response to an activated state of an output signal from the state transition detection circuit 208, and this interruption circuit 20.
5 includes a processor 203 that executes an interrupt process in response to an interrupt signal from 5.

Another feature of the peripheral control device 200 according to the second embodiment of the present invention is the interrupt processing of the processor 203.

Next, the operation of the second embodiment of the present invention will be described in detail with reference to FIGS.

Referring to FIG. 4, when a failure occurs in the power supply unit 5 of the peripheral control device 200, the power supply control unit 7 monitors the state of the power supply unit 5. State transition detection circuit 208
Detects a change in the state of the power supply unit 5 based on the output signal from the power supply control unit 7 and activates the output signal. The output signal from the state transition detection circuit 208 is interrupted by the processor 203 through the interrupt circuit 205.

The interrupt processing executed by the processor 203, which is another feature of the second embodiment of the present invention, will be described with reference to FIG.

Referring to FIG. 5, first, it is checked whether or not the cause of the interrupt is a power failure (step 10).
1). Since the cause of the interrupt is a power failure, step 1
Go to 02. In step 102, a power failure is reported to the host device 1.

Referring to FIGS. 4 and 5, the upper interface control unit 201 is controlled to report the occurrence of a power failure to the upper apparatus 1. Next, it is checked whether the power failure report executed in step 102 has ended normally (step 103). If it ends normally, next step 1
Go to 04. In step 104, a process of blocking the upper interface 10 is executed. This completes the interrupt processing.

The operation of the host device 1 will be described with reference to FIG. After the peripheral controller 200 blocks the higher-level interface 10, the higher-level device 1 recognizes that the higher-level interface 10 is blocked and determines whether or not there is a fixed fault. Host device 1
Since the peripheral control device 200 has received a report indicating that a power supply failure has occurred, determines that the peripheral control device 200 has a power supply failure. The host device 1 determines that the power failure of the peripheral control device 200 is a non-recoverable fixed failure, cancels the issue of the reconnection command, and disconnects the failed peripheral control device 200 from the system.

In the second embodiment of the present invention, the state transition detection circuit 208 detects a change in the state of the output signal from the power supply control section 7 during the occurrence of a power supply failure. State transition detection circuit 2
Based on the detection signal from 08, the occurrence of a power failure is reported to the host device 1 in step 102. Then, in step 104, the process of blocking the upper interface 10 is executed.

In the second embodiment of the present invention as well, as in the first embodiment, since the contents of the power source failure are reported to the higher-level device 1, the failure of the reconnection command conventionally performed in the higher-level device 1. The effect is that no processing is required.

Next, a third embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 7, the system applied to the present invention is a peripheral controller 2 which is a third embodiment of the present invention.
00, this peripheral control device 200 and host interface 1
Host device 1 and peripheral control device 200 connected via 0
And a peripheral device 6, which is connected via a lower-level interface 60, and a peripheral control device 200, and peripheral control with a power supply unit 5 for supplying power via a power supply signal line 50 and a liquid such as water or a gas such as air. A cooling device 8 for cooling the device 200 is included.

The peripheral control device 200 according to the third embodiment of the present invention includes a higher-level interface control unit 201 for controlling the higher-level interface 10, a lower-level interface control unit 202 for controlling the lower-level interface 20, and these interface control units 201 and 202. Memory 204 for storing microprograms for controlling, this memory 2
It includes a processor 203 which describes the microprogram from 04 and controls at least the interface controls 201 and 202.

One of the characteristics of the peripheral control device 200 according to the third embodiment of the present invention is that the cooling device 8 is operated when a failure occurs.
Cooling abnormality detection circuit 209 that detects an abnormality of the cooling device and outputs a signal in response to an output signal from the cooling abnormality detection circuit, an interrupt circuit 205 that generates an interrupt in response to a signal from the cooling abnormality detection circuit 209, and this interruption. It includes a processor 203 that performs an interrupt process in response to an interrupt signal from an interrupt circuit 205.

Another feature of the peripheral controller 200 according to the third embodiment of the present invention lies in the interrupt processing of the processor 203.

Next, the operation of the third embodiment of the present invention will be described in detail with reference to FIGS.

Referring to FIG. 7, when a failure occurs in the cooling device 8 of the peripheral control device 200, the cooling abnormality detection circuit 209 detects the abnormality of the cooling device 8. An output signal from the cooling abnormality detection circuit 209 is interrupted by the processor 203 through the interrupt circuit 205.

The interrupt processing executed by the processor 203, which is another feature of the third embodiment of the present invention, will be described with reference to FIG.

Referring to FIG. 8, first, it is checked whether or not the cause of the interrupt is a cooling failure (step 10).
5). Since the cause of interruption is a cooling failure, step 1
Proceed to 06. In step 106, the cooling failure is reported to the host device 1.

Referring to FIGS. 8 and 9, the host interface controller 201 is controlled to report the occurrence of a cooling failure to the host device 1. Next, it is checked whether or not the cooling fault report executed in step 106 has ended normally (step 103). If it ends normally, next step 1
Go to 04. In step 104, a process of blocking the upper interface 10 is executed. This completes the interrupt processing.

The operation of the host device 1 will be described with reference to FIG.

After the peripheral controller 200 blocks the higher-level interface 10, the higher-level device 1 recognizes that the higher-level interface 10 is blocked and determines whether or not there is a fixed fault. Since the host device 1 has received the report of the occurrence of the cooling fault from the peripheral control device 200, it determines that the peripheral control device 200 has a cooling fault. The upper level device 1 determines that the cooling failure of the peripheral control device 200 is an unrecoverable fixed failure, cancels the issue of the reconnection command, and disconnects the failed peripheral control device 200 from the system.

In the third embodiment of the present invention, a cooling abnormality detecting circuit 20 for detecting an abnormality of the cooling device 8 during the occurrence of a cooling fault.
An abnormality is detected by 9. On the basis of the detection signal from the cooling abnormality detection circuit 209, the occurrence of a cooling failure is reported to the host device 1 in step 106. Then, in step 104, the process of blocking the upper interface 10 is executed.

In the third embodiment of the present invention, the contents of the cooling failure are reported to the high-level equipment 1, so that the high-level equipment 1 does not have to carry out the failure processing of the reconnection command conventionally. Bring

Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 10, the system applied to the present invention is a peripheral control device 200 according to the fourth embodiment of the present invention, and a host device connected to the peripheral control device 200 via the host interface 10. 1, peripheral control device 20
0 and the peripheral device 6, which is connected via the lower interface 60, to the peripheral control device 200 via the power supply signal line 50, and the temperature sensor 9 for detecting the temperature in the peripheral control device 200. Including.

The peripheral control device 200 according to the first embodiment of the present invention controls an upper interface control unit 201 for controlling the upper interface 10, a lower interface control unit 202 for controlling the lower interface 20, and controls these interface control units 201 and 202. Memory 204 for storing a micro program for
It includes a processor 203 which describes the microprogram from 04 and controls at least the interface controls 201 and 202.

One of the characteristics of the peripheral control device 200 according to the fourth embodiment of the present invention is that an abnormal temperature in the peripheral control device 200 is detected in response to an output signal from the temperature sensor 9 due to a failure. In response to the signal from this temperature abnormality detection circuit 211, and in response to the interrupt signal from this interrupt circuit 205. It includes a processor 203 that performs an interrupt process.

Another feature of the peripheral controller 200 according to the fourth embodiment of the present invention lies in the interrupt processing of the processor 203.

Next, the operation of the fourth embodiment of the present invention will be described with reference to FIGS.

Referring to FIG. 10, the peripheral controller 200
When a failure of the device 200 occurs in the temperature sensor 9 of 1, the temperature abnormality detection circuit 211 detects a temperature abnormality in the device 200. The output signal from the temperature abnormality detection circuit 211 is interrupted by the processor 203 through the interrupt circuit 205.

The interrupt processing executed by the processor 203, which is another feature of the present invention, will be described with reference to FIG.

Referring to FIG. 11, first, it is checked whether or not the cause of the interruption is abnormal temperature (step 107). Since the cause of the interruption is abnormal temperature, the process proceeds to step 108. In step 108, a temperature abnormality is reported to the host device 1.

Referring to FIGS. 10 and 11, the upper interface control unit 201 is controlled to report the occurrence of a cooling failure to the upper apparatus 1. Next, step 10
It is checked whether or not the temperature abnormality report executed in step 8 has ended normally (step 103). When the process ends normally, the process proceeds to the next step 104. In step 104, a process of blocking the upper interface 10 is executed. This completes the interrupt processing.

The operation of the host device 1 will be described with reference to FIG.

After the peripheral controller 200 blocks the higher-level interface 10, the higher-level device 1 recognizes that the higher-level interface 10 is blocked and determines whether or not there is a fixed fault. Since the host device 1 receives the report of the occurrence of the temperature abnormality from the peripheral control device 200, it determines that the temperature error of the peripheral control device 200. The host device 1 determines that the temperature abnormality of the peripheral control device 200 is a non-recoverable fixed fault, cancels the issue of the reconnection command, and disconnects the faulty peripheral control device 200 from the system. It is obvious that the present invention is applicable not only to the peripheral control device but also to the peripheral device.

In the fourth embodiment of the present invention, while the temperature abnormality is occurring, the temperature abnormality detection circuit 211 detects the temperature abnormality in the apparatus. Based on the detection signal of the temperature abnormality detection circuit 211, the occurrence of the temperature abnormality is reported to the host device 1 in step 108. Then, in step 104, the process of blocking the upper interface 10 is executed.

In the fourth embodiment of the present invention, since the contents of the cooling failure are reported to the host system 1, it is not necessary to carry out the failure processing of the reconnection command which is conventionally carried out in the host system 1. Bring

[0076]

One of the features of the present invention is that when a peripheral control unit has a fixed fault such as a power source fault, the peripheral control unit can detect the contents of the fault occurring before the peripheral control unit blocks the upper interface. To notify the device. Due to this feature, the present invention eliminates the processing related to the reconnection command that the host device has performed. Therefore, according to the present invention, when a fixed failure occurs in the peripheral control device, the time for the reconnection command repeatedly issued by the host device for the specified number of times can be omitted.

As a result, according to the present invention, when a fixed fault occurs, the faulty device can be disconnected and switched to the alternative device quickly. Therefore, the present invention can realize speeding up of fault processing of fixed faults.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of the present invention and its periphery.

FIG. 2 is a diagram for explaining an interrupt process executed by a processor 203 shown in FIG.

FIG. 3 is a diagram for explaining the operational relationship between the first embodiment of the present invention and the host device 1.

FIG. 4 is a diagram showing a configuration of a second embodiment of the present invention and its periphery.

5 is a diagram for explaining an interrupt process executed by a processor 203 shown in FIG.

FIG. 6 is a diagram for explaining the operational relationship between the second embodiment of the present invention and the host device 1.

FIG. 7 is a diagram showing a configuration of a third embodiment of the present invention and its periphery.

8 is a diagram for explaining an interrupt process executed by the processor 203 shown in FIG.

FIG. 9 is a diagram for explaining the operational relationship between the third embodiment of the present invention and the host device 1.

FIG. 10 is a diagram showing a configuration of a fourth embodiment of the present invention and its periphery.

11 is a diagram for explaining an interrupt process executed by the processor 203 shown in FIG.

FIG. 12 is a diagram for explaining the operational relationship between the fourth embodiment of the present invention and the host device 1.

FIG. 13 is a diagram for explaining an example of a conventional technique.

FIG. 14 is a diagram for explaining an example of a conventional technique.

FIG. 15 is a diagram for explaining another example of the conventional technique.

FIG. 16 is a diagram for explaining another example of the conventional technique.

[Explanation of symbols]

1 Central Processing Unit, Upper Device (CPU) 2 Input / Output Processing Device (IOP) 3 Service Processor (SVP) 5 Power Supply Unit 6 Peripheral Device 7 Power Supply Control Unit 8 Cooling Device 9 Temperature Sensor 10 Upper Interface 20a-20n Channel Device (CH) ) 21 micro control unit 22 register (fault processing instruction information) 30 controlware control unit 31 file device 32 fault processing instruction information 33 console 50 power supply signal 60 lower interface 71 power control signal 101 fault processing step (determination of interrupt cause) 102 failure processing step (report of power failure) 103 failure processing step (judgment of normal termination of reporting) 104 failure processing step (blocking of upper interface) 105 failure processing step (judgment of interrupt cause) 106 failure processing step (of cooling failure) report) 107 Failure Processing Step (Judgment of Interrupt Cause) 108 Failure Processing Step (Report of Temperature Abnormality) 200 Peripheral Controller 201 Upper Interface Control Unit 202 Lower Interface Control Unit 203 Processor 204 Memory 205 Interrupt Circuit 206 Voltage Monitoring Circuit 207 Voltage Abnormality Detection circuit 208 State transition detection circuit 209 Cooling abnormality detection circuit 210 Internal bus 211 Temperature abnormality detection circuit

Claims (4)

[Claims] 1. A device connected to a higher-level device through a higher-level interface, and detecting means for detecting an abnormality related to the own device, and reporting the occurrence of a failure to the higher-level device based on the detection of this detecting means. A device connected to a higher-level device, comprising: processing means for processing the blockage of the higher-level interface after the report. 2. A device connected to a higher-level device through a higher-level interface, the detection means detecting an abnormality of a power supply supplied to the own device; and based on the detection of the detection means, a power failure of the upper-level device. A device connected to a higher-level device, comprising: processing means for reporting the occurrence and, after the reporting, processing for blocking the higher-level interface. 3. A device connected to a host device through a host interface, the device including a cooling abnormality detecting unit that detects an abnormality of a device that cools itself, and the host device based on the detection of the cooling abnormality detecting unit. A device connected to a host device, comprising: a processing unit that reports the occurrence of a cooling fault and, after the report, processes the blockage of the host interface. 4. A device connected to a host device via a host interface, the temperature anomaly detecting means for detecting an anomaly in temperature within the device itself, and the temperature of the host device based on the detection by the temperature anomaly detecting means. A device connected to a host device, comprising: processing means for reporting the occurrence of an abnormality and, after the report, processing for blocking the host interface.