JPS6219949A - Address converting device - Google Patents

Abstract

PURPOSE:To attain the address converting functions of 2 levels at a time with high efficiency by providing >=2 pairs of registers to hold the information needed for address conversion of two levels. CONSTITUTION:In an information processor of a virtual computer system, >=2 pairs of registers are provided independently of each other to holds the informa tion needed for address conversion together with the means which select the registers of each pair. Then the address converting processes are executed for >= 2 types of different architectures. Thus the address converting processes of >=2 levels can be executed in parallel with each other as much as possible. This improves greatly the address converting performance with >=2 levels as well as the address converting performance of 2 levels.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an address translation device in a virtual storage type information processing apparatus.

[Background of the invention]

In a virtual memory type information processing device, it is necessary to convert a virtual address when the information processing device accesses data or instructions in main memory to an absolute address in absolute main memory. Conventionally, this conversion means has been realized in various ways, such as by hardware logic or by intervention of a microprogram. Regarding the general specifications of so-called address conversion, which converts virtual addresses to absolute addresses, see, for example, the publication rzIB published by fBM.
M 5yste+s 3 7 0 Pr1n
ciples of 0perat, i.

n” (GA-22-7000) and “I B M
System 3 7 0 Ext, end
ed Architecture Pr1ncip
les of 0operation” (SA22-7
The details are described in 085).

As is clear from the above publications, it has become necessary for the architecture for address translation itself to be set up under completely different specifications. For example, as is clear from the above publication, there is a difference between the specifications of the address translation architecture in the "System/3F0 mode architecture" and the address translation architecture in the "370-XA mode." In this example, both In both architectures, in the procedure of cutting out the segment field, page field, and displacement field from the logical address, retrieving the segment table entry and page table entry respectively from main memory, and finally applying prefix conversion to the obtained real address. Although they are the same, there is a big difference in that the logical addresses and real/absolute addresses to be interpreted are 24-bit addresses on one side, while 31-bit addresses on the other. The major impact is the difference in the segment field (hereinafter abbreviated as SX), page field (hereinafter abbreviated as PX), and displacement field (hereinafter abbreviated as BX) and their address attributes. This has a major impact on the structure of the

As in the above example, measures have been taken to realize address translation for different architectures within a single processing device, and address translation devices that statically process address translation that satisfies the specifications of both so-called different architectures have been used. has also been realized. However, in this type of address translation device, although there is a function to statically perform address translation functions based on multiple architectures, it is possible to switch dynamically, and in addition, in the address translation process, multiple It is not possible to mix architecture address translation processes.

In recent years, a system called a virtual computer system has been realized, and many examples have been put into practical use in which multiple virtual computers are generated under a single real computer to construct an information processing system. The attributes of the address in this case are a level 1 address which is an absolute address in the real computer, a level 2 address which is a virtual address of the real computer but equal to the absolute address of the virtual computer, and a level 3 address which is a virtual address of the virtual computer. are categorized. When a real computer and a virtual computer each have address translations with different architectures, or.

The same is true even if a real computer and a virtual computer have address translation of the same architecture, but address translation from a level 3 address to a level 2 address must be based on the address translation architecture of the virtual machine, and from a level 2 address to a level 2 address. Address conversion to one address must be based on the address conversion architecture of the actual computer.

Conventionally, the process of converting an address from a level 3 address to a level 1 address is complicated.

It was not realized by hardware logic, and relied on a shadow conversion table generated from a microprogram called a virtual machine assist (hereinafter abbreviated as VMA) or a virtual machine control program (hereinafter abbreviated as VMCP). By preparing a shadow translation table by VMCP, address translation from a level 3 address to a level 1 address is treated by hardware in the same way as a pseudo translation from a level 2 address to a level 1 address. Although it has become possible to reduce the overhead caused by VMCP, there still remains an overhead for VMCP to prepare a shadow conversion table, and this overhead also causes a non-negligible drop in processing performance to the system.

A measure to eliminate this overhead is to eliminate the use of shadow tables, and an example of this method is outlined in Japanese Patent Laid-Open No. 57-212680. Also, a method has been proposed in which one or more so-called V=RVMs are generated, which in principle does not require the preparation of a shadow table.

The conventional method for converting level 3 addresses to level 1 addresses without preparing a shadow conversion table is
It has also been realized in the MA microprogram, and is also described in the above-mentioned Japanese Patent Application Laid-Open No. 57-212680. In particular, Japanese Patent Application Laid-Open No. 57-212680 describes a conversion means using a microprogram from a level 3 address to a level 1 address, but conversion using hardware is considered to have room for further performance improvement.

There is only a description that the function exists called acceleration mode, but there is no description of the specific means for realizing it.
Furthermore, the address translation hardware has essentially no difference from the logical structure that performs address translation in a single architecture, and is largely supported by microprograms, resulting in a dramatic improvement in the performance of address translation at two or more levels. I can't hope for that.

[Purpose of the invention]

An object of the present invention is to provide an address translation device that can efficiently translate multi-level addresses constructed using an arbitrary architecture in a virtual computer system.

[Summary of the invention]

A feature of the present invention is that it includes two or more sets of registers that hold address translation information necessary for two-level address translation, and efficiently performs two-level address translation functions based on different architectures (or the same architecture) at once. It is about to come true. Specifically, we have realized an address translation device that directly translates a level 3 virtual address requested by a virtual machine into a level 1 address, which is an absolute address of a real computer.

That is, in the present invention, address translation operations for different architectures (or the same architecture) use the same address translation circuit, and translation operations due to differences in architecture are dynamically switched, resulting in a change from a level 3 address to a level 1 address. The conversion to is performed in one address translation process.

[Embodiments of the invention]

FIG. 1 is a block diagram of an address translation device which is an embodiment of the present invention. In this embodiment, an example is shown in which two sets of address translation information are stored when performing two-level address translation.

In FIG. 1, reference numeral 1 denotes a control device (1) that controls the setting of register groups, data transfer, etc.
(hereinafter abbreviated as CU). 2 is an address translation execution stage, control of data transfer within the address translation device, and CUI.
This is an address translation control circuit (hereinafter abbreviated as DATCTL) that manages the exchange of control with the DATCTL. 3 is an address adder (hereinafter abbreviated as AA) that performs binary addition of two inputs;
The addition result of A3 is set in address latch 4 (hereinafter abbreviated as TAL). The data set in TAL4 is sent to CUI via signal line 109. 5 is 6.
6 is a selector circuit (hereinafter abbreviated as 5ELB) that selects one set of td input signals and sends it to the signal line 301;
This is a selector circuit (hereinafter abbreviated as 5ELA) that selects one set of input signals and sends it to the signal line 302.

Reference numeral 7 denotes a conversion logical address latch (hereinafter abbreviated as TLAX) which latches the address to be converted and sends the latched contents to DATCTL2 via the signal line 201. T
An address to be converted is set in LAX7 as necessary during the address conversion process from the CUI.

8 and 9 are conversion format registers (hereinafter abbreviated as HTFR and GTFR) that hold conversion formats used for address conversion of the real computer (host) and virtual computer (guest), respectively. CUI is installed in advance for HTFR8 and GTFR9.
, respectively, the conversion format data of the real computer and the conversion format data of the virtual computer are set via the signal fi102.

10 and 11 are segment table starting point registers (hereinafter referred to as H3TOR) that hold the segment table starting point and segment table length of the real computer and virtual computer, respectively.
and GSTOR). The segment table designation data of the real computer and the segment table designation data of the virtual computer are set in advance in H3TORI O and GSTORll from the CUI, respectively.

12 is a segment table entry register (hereinafter abbreviated as 5TER) that holds a segment table entry taken out in the address translation process, and 13 is a page table entry register (hereinafter abbreviated as PTER) that similarly holds a page table entry. 5TERI
2 and PTER 13 are used to hold tape menu entries for both the real computer and the virtual computer.

14 and 15 are conversion logical address registers (hereinafter abbreviated as HTLAR and GTLAR) that hold virtual addresses to be converted for a real computer and a virtual computer, respectively. HTLAR14 and GTLAR15 receive the corresponding virtual address from the CUI on signal line 1 during the conversion process.
Set via 06.

Reference numeral 16 denotes a main memory starting point address register (hereinafter referred to as MSO
The main memory starting point address of the corresponding virtual machine is set in advance in the MSOAR 16 (abbreviated as AR) via the signal line 103 by the CUI. Reference numeral 17 denotes a translation exception address register (hereinafter abbreviated as TEAR) which, when an exception to address translation occurs during the address translation process, sets and holds the virtual address that caused the exception.

Reference numeral 18 denotes a main memory range address register (hereinafter abbreviated as MSEAR) that holds a main memory range address that defines the main memory range of a virtual machine. The main memory cylinder address of is set.

FIG. 2 is a flowchart for explaining the operation of FIG. 1, and FIG. 3 schematically shows the operation. The numbers in circles in FIG. 3 correspond to the processing steps in FIG. The operation shown in FIG. 1 will be explained below along with the processing procedure shown in FIG. 2.

First, the processing from steps 501 to 506 will be explained (FIG. 3(a)).

Step 501 The CUI converts the virtual address of the virtual machine (hereinafter abbreviated as guest) requested to be converted into the GTLAR of this address translation device.
Signal lines 106 and 10 for I5 and TLAX7 respectively
1 through signal line 10, and further connect signal line 10 to DATCTL2.
8, an address translation activation request trigger is sent. That is, the same virtual address is set to GTLARI5 and TLAX7.

In this explanation, the host and guest program state word (PSW) address translation mode pits are both II.
Let us take as an example a case where address translation is required for both the host and the guest.

Step 502 DATCTL2, which has received the address translation start trigger, checks the format of the guest translation format data held in GTFR9 based on the guest address translation architecture, and if it is an invalid format, it sends a cUL signal to that effect via signal a108. and stops further address translation operations.

The guest conversion format data held in GTFR9 is
Specifically, it defines the segment size and page size of the guest address translation architecture. As an example, the publication "IBM Sys" published by IBM Corporation
tem 370 Pr1ciples ofOpe
rat, ion'' (GA-22-7000) and re
IBM System 3 7 0
Extended ArchitecturePri
ciples of zero peration”
(SA-22-7085), if the segment size is 64 bytes and the page size is 2 bytes, the value is (01000)2, and if the segment size and page size are 1 MB and 2 bytes, respectively. is (01010)2.64 bytes and 4 bytes is (10000)z, 1M byte and 4 bytes is (10000)z.
1001o3z or (10110).

It is.

DATCTL2 is, well? :, 5E sends an instruction to output the guest segment table specification data held in GSTORI 1 to the signal line 305 via the signal line 303.
The segment table length of the segment table designation data issued to LB5 and obtained via the signal line 305;
Compare the segment field (hereinafter referred to as SX) of the guest virtual address (hereinafter referred to as GVA) sent from TLAX7 via the signal line 201 based on the guest address translation architecture, and if the guest SX is larger, Report this to CUl via the signal line 108,
Stops subsequent address translation operations.

DATCTL2 simultaneously issues an instruction to set GVA held in GTLARI5 to TEAR17 via signal line 306 to 5ELA6 via signal line 304, and also issues an instruction to 5ELB5 via signal line 303 to signal LA206. Out of the contents of GSTORI 1 being sent, an instruction is issued to extract only the segment table starting point data and sending it to the signal line 301, and the contents of GTLAR15 are sent to the signal line 210 to 5ELA6 via the signal line 304. After cutting out the SX part of the GVA and performing a predetermined shift and LL OJJ insertion based on the guest address translation architecture, the signal line 3 is
Issue an instruction to send to 02.

Address calculator 3 uses guest segment table starting point address (GSTO) sent to signal lines 301 and 302.
and the guest's sx (GSX), and set the addition result to TAL4. The content set in TAL4 here is the Guess 1-Segment Table Entry (hereinafter referred to as II).
This is the level 2 real address (GR) of the GsTE (abbreviated as GsTE) and is sent to the CUI via signal line 109.

Step 503 The CUI performs prefix conversion on the GSTE level 2 address (G R) sent via the signal line 109 using the guest prefix value, and sets it in HTLARI4 via the signal line 106. The address set in HRLARI 4 is a GSTE level 2 absolute address (GA).

DATCTL2 issues an instruction to 5ELB5 via the signal line 303 to select and output the main memory range address, which is the content of MSEAR18 outputted to the signal a211, to the signal line 301, and further via the signal line 304. Te5
HTLA output to signal line 209 for ELA6
An instruction is issued to select and output the GSTE level 2 absolute address, which is the content of RI 4, to the signal line 302. A.A.
3 performs a comparison operation between the main memory range address output to the signal lines 301 and 302 and the level 2 absolute address of the GSTE, and sets the comparison result in TAL4. If the level 2 absolute address of GSTE is larger than the main memory range address, TAL4 sends a message to that effect via signal line 307 to DA.
Report to TCTL. When the DATCTL 2 receives the report signal, it reports the fact to the CUI via the signal line 108.

Stops subsequent address translation operations.

Step 505 If the level 2 absolute address of GSTE is within the main memory range address, DATCTL2 outputs the MSOARI output to signal lX204 to 5ELB5 and 5ELA6 via signal line 303 and signal line 304, respectively.
Select the main memory starting point address, which is the content of 6, and connect the signal line 30.
1 and is output to the signal line 209) H
An instruction is issued to select the level 2 absolute address (GA) of GSTE, which is the content of TLARI4, and output it to the signal line 302.

AA3 adds the main memory starting point address output to signal lines 301 and 302 and the level 2 absolute address of GSTE, and sets the addition result in TAL4. This TAL4
The address set to is the GSTE level 1 virtual address, which is equal to the GSTE level 1 real address if the address translation mode pit of the host's PSW is 1101'.

The address conversion mode pit of the host IP SW is I
If the bit is "Og", the process advances to step 514, but this example shows the case where this bit is "1".

The GSTE level 1 virtual address set in TAL4 is sent to the CUI via signal line 109.

Step 506 CUI receives the level 1 virtual address of GSTE via signal line 109 and converts it to HTLAR via signal line 106.
I set it to 4 and also set it to TL via the signal line lot.
Set it to AX7.

Next, the processing from steps 507 to 513 will be explained (FIG. 3(b)).

Step 507 DATCTL2 checks the host translation format data held in HTFR8 based on the host address translation architecture, and if the format is invalid, reports the fact to CUI via signal line 108, and performs subsequent address translation. Stop operation.

DATCTL2 simultaneously transfers the held host segment table specification data to signal line 3.
An instruction to output to 05 is sent to 5EL via signal line 3゜3.
The segment table length in the segment table designation data sent to B5 and obtained via the signal line 305, and T
Host virtual address (level 1 virtual address) (hereinafter referred to as HVA
(abbreviated as ) based on the host address translation architecture, and if the host SX is larger, this is reported to CU1 via the signal line 108, and subsequent address translation operations are stopped.

DATCTL2 simultaneously issues an instruction to set the HVA held in HTLARI4 to TEAR17 via signal line 306 to 5ELA6 via signal 8304, and sends a signal @205 to 5ELB5 via signal line 303. It issues an instruction to extract only the segment table starting point data (HS TO) out of the contents of the H5TORIO that is being processed and sends it to the signal line 301, and further sends the HTLARI data sent to the signal line 209 to the 5FLA6 via the signal line 304. After cutting out the SX part of the HVA which is the contents of 4 and inserting a predetermined shift and "0" based on the host address translation architecture, an instruction to send it to the signal line 302 is issued.

AA3 adds the host segment table starting point address (H3T○) sent to signals m301 and 302 to the SX section of the HVA, and sets the addition result in TAL4. The address set in TAL4 here is the level 1 real address (HR) of the host segment table entry (hereinafter abbreviated as H3TE), and is sent to CU1 via signal line 109.

Step 508 The CUI uses the level 1 real address of the HSTE sent via the signal line 109 to issue a read request for the HSTE to the main memory.

Step 509 The CUI transmits the HSTE read from the main memory to the signal line 10.
5 to 5TER12 via the signal line 108, and reports this to the DATCTL2 via the signal line 108.

Step 510 DATCTL2 is connected to step 50 via signal line 108.
Based on the host address translation architecture, the H3TE invalid bit (I
If the invalid bit is '1', this fact is reported to the CUI via the signal line 108, and subsequent address conversion operations are stopped.

DATCTL2 simultaneously connects 5TE via signal line 303.
The contents of RI2 are sent to DATCTL2 via the signal line 305.
This operation checks the HSTE format based on the host address translation architecture, and if there is a format violation, the CUI is sent via the signal line 108.
The address translation operation will be stopped from now on.

DATCTL2 simultaneously outputs a signal to 5ELB5 via signal line 303 to output the contents of HSTE held in 5TER12 to signal line 305, and outputs the page table length of HSTE obtained via signal line 305 and TLAX.
The px part of the host virtual address sent from 7 via the signal line 201 is compared based on the host address translation architecture, and if the host PX is larger, that fact is reported to the CUI via the signal line 108. The address translation operation after that is stopped.

At the same time, DATCTL2 sends an instruction to cut out only the page table starting point data (HPTO) from the contents of 5TER12 sent to signal [207 and send it to signal line 301 to 5ELB5 via signal i@303. HTLARI which is further sent to the signal line 209
After cutting out the px part (HP
An instruction to send the signal to the signal line 302 is sent to the 5ELA6 via the signal B504.

AA3 adds the host page table starting point address (HPTO) sent to signals 11301 and 302 with the px section (HPX) of HVA, and sends the addition result to TAL4.
Set to . Here, the address set in TAL4 is the level 1 real address (HR) of the host page table entry (hereinafter referred to as HPTE), and the address set in TAL4 is the level 1 real address (HR) of the host page table entry (hereinafter abbreviated as HPTE), and
09 to CUI.

Step 511 The CUI uses the level 1 real address of the HPTE sent via the signal line 109 to issue a read request for the HPTE to the main memory.

Step 512 The CUI transmits the HPTE read from the main memory to the signal line 105.
PTERI 3 via signal line 108, and reports this to DATCTL2 via signal line 108.

Step 513 DATCTL2 is connected to step 51 via the signal line 108.
When it is reported that the execution of step 2 has finished.

Based on the host address translation architecture, I]PT
It is checked whether the invalid bit (E bit) of E is 111 IP, and if the invalid bit is II II II, this fact is reported to the CUI via the signal line 108, and the subsequent address translation operation is stopped.

DATCTL2 simultaneously connects PTER via signal line 303.
An instruction is issued to send the contents of I3 to DATCTL2 via the signal line 305, and this operation performs a HPTE format check based on the host address translation architecture, and if there is a format violation, it is sent to the CUI via the signal line 108. It reports this and stops subsequent address translation operations.

At the same time, DATCTL2 sends an instruction to edit only the page frame real address (hereinafter abbreviated as PFRA) part of the contents of PTERI3 sent to the signal line 208 based on the host address translation architecture and send it to the signal line 301. Send to 5ELB5 via signal line 303,
Furthermore, BX of the HVA sent to the signal line 209
After cutting out the part (HBX) and editing such as predetermined shifts and insertion of "0" based on the host address translation architecture, an instruction to send it to the signal line 302 is sent to the 5ELA6 via the signal line 304. do.

2N, in step 510 or step 513, depending on the applicable architecture, the storage protection bit of the address translation table is saved in DATCTL2.

AA3 is the host P sent to signal lines 301 and 302.
FRA (HPFRA) and HVA (7) BX section (HB
X) and set the addition result to TAL4. Here, the address set in TAL4 is the level 1 real address (HR) of the guest segment table entry (hereinafter abbreviated as GSTE), and is sent to the CUI via the signal line 109.

Next, the processing from steps 514 to 519 will be explained (FIG. 3(C)).

Step 514 The CUI uses the GSTE level l real address (HR) sent via the signal line 109 to write the G to main memory.
At the same time as issuing a STE read request, the contents of GTLARI5 are sent to 5ELA6 via the signal line 304 and TEAR
I issue an instruction to set it to 17. At the same time, CUI sets GVA to TLAX7 via signal line 101. or,
It sets the read GSTE to 5TERI 2 and reports this to DATCTL2 via the signal line 108.

The soup 515 DATCTL2 is connected to the step 51 via the signal line 108.
Based on the guest address translation architecture, the DSTE invalid bit (I
If the invalid bit is 111H, this fact is reported to the CUI via the signal line 108, and subsequent address translation operations are stopped.

DATCTL2 simultaneously connects 5TE via signal line 303.
5E sends an instruction to send the contents of R12 to the signal line 305.
This operation checks the format of GSTH based on the guest address translation architecture, and if there is a format violation, it is reported to CU1 via the signal line 108, and subsequent address translation operations are stopped.

DATC:TL2 simultaneously stores the GSTE's common segment bits or storage protection bits in DATCT:L2, depending on the appropriate architecture.

DATCTL2 also outputs a signal to 5ELB5 via signal line 303 to output the contents of GSTE stored in 5TERI 2 to signal line 305;
The page table length of GSTE (,GP
TL) and the PX part (GPX) of the guest virtual address sent from TLAX7 via the signal line 201 based on the guest address translation architecture, and if the guest PX (GPX) is larger, the is sent to the CUI via the signal line 108, and subsequent address conversion operations are stopped.

At the same time, DATCTL2 sends an instruction to 5ELB5 via signal a303 to extract only the page table starting point data (GPTO) from the contents of 5TER12 sent to signal line 207 and send it to signal line 301, and then After cutting out the PX portion (GPX) of the GVA that is the content of GTLAR 15 sent to the signal line 210 and performing editing such as a predetermined shift and II OHp insertion based on the guest address translation architecture, the signal line 302 5E via the signal line 304.
Send to LA6.

AA3 is the guest page table starting point address (GPTO) sent to signal lines 301 and 302 and the px of GVA.
(GPX) and sets the addition result to TAL4. 2\, the address set in TA14 is the guest page table entry (hereinafter abbreviated as GPTE)
This is the level 2 real address (level 1 virtual address) of , and is sent to the CUI via signal line 109.

Step 516 The CUI performs prefix conversion on the GPTE level 2 address (G R) sent via the signal line 109 using the guest prefix value, and sets it to HTLAR1,4 via the signal line 106. The address set in HTLARI 4 is a GPTE level 2 absolute address (GA).

Step 517 Step 517 performs the same operations as step 504, except that the GPTE level 2 absolute address is replaced with the GSTE level 2 absolute address.

Step 518 Step 518 performs the same operation as step 505, except that the GPTE level 2 absolute address is replaced with the GSTE level 2 absolute address.

2\, the address set in TAL4 is GPTE
is the level 1 virtual address of the host and is equal to the GPTE level 1 real address if the address translation mode bit of the host's PSW is '0''.

If the address translation mode pit of the host PSW is '0'', the process proceeds to step 524, but this example shows the case where this bit is II III II.

The GPTE level 1 virtual address (HV) set in TAL4 is sent to CU1 via signal line 109.

Step 519 The CUI receives the GPTE level 1 virtual address (HV) via the signal line 109 and transfers it to H via the signal line 106.
It is set to TLARl4 and is also set to TLAX7 via the signal line 101.

Next, the processing from steps 520 to 526 will be explained (FIG. 3(d)).

Step 520 Step 520 performs the same operation as step 507, checks for an invalid format, and checks the host segment length (HS T
Comparison check between L) and host SX (H8X), host segment table origin (HST○) and host SX
(H5X) is added.

Step 521 In step 521, the same operation as in step 508 is performed.

Step 522 In step 522, the same operation as in step 509 is performed.

Step 523 In step 523, the same operation as step 510 is performed, checking the invalid bit (■ bit) of HSTE,
STE format check, host page table length (HP
Comparison of host page table origin (HPTO) and host PX unit (HPX)
X), obtains the HPTE address from TAL4, and sends it to CUI.

Step 524 Step 524 performs the same operation as step 511.

Step 525 Step 525 performs the same operation as step 512.

Step 526 Step 526 performs the same operation as step 513,
Check the invalid bit (■ bit) of HPTE, check the format, add PFRA (HP F RA) of PTER13 and BX part (HBX) of HTLARI4, and set the result to TAL4.

The address set in TAL4 is the guest PT.
Level 2 real address (HR) of E, signal line 109
is sent to CUI via.

Next, the processing from steps 527 to 532 will be explained (FIG. 3(e)).

Step 527 The CUI uses the level 1 real address (HR) of the incoming GPTE sent via the signal line 109 to address the G
At the same time as issuing a PTH read request, the contents of GTLARI5 are sent to 5ELA6 via the signal line 304 and TEAR
I issue an instruction to set it to 17. At the same time, CUI sets GvAt&TLAX7 via signal $A101. It also sets the read GPTE in PTER13 and reports this to DATCTL2 via signal line 108.

Step 528 DATCTL2 is connected to step 52 via signal line 108.
When it is reported that the execution of PTER 7 has finished, based on the guest address translation architecture, the
It is checked whether the invalid bit (ebit) is re 1 n, and if the invalid bit is '1'', that fact is sent to the signal line 10.
8 to CU1, and the subsequent address translation operation is stopped.

DATCTL2 also connects PTE via signal line 303.
5E sends an instruction to send the contents of R13 to the signal line 305.
A GPTE format check is performed based on the guest address translation architecture by sending one line to LB5, and if there is a format violation, the fact is reported to the CUI via the signal line 108, and subsequent address translation operations are stopped.

DATCTL2 simultaneously stores the GPTE storage protection bits in DATCTL2 depending on the appropriate architecture.

DATCTL2 simultaneously reads the guest PFRA part (G
An instruction to edit only P F RA) based on the guest address translation architecture and send it to signal line 301 is sent to 5ELB5 via signal line 303, and further to signal line 2.
BX part (GBX) of GVA sent to 10
A predetermined shift based on the guest address translation architecture and an instruction to send to the ``0''b line 302 are sent via the signal line 304.
Send to ELA6.

AA3 is the guest P sent to signal lines 301 and 302.
FRA (GPFRA) and GVA (71BX section (GB
X) and set the addition result to TAL4. The address set in TAL4 here is the guest real address (GR) and is sent to the CUI via the signal line 109.

Step 529 The CUI performs prefix conversion on the guest real address (hereinafter abbreviated as GRA) sent via the signal line 109 using the guest prefix value.

Set to HTLARI 4 via signal fi106. The address set in HTLARI 4 is the guest's level 2 absolute address.

Step 530 Step 530 sets the level 2 absolute address of the guest to G
Replace with STE level 2 absolute address, step 5
Perform the same operation as 04.

Step 531 Step 531 sets the level 2 absolute address of the guest to G
Replace with STE level 2 absolute address, step 5
Perform the same operation as 05.

The address set in TAL4 is the guest's level 1 address.
If it is a virtual address and the address translation mode pit of the host's PSW is u O, then the guest's level 1
Equal to real address. If the address translation mode of the host PSW is 110'', the process proceeds to step 540, but in this example, the case where this bit is LL L 11 is shown.

The guest's level 1 virtual address (HV) set in TAL4 is sent to CU1 via signal line 109.

Step 532 Step 532 replaces the GPTE's level 1 virtual address with the guest's level 1 virtual address and steps 5
Perform the same operation as No. 19.

Next, the processing from steps 533 to 540 will be explained (FIG. 3(f)).

Step 533 Step 533 performs the same operation as step 507.

Step 534 Step 534 performs the same operation as step 508.

Step 535 Step 535 performs the same operation as step 509.

Step 536 Step 536 performs similar operations to step 510.

Step 537 Step 537 performs the same operation as step 511.

Step 538 Step 538 performs the same operation as step 512.

Step 539 Step 539 performs the same operation as step 513.

The address set in TA L 4 is the guest's level 1 real address and is sent to CUL via signal line 109.

Step 540 The CUI receives the level 1 real address sent via the signal line 109, and further sends the DATC via the signal line 108.
The common secment bit and storage protection bit stored in TL2 are retrieved. Thereafter, a data read request is issued to the main memory.

Although one embodiment of the present invention has been described above, the guest virtual address may be taken out from GTLARI 5 and re-sent to CUl, or the structure may be such that the guest virtual address is taken out from GTLARI 5 and re-sent to CUl, or 5TERI2 and PTERI3
may be in the same register.

Alternatively, H5TORIO and GSTORI 1 may be made the same register, and CUl may be replaced each time it is used, or TLAX7 and HTLARI4 may be made the same register.

Alternatively, the HTLAR 14 and GTLARI 5 may be made into the same register, and CUl may be replaced each time it is used.

Furthermore, in the flow diagram of FIG. 2, each step may be realized by competing or separating each step as necessary.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, each address conversion process for two or more levels of address conversion can be executed in parallel as much as possible, and the performance of two or more levels of address conversion can be dramatically improved. , it is also possible to dramatically improve the two-level address translation performance of different architectures.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
A processing flow diagram for explaining the operation of the figure, Figure 3 is the first
It is a schematic diagram for demonstrating the operation|movement of a figure. 1... Control device, 2... Address conversion control circuit,
3...Address adder, 4...Address latch, 5...Selector B, 6...Selector A,
7... Conversion logical address latch, 8... Host conversion format % expression % starting point register, 11... Guest segment table starting point register, 12... Segment table entry register, 13... Page table entry register, 14...Host translation logical address register, 15...Guest translation logical address register, 16...Main memory starting point address register,
17... Conversion exception address register. 18...Main memory range address register. Figure 2 (2) Figure 2 (Figure 2 (C)

Claims (1)

[Claims] (1) A virtual machine type information processing device is provided with two or more independent sets of registers that hold address translation information necessary for address translation, and is provided with means for selecting each set of registers, so that two or more types of different architectures can be used. An address translation device characterized in that it performs each address translation process.