JPS62195929A - Switch element for ladder resistance network - Google Patents

Abstract

PURPOSE:To decrease the element dimension and the pattern area by using a push-pull buffer circuit formed by an N-channel MOS transistor (TR) only as a switch element. CONSTITUTION:A push-pull buffer circuit BUF comprising N-channel MOS TRs N3, N4 is used as a switch element SWi, and a bit ai of a digital input and an output ai' of a CMOS inverter I1 of the pre-stage are given as complementary input signals. The TRs N3, N4 are connected in series between a reference voltage Vref node and a VSS potential node in the buffer circuit BUF and each base is connected to respective sources. Since the potential of the base of the TR N3 at the reference voltage node side of the buffer circuit BUF is the same potential as the source, even under the condition that there is a potential difference between the power potential VDD for each bit of the digital input and a switch element reference potential Vref, no back gate bias is applied, the effect of the back gate bias effect (increase in on-resistance) is not received, and the increase in the pattern area attended with the increased current amplification factor beta to suppress the increase of the on-resistance is not incurred.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application If) The present invention relates to a ladder resistance type digital-to-analog (D/A) conversion circuit used in various electronic devices, and in particular to an integrated circuit. The present invention relates to a MOS type switch circuit for a ladder resistance network.

(Prior Art) This type of conventional ladder resistance type D/A conversion circuit has a resistor R as shown in FIG. -Rn and resistors r1 to rn-1 are connected in a ladder arrangement, input voltage v1 is applied to input terminal (one end of resistor R) 1, and each terminal of resistor R1 to Rn is connected to a switch. Each pitch {a1~&n of the dezotal input is applied via the elements SW1~SWn, and the analog conversion output voltage Vout is obtained from the output terminal (interconnection point between the resistor ryl-1 and the resistor Rn) 2. has been done. In this case, the resistance rH(1;=1.

... n-1) resistance value is R, then resistance J(+ =
0.

. . . The resistance value of n) is selected to be 2R. Now, if the potential of any bit al (1≦l≦n) of the digital input is set to V+ (=”01 level) or V2 (=”19 level), the output voltage Vout will be...(1) . However, when a(-=V1, , = n
Q″, when a 1 =V2, 81=″1″.

As mentioned above, in the ladder resistance type D/A conversion circuit shown in FIG. 2, the resistance value provided corresponding to each bit is R.
, 2R, two types of resistors are connected to form a ladder-shaped resistor network, so only two types of resistance values are required, the circuit configuration is simple, and it is extremely convenient for integrated circuits. It has characteristics and is widely used. In addition, the characteristic feature of the above circuit is that it is necessary to perform accurate current distribution in the ladder resistor network.
Although the absolute accuracy of the resistance values R and 2R is not so necessary, the relative ratio (resistance ratio) of the resistance values R and 2H is required to have high accuracy, and this requirement becomes stricter as the resolution of D/A conversion increases. In addition, if the on-resistance value of the voltage mode switch element connected to the resistor with a resistance value of 2R provided corresponding to each bit cannot be ignored with respect to the reference resistance value RK, the D/A
This is known to cause conversion errors. Therefore, it is necessary to make the on-resistance value of the switch element sufficiently smaller than the reference resistance value H.

By the way, conventionally, the switch elements s'w1 to swn are each made on an N-type silicon substrate and cascade-connected in two stages (Z)0MO, as shown in FIG.
8 (7 Haak 11, I2 was used.

The preceding stage CMOS inverter I1 has a P-channel MOS transistor P1 and an N-channel MOS transistor N1 connected in series between the vDD potential node and the Vllll potential node, and each substrate is connected to the respective source S. Oshi, f-to interconnection end (long sword node)
is given bit a1 of the r digital input.

In the subsequent CMOS inverter I2, a P-channel MO8 transistor P2 and an N-channel MOS) run resistor N2 are connected in series between the reference voltage Vref node and the vs8 potential end, and the output node thereof is connected to a resistor R1 having a resistance value of 2R.
connected to one end of the In this case, N-channel MOS
) The substrate of run lister N2 is connected to the source SfC, but the substrate of P channel MO8) run lister P2 is connected to vD.
Connected to the D potential node. In the D/A conversion circuit using the above CMOS inverter h + I2 as a switching element, each pin of the dezotal input
Assuming that the level is the ground potential, the '1'' level is the vDD potential (for example, 5V), and the maximum amplitude of the output voltage Vout is 2V, the reference voltage Vref=''l, v, V potential is set to the s ground potential. Generally, the on-resistance R6N in a MOS) runnostar is in the non-saturation region 1vcs-vt
l>IVD81 (here, vo8 is the dart-source voltage, vT is the gate threshold voltage, and VDll is the drain-source voltage), and is expressed as the following equation.

Here, IDa is a drain-source current, and β is a current amplification factor. On the other hand, P of the CMOS inverter I2 in the subsequent stage
Channel controller/nostar P2 has a reference voltage Vre at its source.
f (= 2 v) is given, but since the substrate is connected to the DD potential (= 5 v), a pack dart bias of 3 v is applied between the substrate and the source. The on-resistance R8NP2 of the P-channel transistor P2 is expressed as a ninth-order equation different from the previous equation (2).

Here, is the amount of change in threshold voltage due to pack dart bias. Therefore, the P-channel transistor P2 has an on-resistance R0 due to an increase in the threshold voltage.
NP□ increases. However, due to this, as mentioned above, the switch element SW.

If the on-resistance value of ~SWn cannot be ignored with respect to the reference resistance value R, this is not preferable because it causes a conversion error. Therefore, as a means to suppress the increase in on-resistance due to the pack gate bias effect as described above, a method has been adopted in which the current amplification factor β is increased by increasing the channel width, which is an element dimension element of the MOS (MOS) run lister. However, this method has the disadvantage that the channel width increases, leading to an increase in the circuit area of the switch element on the integrated circuit.

(Problems to be Solved by the Invention) As described above, the present invention solves the problem of the power supply voltage v for digital input.
Under conditions where there is a potential difference between DD and the reference potential Vref for the switch element, the /f turn area of the switch element is increased in order to suppress an increase in on-resistance due to the pack gate bias effect of the switch element. The present invention has been made in order to eliminate the drawbacks of the switching elements being packed together, and to provide a switch element for a ladder resistor network in which the on-resistance of the switch element is not affected by the packed date bias effect and the turn area of the switch element is small. [Structure of the Invention] (Means for Solving the Problems) The switch element for a ladder resistance network of the present invention is an N-channel M
It is characterized by using a Bushdel type buffer circuit formed only of O3 transistors.

(Function) Since the substrate and source of the N-channel transistor on the reference 1 voltage node side of the push-pull buffer circuit are at the same potential, the power supply potential VDD for digital input and the power supply potential for the buffer circuit (reference Since no gate bias is applied even under conditions where there is a potential difference with the potential (Vref), it is no longer affected by the back gate bias effect (increase in on-resistance), and the increase in on-resistance can be suppressed. Therefore, there is no need to increase the pattern area of the switch element.

(Example) An example of the present invention will be described in detail below with reference to one drawing.

The ladder resistor network switch element shown in FIG. 1 is a rear-stage C
In place of the MOS inverter E2, a push-glue buffer circuit BUF consisting of N-channel MO8) run-listers N3 and N4 is used, and a digital input signal BUF is used as a complementary input signal of a pair of input nodes of this buffer circuit BUF. The output voltage of the CMOS inverter 11 at the previous stage is also changed, and the same parts as in FIG. 3 are given the same reference numerals and their explanations are omitted.

The buffer circuit BUF has an N-channel MO8) run lister N3. between the reference voltage Vr@f node and the v0 potential node. N4 are connected in series, each substrate being connected to its respective source S.

According to the switch element described above, only the N-channel MO8) Lanzostar Ns, N4 is connected to one end of the resistor R1 with a resistance value of 2R provided for each bit of the ladder resistance type D/A conversion circuit shown in FIG. The output node of a push-pull buffer circuit BUF consisting of the following is connected. Therefore, since the substrate of the N-channel transnostor NS on the reference voltage node side of the buffer circuit BUF has the same potential as the source, there is a gap between the power supply potential VDD for each bit of the digital input and the reference potential Vref for the switch element. Even under conditions where there is a potential difference between This does not result in an increase in the four-turn area due to this. Moreover, N channel MO
The current amplification factor βN of the S transistor is the P channel MOS
It is about twice as large as the current amplification factor βP of a transistor for the same element dimensions, so it takes more time to realize a switch element with the same on-resistance than when it is made using a conventional CMOS inverter (I2 in Figure 3). However, as in this example, fabricating a loose buffer circuit BUF using only N-channel transistors has the advantage that the element size and no-turf area can be smaller, which is suitable for integrated circuit implementation.

Note that the push-pull buffer circuit BUF of the above embodiment
The digital input bit aI and its complementary signal i may be input to the pair of input nodes, and the CMOS inverter 11 at the previous stage may be omitted or replaced with another circuit as necessary.

〔Effect of the invention〕

As described above, according to the switch element for a ladder resistance network of the present invention, the power supply potential for digital input and the power supply potential (reference potential) for the switch element in the pressure mode provided for each bit of the digital input are Even under conditions where there is a potential difference between them, no pack date bias is applied to the switch element, so it is not affected by an increase in on-resistance due to the pack r-) bias effect. Also, P channel M
Since the switching element is formed only by the N-channel MOSFET 8) which has a large current amplification factor, the device size and set-up area are advantageously small.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the ladder resistance network switch element of the present invention, FIG. 2 is a configuration explanatory diagram showing a ladder resistance type D/A conversion circuit, and FIG. FIG. 2 is a circuit diagram showing a conventional example of a switch element for a ladder resistance network. r l~rn-1"'resistance (resistance value R), RO-Rn
...Resistance (resistance value 2 R), a1-an...Digital input, BUF...Push-pull type buffer circuit,
N5. N4...N channel MOS transistor, vD
D: Power supply potential for digital input, Vref: Power supply potential for pushpull type buffer circuit.

Claims (2)

[Claims] (1) The resistance value corresponding to each bit of the digital input in a ladder resistance network formed by connecting a plurality of resistors with a resistance value of R and a plurality of resistors with a resistance value of 2R in a ladder shape is A switch element for a ladder resistor network, characterized in that a push-pull type buffer circuit consisting of an N-channel MOS transistor is used as a switch element connected to each end of a 2R resistor. (2) Claim 1, characterized in that there is a potential difference between a power supply potential for a digital input serving as an input of the push-pull buffer circuit and a power supply potential for the push-pull buffer circuit. Switch element for the ladder resistance network described.