JPS58202622A - Digital-analog converting circuit - Google Patents

Abstract

PURPOSE:To keep a small chip area and at the same time to improve the accuracy of conversion, by having a constant level for the gate-source voltage of an MOSFET which is used as a switch. CONSTITUTION:When the signal D of the highest bit is inverted into the level ''1'', an MOSFET32 is turned on. Then a current I1 flows from the input voltage VIN through a resistance 34. The same working is secured also with signals of optional bits D2-Dn, and then a digital signal is converted into an analog current. In this case, the sources of MOSFET31 and 32 which are controlled with the signal D1 are connected to the earth potential, respectively. Therefore, the gate-source voltage VGS is constant for FETS 31 and 32 despite of the variation of the reference voltage VREF and the voltage VIN. While the potential is set approximately at a constant level at the joint of a resistance 11 although it increases gradually. As a result, the voltage VGS is also set approximately at a constant level for FET31 and 32, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital-to-analog conversion circuit using a resistance ladder circuit system.

[Technical background of the invention and its problems]

FIG. 1 is a circuit diagram showing the principle of a digital-to-analog conversion circuit (hereinafter referred to as a DA conversion circuit) using a resistance ladder circuit system. In the figure, a plurality of resistors 11, 11, . . . each having a value of R are connected in series to form a series circuit. A ground potential is applied to one end of this series circuit. Further, each of the series connection points of the series circuit U, the other end, and the resistor 11 has two
Each resistor 12. has a value R. One end of the resistor 12, 12°... is connected to the other end of each switch 13. Digital signal, -Dn (where, is the most significant bit, Dn
is the least significant bit), one of the reference voltage VREF and the input voltage VIN is selected according to the respective levels. Further, a resistor 14 having a value of 2R is connected between the terminal end of the series circuit mark and the reference voltage VREF application point. It is assumed that the values of the reference voltage VRilF and the input voltage VIN are equal.

In the D-A conversion circuit having such a configuration, if all the switches 13 are currently selecting the reference voltage VREF 11, the most significant bit signal.

A current I1 flows through the resistor 12 to which the switch 13 controlled by P is connected, and each switch 13 controlled by the lower bit signal Dn is also connected to this A current of I2 (=+I+ L~In(=,;H-+I+) flows through each resistor 12. Next, in such a state, when only the most significant bit signal is inverted, this signal becomes The switch 13 controlled by the switch 13 selects the input voltage VIN.Then, the current 2 that was flowing through the resistor 12 is now caused to flow by the input voltage VIN.Therefore, at this time, the current flowing from the point where the input voltage VIN is applied is I1. becomes.

Further, when only the signal of the bit following the most significant bit is inverted, the switch 13 controlled by this signal D2 selects the input voltage VIN. Then, the current I flowing through the resistor 12 is also caused to flow by the input voltage VIN. Therefore, at this time, the current flowing out from the point where the input voltage VIN is applied is I2. Below, digital signal D1
When Dn is inverted, the value of the current flowing out from the point where the input voltage VIN is applied changes corresponding to D1 to Dn. Therefore, in the above digital signal, -Dn is converted into the corresponding analog current. It is.

In the above D-A conversion circuit, each switch 13 is a MOS
When realizing the circuit using FETs and integrating the circuit, conventionally, each switch 13 is configured with a P-channel MO8F'ET and an N-channel MO8F'ET, respectively, as shown in FIG. That is, one each P-channel MO8FET 1
C-MO8 switch υ consisting of 5 and N-channel MO8FET I6 connected in parallel and one P-channel MO
8FET f 8 and N channel MO8FET 19
One end of another C-MOS switch formed by connecting in parallel is connected to each resistor 12. One of the above C-MOS
The other end of the switch U is connected to the reference voltage '/ngy application point, and the other end of the other C-MOS switch 20 is connected to the input voltage VI.
Connect to the N application point. And MO8FET 25°19
Each digital signal D1 to Dn is input to both darts,
Further, each digital signal D1 to Dn is inputted to both the darts of the MO8FETs 16 and 18 via each inverter 21.

In this circuit, when the digital signal is at the "1" level, one C-MO8 switch 20 is turned on and the input voltage V
When IN is selected and the digital signal is at the "0#" level, the other C-MOS switch 2 is turned on and the reference voltage VBEF is selected.

By the way, in the conventional circuit shown in FIG. 2 above, each C-MO8
When trying to design the on-resistance of switch 17.20 to be small, each MO8FET J 5, 16°114.19
It is necessary to increase the element size, which has the disadvantage of increasing the chip area.

Therefore, in order to reduce the chip area, conventionally,
Each switch 13 is connected to two MO8Fs of the same channel type.
This is realized by ET.

FIG. 3 is a conventional circuit configuration diagram in which each of the switches 13 is realized by two N-channel MO8FE'r' 2 and 23, for example. In this circuit, the drains of two N-channel MO8FETs 22 and 23 are both connected to the resistor 12, the source of one MO8FET 22 is connected to the reference voltage vR liver application point, and the source of the other MO8FET 22 is connected to the reference voltage vR liver application point.
The source of FET 23 is connected to the input voltage VIN application point. The substrates of both MO8FF and T22, 23 are connected to their respective sources, and the dirt of MOS FET 22 receives digital signals 1~ through inverter 24, and the r-)K of MOSFET 23 directly receives digital signals. is inputting information.

In this circuit, when the digital signal is at the "1# level", one MOS FIT 23 is turned on and the input voltage V
When IN is selected and the digital signal is at the ``0# level'', the other MOS FET ?2 is turned on and the reference voltage viewer is selected.

In the circuit shown in Figure 3 above, the switch 13 is two MOS FEs.
Since the circuit is composed of T, the chip area can be made smaller than that of the circuit shown in FIG. However, from Hiko, MO
Since the source of 8FB'l''2.23 is connected to the reference voltage VRKF application point or the input voltage 'l'IN application point, when this voltage VntFrv4 fluctuates, the MOS
FET? 2, 23 (Dr-to-source voltage VG8 also fluctuates, and as a result, both MO8FETs, ?
The on-resistances of 2 and 23 vary significantly. M.O.S.
FET? Since the on-resistances 2 and 23 are inserted in series with each resistor 12, when this on-resistance changes, the values of the currents 11 to In also change, and this change appears as a conversion error. .

Figure 4 shows the MOSF with respect to VRIF and VIN fluctuations.
FIG. 3 is a characteristic diagram showing changes in on-resistance ROM of ET.

In the figure, curve I is for the N-channel type, and curve 2 is for the P'-channel type. Regarding the curved work in Figure 4, as VRIF and VIN increase, the MOS
This shows that the dirt-source voltage in the FET becomes smaller and the on-resistance RoN increases, and the curve ■
This shows that as vazp and VIN decrease, on-resistance aOX increases. Therefore, VR
As VGII changes in response to changes in IF and VIN, the Zeon resistance ROM also changes. This also holds true even if P-channel type MO8FETs are used for the N-channel MO8FETs 22 and 23).

Conventionally, when each switch 13 is implemented using a C-MOS switch, the chip area becomes large, and two MOS FEs of the same channel type are used.
When implemented with T, there is a drawback that the on-resistance fluctuates significantly and the conversion accuracy decreases.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to provide a digital-to-analog conversion circuit that can reduce the chip area when integrated and maintain high conversion accuracy. It is about providing.

[Summary of the invention]

In order to achieve the above object, the present invention includes a series circuit in which a plurality of first resistors of equivalent value are connected in series and a predetermined potential is applied to one end, one end of the series circuit, the other end, and two same-channel switch MO8FETs whose sources are commonly connected to each series connection point;
Each second resistor inserted between the drain of one of the 2□ MOS FETs and the reference voltage application point, and the drain of the other of the two MOS FETs and the input voltage application point. a fourth resistor inserted between the other end of the series circuit and the reference voltage application point, and a plurality of bits. Each of the above two MOs corresponds to each digital signal.
means for controlling conduction of one of the SFETs, and conduction control of the two MOS FETs whose sources are connected to one end of the series circuit to which the predetermined potential is applied is controlled by a digital signal of the most significant bit. ing.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings. Fifth
The figure is a circuit configuration diagram of an embodiment of a digital-to-analog conversion circuit according to the present invention.

In the figure, a plurality of resistors 11 each having a value R,
11. ... are connected in series to form a series circuit p. A ground potential is applied to one end of this series circuit. Furthermore, one end and the other end of the above series circuit and a resistor 1
Each column contact point of 1 has two N-channel MO8FETs each as a switch, 97. ．． 9. ? sources are commonly connected. MOS FET 3 for each one of the above
1 is connected to one end of each resistor 33 having a value of 2R, and the other end of these resistors 33 is connected to the reference voltage VREI.
Commonly connected to the P application point. MOS of each other above
Each resistor 3 with a value of 2R is also connected to the drain of FET 32.
4 are connected, and the other ends of these resistors 34 are commonly connected to the input voltage VIN application point. Further, a resistor 14 having a value of 2R is connected between the other end of the series circuit and the reference voltage VREF application point.

Two MOSs are located on the leftmost side in the figure, and their sources are connected to one end of the series circuit, that is, to the ground potential point.
One MOS FET 3 among FETs 31 and 32
The dirt of 2 has a multi-bit digital signal D.~D.
-Declaration: The signal of the most significant bit is input. Similarly, a signal 1 is input to ff-) of the other MO8FET 31 via an inverter 35. The above digital signal.

Alternatively, among the two MO8FETs J 1 and 32 that are adjacent to the two MO8FETs 3J and s 2 to which the inverted signal from the inverter 35 is input as a dart, one of the MOS FETs 32 is inserted into the dirt, and the lower bit is also input. A digital signal is input.

Similarly, a signal is input to the other MOS FET 31 via an inverter 35. Similarly, one of the two successively adjacent MO8FETs 31 and 32 receives the digital signal DI (1=3 to
n) is input, and a digital signal Di is input to the dart of the other MOS FET 31 via each inverter 35. Note that in this circuit as well, the values of the reference voltage VIIIF and the input voltage VIN are assumed to be appropriate.

In the D-A converter circuit having the above configuration, if all the digital signals D1 to Dn are currently set to the "0" level, each one of the MOS FETs 31 is turned on, and the current flowing into the series direction path 10 is turned on. are all reference voltages vgg
Flows out from the y application point through each resistor 33. Therefore, in this case, the current flowing out from the point of application of the input voltage VIN is O. On the other hand, if only the most significant bit signal is inverted to the "l#" level, the other MOSFET 32 of the two MOSFETs 31 and 32 controlled by this signal is turned on. The current 11 then flows from the input voltage VIN through the resistor 34. Similarly, if the digital signal of any bit is
When the MOS FIT 32 is turned on by inverting to '1'' level, the corresponding current among the above ■ and ~In becomes the input voltage v
IN flows through each resistor 34. Therefore, in this circuit as well, the digital signal ~Dn is converted into a corresponding analog current.

By the way, in this embodiment circuit, the most significant bit signal D1
Two MOS FETs 31 controlled by.

Since the 32 sources are both connected to the ground potential point, the source potential V is always OV. Also these two M
O8FET, 91. ．． When 92 is turned on, its f-) voltage is set to 1111 lbs, for example 15v. Therefore, even if the reference voltage VflEF and the input voltage VIN vary, the dirt-source voltage vos of the MO8F'ET 31 or 32 remains constant at 5V. In addition, the potentials 2 to Vn at each series connection point and the other end of the resistor 11 in the series circuit length are not Ov, but are sequentially larger values, but each is approximately constant, so each bit signal is
The VGII of each of the two MOS FETs 31 and 32 controlled by Dn also becomes approximately constant.

As a result, even if Vmtr and Vlll fluctuate, the on-resistances of each of the two MO8F'ETs, 91 and 32 do not change significantly and can be kept at a nearly constant value, and vasF and V
Conversion errors due to variations in IN can be made smaller than in the case of the circuit shown in FIG.

In addition, the embodiment circuit with has a resistance of 33 compared to the circuit shown in FIG.
Alternatively, it is necessary to provide an extra 34, but since the element area of the resistor when integrated is generally much smaller than that of a MOS FET, the chip is slightly smaller than when the circuit shown in Figure 3 is integrated. This is the extent to which the area increases. Furthermore, the chip area can be significantly reduced compared to the circuit shown in FIG.

By the way, when the reference voltage VRBF and the input voltage VIN are set to 2.5V and the "1" level of the digital signal is set to 5V, the VOS to which the most significant bit signal D1 is input in the conventional circuit of FIG. FET 2
2 or 23 darts, source voltage VaS is 2.5
It is v. On the other hand, in the above embodiment circuit, when vagr and VIN are set to 2.5V and the 1" level of the digital signal is set to 5V, the MoS FET s1 or 32 to which the most significant bit signal D1 is input
dirt.

The source-to-source voltage VG8 is 5V, which is 2 for the circuit in Figure 3.
The value will be doubled. Similarly, each bit signal Di(1
VOS FET of the circuit shown in Fig. 5 to which =2~n) is input.
VGII of 31 or 32 is the VOS FET in the corresponding circuit of FIG. ? Alternatively, VGII of 23 is also a large value. Therefore, if the dimensions of each element are designed to be the same, MOSFETs 31 and 3 in the circuit of FIG.
The on-resistance value of 2 is the VOS FET in the circuit in Figure 3, ?
2 and 23, and conversely, if the on-resistance is to be the same, MO8FETJ 1 and 32 are MOSFETs, ? The dimensions of elements 2 and 23 can also be made smaller.

FIG. 6 is a circuit diagram of another embodiment of the invention. The difference between this embodiment circuit and the embodiment circuit shown in FIG. 5 is that two N-channel MO8EFTs 31 and 3
The reason is that P-channel MO8FETs 41 and 42 are used instead of MO8FETs 2 and 2. In this case, the power supply potential VDD is applied to one end of the series circuit 10 in place of the ground potential, and each current (I+I, . . . In) flows from VDD toward VRIIP or VIN. Note that vDD is V
It is necessary to have a higher potential than RIF and VIN.

In addition, in the example circuits shown in FIGS.
? , There is no problem if the on-resistance value of 4.2 is set sufficiently large, but these MO
If the on-resistance values of SFETs 31, 32 and 41.42 cannot be ignored, or if higher accuracy is required, the value of each resistor 33.34 can be changed from 2R to MOSFET, 9.
It may be set to a value obtained by subtracting the on-resistance values of J, J2, or 41.42, respectively.

Furthermore, as mentioned above, in the embodiment circuit of FIG.
-Dn is input as a bit signal lower than l.
The VGil of OS FET 31.32 is v.

<vt<vs...<Vn, so Dl is input M
OSFET31, 32 (7) Vas is also small LJ
As J increases, the on-resistance increases successively. Therefore, in order to make the on-resistance values uniform, the element dimensions of the MOSFETs 31 and 32 may be made gradually larger.

By the way, in the example circuit shown in FIG. 5, the value R of the resistor 11 is set to IOKΩ, and the value 2R of the resistor 33 or 34 is set to 20Ω.
, VOS FET B 1 or 320 on resistance value 1
00Ω, Vamp and vIN are 2.5V, then VO
The drain-source voltage VD8 of S FET 31 or 32 is, for example, 12.5 mV.

The VOS value uses a non-saturated region and a region with relatively good linearity in the Vos-Ins characteristic of the MOSFET. This, together with keeping VaS constant, makes the characteristics as a switch more stable.

〔Effect of the invention〕

As explained above, according to the present invention, the source of VOS F'F:T used as a switch is connected to one end, the other end, and each series connection point of a resistor, and this V
Since the voltage between the source and f- of the OS FET is kept constant, it is possible to provide a digital-to-analog conversion circuit that can reduce the chip area when integrated and maintain high conversion accuracy.

[Brief explanation of the drawing]

Figure 1 is a circuit configuration diagram showing the principle of a digital-to-analog conversion circuit using a resistance ladder circuit system, Figures 2i and 3.
The figures are respectively a conventional circuit configuration diagram embodying the above (b) path, FIG. 4 is a characteristic diagram of a VOS FET, FIG. 5 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 6 is a circuit diagram of the present invention. FIG. 3 is a circuit configuration diagram of another embodiment of the present invention. 10...Series circuit, 11...Resistor (first resistor),
14... Resistor (fourth resistor), 31.32... N-channel MO8FET, 33... Resistor (second resistor)
, 34... Resistor (third resistor), 35... Inverter, 41.42-P channel MO8FET. Applicant's agent Patent attorney Takehiko Suzue 2/

Claims (3)

[Claims] (1) A series circuit in which a plurality of first resistors of equivalent value are connected in series and a predetermined potential is applied to one end, and a source is commonly connected to one end, the other end, and each series connection point of the series circuit. MOs for each two identical channel type switches
8FET and each second MO8FFI inserted between the drain of one of the two MO8FFI:Ts and the reference voltage application point.
a resistor of the series circuit, each third resistor having a value equivalent to the second resistor inserted between the drain of the other of the two MO8FF:Ts and the input voltage application point, and A fourth resistor inserted between the other end and the reference voltage application point, and means for controlling conduction of either one of the two MOSFETs in response to each of the plurality of bits of digital signal. A digital-to-analog conversion circuit characterized by: (2) The digital-to-analog conversion circuit according to claim 1, wherein the values of the second, third, and fourth resistors are set to twice the value of the first resistor. (3) The values of the second and third resistors are 2 of the first resistors.
2. The digital-to-analog conversion circuit according to claim 1, wherein the value is set to a value obtained by subtracting the resistance when the MO8FET is conductive from the double value.